About the Execution of LoLA for PermAdmissibility-COL-02
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3611.947 | 236623.00 | 254444.00 | 489.50 | TTFT?FFF?FTTTF?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r137-tall-162089122200469.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is PermAdmissibility-COL-02, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-162089122200469
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 440K
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 106K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 112K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Mar 28 16:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 28 16:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Mar 28 16:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 16:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K Mar 27 06:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K Mar 27 06:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.3K Mar 25 08:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 25 08:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 54K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-02-00
FORMULA_NAME PermAdmissibility-COL-02-01
FORMULA_NAME PermAdmissibility-COL-02-02
FORMULA_NAME PermAdmissibility-COL-02-03
FORMULA_NAME PermAdmissibility-COL-02-04
FORMULA_NAME PermAdmissibility-COL-02-05
FORMULA_NAME PermAdmissibility-COL-02-06
FORMULA_NAME PermAdmissibility-COL-02-07
FORMULA_NAME PermAdmissibility-COL-02-08
FORMULA_NAME PermAdmissibility-COL-02-09
FORMULA_NAME PermAdmissibility-COL-02-10
FORMULA_NAME PermAdmissibility-COL-02-11
FORMULA_NAME PermAdmissibility-COL-02-12
FORMULA_NAME PermAdmissibility-COL-02-13
FORMULA_NAME PermAdmissibility-COL-02-14
FORMULA_NAME PermAdmissibility-COL-02-15
=== Now, execution of the tool begins
BK_START 1620949779015
starting LoLA
BK_INPUT PermAdmissibility-COL-02
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability
FORMULA PermAdmissibility-COL-02-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-02-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620950015638
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: NOTDEADLOCKFREE
lola: start findlow
lola: CHECK FINDLOW FOR TRANS display1
lola: TR BINDINGS
lola: INVENT VAR FOR PLACE c17
lola: INVENT VAR FOR PLACE aux15
lola: INVENT VAR FOR PLACE aux13
lola: CHECK EQ TRANS display1
lola: TR BINDINGS DONE
lola: Places: 208, Transitions: 1024
lola: @ trans switch9
lola: @ trans switch3
lola: @ trans switch4
lola: @ trans display4
lola: CHECK FINDLOW FOR TRANS display2
lola: @ trans display3
lola: @ trans switch7
lola: @ trans switch8
lola: @ trans switch11
lola: INVENT VAR FOR PLACE aux13
lola: INVENT VAR FOR PLACE c18
lola: INVENT VAR FOR PLACE aux15
lola: CHECK EQ TRANS display2
lola: @ trans switch10
lola: @ trans switch2
lola: @ trans switch1
lola: @ trans switch5
lola: @ trans switch12
lola: @ trans display2
lola: @ trans display1
lola: @ trans switch6
lola: CHECK FINDLOW FOR TRANS display3
lola: INVENT VAR FOR PLACE c19
lola: INVENT VAR FOR PLACE aux14
lola: INVENT VAR FOR PLACE aux16
lola: CHECK EQ TRANS display3
lola: CHECK FINDLOW FOR TRANS display4
lola: INVENT VAR FOR PLACE c20
lola: INVENT VAR FOR PLACE aux14
lola: INVENT VAR FOR PLACE aux16
lola: CHECK EQ TRANS display4
lola: CHECK FINDLOW FOR TRANS switch10
lola: INVENT VAR FOR PLACE aux11
lola: INVENT VAR FOR PLACE c14
lola: INVENT VAR FOR PLACE aux9
lola: CHECK EQ TRANS switch10
lola: CHECK FINDLOW FOR TRANS switch11
lola: INVENT VAR FOR PLACE aux12
lola: INVENT VAR FOR PLACE aux10
lola: INVENT VAR FOR PLACE c15
lola: CHECK EQ TRANS switch11
lola: CHECK FINDLOW FOR TRANS switch12
lola: INVENT VAR FOR PLACE aux12
lola: INVENT VAR FOR PLACE aux10
lola: INVENT VAR FOR PLACE c16
lola: CHECK EQ TRANS switch12
lola: CHECK FINDLOW FOR TRANS switch1
lola: INVENT VAR FOR PLACE c5
lola: INVENT VAR FOR PLACE in1
lola: INVENT VAR FOR PLACE in3
lola: CHECK EQ TRANS switch1
lola: CHECK FINDLOW FOR TRANS switch2
lola: INVENT VAR FOR PLACE in1
lola: INVENT VAR FOR PLACE c6
lola: INVENT VAR FOR PLACE in3
lola: CHECK EQ TRANS switch2
lola: CHECK FINDLOW FOR TRANS switch3
lola: INVENT VAR FOR PLACE c7
lola: INVENT VAR FOR PLACE in2
lola: INVENT VAR FOR PLACE in4
lola: CHECK EQ TRANS switch3
lola: CHECK FINDLOW FOR TRANS switch4
lola: INVENT VAR FOR PLACE c8
lola: INVENT VAR FOR PLACE in2
lola: INVENT VAR FOR PLACE in4
lola: CHECK EQ TRANS switch4
lola: CHECK FINDLOW FOR TRANS switch5
lola: INVENT VAR FOR PLACE c9
lola: INVENT VAR FOR PLACE aux7
lola: INVENT VAR FOR PLACE aux5
lola: CHECK EQ TRANS switch5
lola: CHECK FINDLOW FOR TRANS switch6
lola: INVENT VAR FOR PLACE c110
lola: INVENT VAR FOR PLACE aux7
lola: INVENT VAR FOR PLACE aux5
lola: CHECK EQ TRANS switch6
lola: CHECK FINDLOW FOR TRANS switch7
lola: INVENT VAR FOR PLACE c11
lola: INVENT VAR FOR PLACE aux8
lola: INVENT VAR FOR PLACE aux6
lola: CHECK EQ TRANS switch7
lola: CHECK FINDLOW FOR TRANS switch8
lola: INVENT VAR FOR PLACE aux6
lola: INVENT VAR FOR PLACE aux8
lola: INVENT VAR FOR PLACE c12
lola: CHECK EQ TRANS switch8
lola: CHECK FINDLOW FOR TRANS switch9
lola: INVENT VAR FOR PLACE aux11
lola: INVENT VAR FOR PLACE aux9
lola: INVENT VAR FOR PLACE c13
lola: CHECK EQ TRANS switch9
lola: findlow criterion satisfied
lola: Time for checking findlow: 1.000000
lola: TRANS 0: display1 is minimal, eq to 0
lola: TRANS 1: display2 is minimal, eq to 1
lola: TRANS 2: display3 is minimal, eq to 2
lola: TRANS 3: display4 is minimal, eq to 3
lola: TRANS 4: switch10 is minimal, eq to 4
lola: TRANS 5: switch11 is minimal, eq to 5
lola: TRANS 6: switch12 is minimal, eq to 6
lola: TRANS 7: switch1 is minimal, eq to 7
lola: TRANS 8: switch2 is minimal, eq to 8
lola: TRANS 9: switch3 is minimal, eq to 9
lola: TRANS 10: switch4 is minimal, eq to 10
lola: TRANS 11: switch5 is minimal, eq to 11
lola: TRANS 12: switch6 is minimal, eq to 12
lola: TRANS 13: switch7 is minimal, eq to 13
lola: TRANS 14: switch8 is minimal, eq to 14
lola: TRANS 15: switch9 is minimal, eq to 15
lola: HLFINDLOW
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-02-00: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-02: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-02-03: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-02-06: AG 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-07: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-08: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-09: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-11: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-02-12: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PermAdmissibility-COL-02-00: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-02: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-02-03: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-02-06: AG 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-07: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-08: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-09: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-11: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-02-12: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PermAdmissibility-COL-02-00: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-02: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-02-03: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-02-06: AG 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-07: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-08: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-09: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-11: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-02-12: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PermAdmissibility-COL-02-00: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-02: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-02-03: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-02-06: AG 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-07: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-08: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-09: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-11: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-02-12: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-02-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 14 (type EXCL) for 13 PermAdmissibility-COL-02-03
lola: time limit : 420 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for PermAdmissibility-COL-02-03
lola: result : true
lola: markings : 12473
lola: fired transitions : 21084
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 6 PermAdmissibility-COL-02-02
lola: time limit : 480 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for PermAdmissibility-COL-02-02
lola: result : false
lola: markings : 6833
lola: fired transitions : 10579
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 PermAdmissibility-COL-02-01
lola: time limit : 673 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for PermAdmissibility-COL-02-01
lola: result : true
lola: markings : 433
lola: fired transitions : 764
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 PermAdmissibility-COL-02-00
lola: time limit : 841 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for PermAdmissibility-COL-02-00
lola: result : true
lola: markings : 321029
lola: fired transitions : 596504
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 24 (type EXCL) for 19 PermAdmissibility-COL-02-05
lola: time limit : 1121 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for PermAdmissibility-COL-02-05
lola: result : false
lola: markings : 34
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 PermAdmissibility-COL-02-10
lola: time limit : 3364 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for PermAdmissibility-COL-02-10
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
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PermAdmissibility-COL-02-00: LTL true LTL model checker
PermAdmissibility-COL-02-01: LTL true LTL model checker
PermAdmissibility-COL-02-02: CONJ false LTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-02"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-02, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-162089122200469"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-02.tgz
mv PermAdmissibility-COL-02 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;