fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r118-tall-162075403300634
Last Updated
Jun 28, 2021

About the Execution of LoLA for LamportFastMutEx-COL-8

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1109.907 335343.00 336904.00 557.80 FTTTTFTFT??FFFFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r118-tall-162075403300634.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is LamportFastMutEx-COL-8, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r118-tall-162075403300634
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 412K
-rw-r--r-- 1 mcc users 19K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 144K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 26 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 26 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 26 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 26 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Mar 27 06:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 06:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Mar 25 07:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 25 07:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 2 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 44K May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-00
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-01
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-02
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-03
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-04
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-05
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-06
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-07
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-08
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-09
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-10
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-11
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-12
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-13
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-14
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1620825474918

starting LoLA
BK_INPUT LamportFastMutEx-COL-8
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA LamportFastMutEx-COL-8-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-8-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620825810261

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: TR BINDINGS
lola: TR BINDINGS DONE
lola: Places: 315, Transitions: 666
lola: @ trans T-setbi_24
lola: @ trans T-yne0_4
lola: @ trans T-fordo_12
lola: @ trans T-xeqi_10
lola: @ trans T-sety_9
lola: @ trans T-setbi_2
lola: @ trans T-awaity
lola: @ trans T-setbi_11
lola: @ trans T-ynei_15
lola: @ trans T-forod_13
lola: @ trans T-setbi_5
lola: @ trans T-xnei_10
lola: @ trans T-await_13
lola: @ trans T-yeq0_4
lola: @ trans T-yeqi_15
lola: @ trans T-sety0_23
lola: @ trans T-setx_3
lola: LAUNCH INITIAL
lola: LAUNCH task # 2 (type SKEL/CNST) for 0 LamportFastMutEx-COL-8-CTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 5 (type SKEL/CNST) for 3 LamportFastMutEx-COL-8-CTLFireability-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 11 (type SKEL/CNST) for 9 LamportFastMutEx-COL-8-CTLFireability-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 14 (type SKEL/CNST) for 12 LamportFastMutEx-COL-8-CTLFireability-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 17 (type SKEL/CNST) for 15 LamportFastMutEx-COL-8-CTLFireability-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 20 (type SKEL/CNST) for 18 LamportFastMutEx-COL-8-CTLFireability-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 23 (type SKEL/CNST) for 21 LamportFastMutEx-COL-8-CTLFireability-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 39 (type SKEL/CNST) for 37 LamportFastMutEx-COL-8-CTLFireability-11
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 42 (type SKEL/CNST) for 40 LamportFastMutEx-COL-8-CTLFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 48 (type SKEL/CNST) for 46 LamportFastMutEx-COL-8-CTLFireability-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 LamportFastMutEx-COL-8-CTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 4 (type CNST) for 3 LamportFastMutEx-COL-8-CTLFireability-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 10 (type CNST) for 9 LamportFastMutEx-COL-8-CTLFireability-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 13 (type CNST) for 12 LamportFastMutEx-COL-8-CTLFireability-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 5 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-01
lola: result : true
lola: LAUNCH INITIAL
lola: LAUNCH task # 16 (type CNST) for 15 LamportFastMutEx-COL-8-CTLFireability-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: CANCELED task # 4 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-01 (obsolete)
lola: FINISHED task # 17 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-05
lola: result : false
lola: FINISHED task # 11 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-03
lola: result : true
lola: FINISHED task # 23 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-07
lola: result : false
lola: FINISHED task # 20 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-06
lola: result : true
lola: FINISHED task # 42 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-12
lola: result : false
lola: FINISHED task # 48 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-14
lola: result : false
lola: FINISHED task # 2 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-00
lola: result : false
lola: FINISHED task # 1 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-00
lola: result : false
lola: FINISHED task # 4 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-01
lola: result : true
lola: FINISHED task # 39 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-11
lola: result : false
lola: FINISHED task # 13 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-04
lola: result : true
lola: FINISHED task # 10 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-03
lola: result : true
lola: FINISHED task # 14 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-04
lola: result : true
lola: CANCELED task # 16 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-05 (obsolete)
lola: FINISHED task # 16 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-05
lola: result : false
lola: LAUNCH INITIAL
lola: LAUNCH task # 32 (type CNST) for 27 LamportFastMutEx-COL-8-CTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: Rule S: 82 transitions removed,49 places removed
lola: LAUNCH task # 44 (type CNST) for 43 LamportFastMutEx-COL-8-CTLFireability-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 32 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-09
lola: result : true
lola: FINISHED task # 44 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-13
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 52 (type EXCL) for 27 LamportFastMutEx-COL-8-CTLFireability-09
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:779
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 5/719 2/32 LamportFastMutEx-COL-8-CTLFireability-09 225101 m, 45020 m/sec, 1728950 t fired, .

Time elapsed: 6 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 10/719 3/32 LamportFastMutEx-COL-8-CTLFireability-09 461090 m, 47197 m/sec, 3596535 t fired, .

Time elapsed: 11 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 15/719 4/32 LamportFastMutEx-COL-8-CTLFireability-09 683181 m, 44418 m/sec, 5275631 t fired, .

Time elapsed: 16 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 20/719 5/32 LamportFastMutEx-COL-8-CTLFireability-09 877306 m, 38825 m/sec, 6880632 t fired, .

Time elapsed: 21 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 25/719 6/32 LamportFastMutEx-COL-8-CTLFireability-09 1050600 m, 34658 m/sec, 8328778 t fired, .

Time elapsed: 26 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 30/719 7/32 LamportFastMutEx-COL-8-CTLFireability-09 1216400 m, 33160 m/sec, 9811070 t fired, .

Time elapsed: 31 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 35/719 8/32 LamportFastMutEx-COL-8-CTLFireability-09 1375513 m, 31822 m/sec, 11259746 t fired, .

Time elapsed: 36 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 40/719 8/32 LamportFastMutEx-COL-8-CTLFireability-09 1516340 m, 28165 m/sec, 12648017 t fired, .

Time elapsed: 41 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 45/719 9/32 LamportFastMutEx-COL-8-CTLFireability-09 1687447 m, 34221 m/sec, 14133246 t fired, .

Time elapsed: 46 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 50/719 10/32 LamportFastMutEx-COL-8-CTLFireability-09 1851926 m, 32895 m/sec, 15653593 t fired, .

Time elapsed: 51 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 55/719 11/32 LamportFastMutEx-COL-8-CTLFireability-09 1999114 m, 29437 m/sec, 17078815 t fired, .

Time elapsed: 56 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 60/719 12/32 LamportFastMutEx-COL-8-CTLFireability-09 2143186 m, 28814 m/sec, 18521255 t fired, .

Time elapsed: 61 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 65/719 12/32 LamportFastMutEx-COL-8-CTLFireability-09 2282531 m, 27869 m/sec, 19939263 t fired, .

Time elapsed: 66 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 70/719 13/32 LamportFastMutEx-COL-8-CTLFireability-09 2409464 m, 25386 m/sec, 21266139 t fired, .

Time elapsed: 71 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 75/719 14/32 LamportFastMutEx-COL-8-CTLFireability-09 2578632 m, 33833 m/sec, 22754957 t fired, .

Time elapsed: 76 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 80/719 15/32 LamportFastMutEx-COL-8-CTLFireability-09 2754504 m, 35174 m/sec, 24290952 t fired, .

Time elapsed: 81 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 85/719 15/32 LamportFastMutEx-COL-8-CTLFireability-09 2917696 m, 32638 m/sec, 25794214 t fired, .

Time elapsed: 86 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 90/719 16/32 LamportFastMutEx-COL-8-CTLFireability-09 3086827 m, 33826 m/sec, 27325935 t fired, .

Time elapsed: 91 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 95/719 17/32 LamportFastMutEx-COL-8-CTLFireability-09 3237654 m, 30165 m/sec, 28798791 t fired, .

Time elapsed: 96 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 100/719 17/32 LamportFastMutEx-COL-8-CTLFireability-09 3379023 m, 28273 m/sec, 30255567 t fired, .

Time elapsed: 101 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 105/719 18/32 LamportFastMutEx-COL-8-CTLFireability-09 3557384 m, 35672 m/sec, 31827773 t fired, .

Time elapsed: 106 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 110/719 19/32 LamportFastMutEx-COL-8-CTLFireability-09 3722816 m, 33086 m/sec, 33390588 t fired, .

Time elapsed: 111 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 115/719 20/32 LamportFastMutEx-COL-8-CTLFireability-09 3880829 m, 31602 m/sec, 34930089 t fired, .

Time elapsed: 116 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 120/719 21/32 LamportFastMutEx-COL-8-CTLFireability-09 4030869 m, 30008 m/sec, 36449176 t fired, .

Time elapsed: 121 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 125/719 22/32 LamportFastMutEx-COL-8-CTLFireability-09 4164274 m, 26681 m/sec, 37903644 t fired, .

Time elapsed: 126 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 130/719 22/32 LamportFastMutEx-COL-8-CTLFireability-09 4323245 m, 31794 m/sec, 39464787 t fired, .

Time elapsed: 131 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 135/719 23/32 LamportFastMutEx-COL-8-CTLFireability-09 4469798 m, 29310 m/sec, 40997140 t fired, .

Time elapsed: 136 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 140/719 24/32 LamportFastMutEx-COL-8-CTLFireability-09 4607743 m, 27589 m/sec, 42489066 t fired, .

Time elapsed: 141 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 145/719 25/32 LamportFastMutEx-COL-8-CTLFireability-09 4744554 m, 27362 m/sec, 43989424 t fired, .

Time elapsed: 146 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 150/719 25/32 LamportFastMutEx-COL-8-CTLFireability-09 4867907 m, 24670 m/sec, 45396924 t fired, .

Time elapsed: 151 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 155/719 26/32 LamportFastMutEx-COL-8-CTLFireability-09 5012332 m, 28885 m/sec, 46911444 t fired, .

Time elapsed: 156 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 160/719 27/32 LamportFastMutEx-COL-8-CTLFireability-09 5182635 m, 34060 m/sec, 48537073 t fired, .

Time elapsed: 161 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 165/719 27/32 LamportFastMutEx-COL-8-CTLFireability-09 5336584 m, 30789 m/sec, 50121514 t fired, .

Time elapsed: 166 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 170/719 28/32 LamportFastMutEx-COL-8-CTLFireability-09 5493247 m, 31332 m/sec, 51706294 t fired, .

Time elapsed: 171 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 175/719 29/32 LamportFastMutEx-COL-8-CTLFireability-09 5636059 m, 28562 m/sec, 53252726 t fired, .

Time elapsed: 176 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 180/719 29/32 LamportFastMutEx-COL-8-CTLFireability-09 5769188 m, 26625 m/sec, 54751292 t fired, .

Time elapsed: 181 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 185/719 30/32 LamportFastMutEx-COL-8-CTLFireability-09 5953271 m, 36816 m/sec, 56372665 t fired, .

Time elapsed: 186 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 190/719 31/32 LamportFastMutEx-COL-8-CTLFireability-09 6112050 m, 31755 m/sec, 57885898 t fired, .

Time elapsed: 191 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 195/719 32/32 LamportFastMutEx-COL-8-CTLFireability-09 6268592 m, 31308 m/sec, 59397708 t fired, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 53 (type EXCL) for 34 LamportFastMutEx-COL-8-CTLFireability-10
lola: time limit : 849 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 5/849 2/32 LamportFastMutEx-COL-8-CTLFireability-10 255762 m, 51152 m/sec, 580687 t fired, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 10/849 3/32 LamportFastMutEx-COL-8-CTLFireability-10 508524 m, 50552 m/sec, 1195778 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 15/849 4/32 LamportFastMutEx-COL-8-CTLFireability-10 761195 m, 50534 m/sec, 1834858 t fired, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 20/849 5/32 LamportFastMutEx-COL-8-CTLFireability-10 1015565 m, 50874 m/sec, 2478644 t fired, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 25/849 7/32 LamportFastMutEx-COL-8-CTLFireability-10 1267664 m, 50419 m/sec, 3154315 t fired, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 30/849 8/32 LamportFastMutEx-COL-8-CTLFireability-10 1518679 m, 50203 m/sec, 3802041 t fired, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 35/849 9/32 LamportFastMutEx-COL-8-CTLFireability-10 1767993 m, 49862 m/sec, 4462297 t fired, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 40/849 10/32 LamportFastMutEx-COL-8-CTLFireability-10 2016957 m, 49792 m/sec, 5125546 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 45/849 11/32 LamportFastMutEx-COL-8-CTLFireability-10 2275848 m, 51778 m/sec, 5827731 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 50/849 13/32 LamportFastMutEx-COL-8-CTLFireability-10 2530692 m, 50968 m/sec, 6524346 t fired, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 55/849 14/32 LamportFastMutEx-COL-8-CTLFireability-10 2787720 m, 51405 m/sec, 7254157 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 60/849 15/32 LamportFastMutEx-COL-8-CTLFireability-10 3044629 m, 51381 m/sec, 7941580 t fired, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 65/849 16/32 LamportFastMutEx-COL-8-CTLFireability-10 3296839 m, 50442 m/sec, 8655059 t fired, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 70/849 17/32 LamportFastMutEx-COL-8-CTLFireability-10 3551278 m, 50887 m/sec, 9351689 t fired, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 75/849 19/32 LamportFastMutEx-COL-8-CTLFireability-10 3803459 m, 50436 m/sec, 10041655 t fired, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 80/849 20/32 LamportFastMutEx-COL-8-CTLFireability-10 4058978 m, 51103 m/sec, 10744991 t fired, .

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 85/849 21/32 LamportFastMutEx-COL-8-CTLFireability-10 4314772 m, 51158 m/sec, 11447501 t fired, .

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 90/849 22/32 LamportFastMutEx-COL-8-CTLFireability-10 4567245 m, 50494 m/sec, 12122885 t fired, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 95/849 23/32 LamportFastMutEx-COL-8-CTLFireability-10 4828023 m, 52155 m/sec, 12824390 t fired, .

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 100/849 25/32 LamportFastMutEx-COL-8-CTLFireability-10 5089088 m, 52213 m/sec, 13548602 t fired, .

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 105/849 26/32 LamportFastMutEx-COL-8-CTLFireability-10 5342898 m, 50762 m/sec, 14272953 t fired, .

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 110/849 27/32 LamportFastMutEx-COL-8-CTLFireability-10 5596786 m, 50777 m/sec, 14989100 t fired, .

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 115/849 28/32 LamportFastMutEx-COL-8-CTLFireability-10 5847857 m, 50214 m/sec, 15736985 t fired, .

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 120/849 29/32 LamportFastMutEx-COL-8-CTLFireability-10 6098731 m, 50174 m/sec, 16468696 t fired, .

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 125/849 30/32 LamportFastMutEx-COL-8-CTLFireability-10 6346297 m, 49513 m/sec, 17166790 t fired, .

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 130/849 32/32 LamportFastMutEx-COL-8-CTLFireability-10 6599498 m, 50640 m/sec, 17891881 t fired, .

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 53 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 LamportFastMutEx-COL-8-CTLFireability-08
lola: time limit : 1088 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 49 LamportFastMutEx-COL-8-CTLFireability-15
lola: time limit : 1632 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-15
lola: result : false
lola: markings : 256
lola: fired transitions : 1024
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 LamportFastMutEx-COL-8-CTLFireability-02
lola: time limit : 3264 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-02
lola: result : true
lola: markings : 15
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-02: EG true state space / EG
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-COL-8-CTLFireability-09: CONJ unknown CONJ
LamportFastMutEx-COL-8-CTLFireability-10: AXAG unknown AGGR
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-15: F true state space / EG


Time elapsed: 336 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-8"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is LamportFastMutEx-COL-8, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r118-tall-162075403300634"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-8.tgz
mv LamportFastMutEx-COL-8 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;