About the Execution of LoLA for FamilyReunion-PT-L00010M0001C001P001G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 10137.136 | 3600000.00 | 7479257.00 | 10848.50 | ?????FT?T?F????T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r080-tall-162048871600938.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is FamilyReunion-PT-L00010M0001C001P001G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r080-tall-162048871600938
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.2M
-rw-r--r-- 1 mcc users 77K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 526K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 157K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 591K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 9.2K Mar 28 16:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 48K Mar 28 16:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 16K Mar 28 16:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 52K Mar 28 16:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.2K Mar 23 10:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 40K Mar 23 10:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Mar 22 18:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 48K Mar 22 18:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.6K Mar 22 09:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.0K Mar 22 09:11 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 24 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 552K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620790536301
starting LoLA
BK_INPUT FamilyReunion-PT-L00010M0001C001P001G001
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: RELEASE
lola: LAUNCH task # 57 (type SKEL/FNDP) for 24 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SKEL/EQUN) for 24 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SKEL/SRCH) for 24 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 60 (type SKEL/SRCH) for 24 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 57 (type SKEL/FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: result : true
lola: fired transitions : 29
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 58 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08 (obsolete)
lola: CANCELED task # 59 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08 (obsolete)
lola: CANCELED task # 60 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/CTLFireability-58.sara.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 58 (type SKEL/EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: result : true
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF 0 0 0 0 2 0 0 2
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ 0 0 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 856 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 63 (type EXCL) for 24 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: time limit : 137 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 61 (type FNDP) for 24 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 24 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 24 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: try reading problem file /home/mcc/execution/CTLFireability-62.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 63 (type EXCL) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: result : true
lola: markings : 22
lola: fired transitions : 21
lola: time used : 6.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 61 (type FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: result : true
lola: fired transitions : 20
lola: tried executions : 1
lola: time used : 6.000000
lola: memory pages used : 0
lola: FINISHED task # 64 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: result : unknown
lola: time used : 7.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF 0 0 1 0 5 0 0 2
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 1 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 1 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 1 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ 0 4 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF STEQ 7/1365 0/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08 sara is running.
Time elapsed: 864 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: CANCELED task # 62 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08 (obsolete)
lola: LAUNCH task # 40 (type EXCL) for 39 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13
lola: time limit : 160 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 65 (type FNDP) for 45 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type EQUN) for 45 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SRCH) for 45 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 62 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 65 (type FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 66 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15 (obsolete)
lola: CANCELED task # 68 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15 (obsolete)
lola: FINISHED task # 68 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-66.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 1 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 1 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 1 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 1 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 1 0 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 3/195 1/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 13766 m, 2753 m/sec, 21187 t fired, .
Time elapsed: 869 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 66 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:715
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 8/195 1/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 58604 m, 8967 m/sec, 97291 t fired, .
Time elapsed: 874 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 13/195 1/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 102284 m, 8736 m/sec, 173522 t fired, .
Time elapsed: 879 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 18/195 2/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 144201 m, 8383 m/sec, 249348 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 73/195 5/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 591305 m, 8514 m/sec, 1097268 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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40 CTL EXCL 128/195 7/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 989717 m, 8307 m/sec, 1952135 t fired, .
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40 CTL EXCL 179/195 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 1369051 m, 7475 m/sec, 2731225 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 184/195 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 1403015 m, 6792 m/sec, 2811725 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 189/195 10/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 1434464 m, 6289 m/sec, 2888779 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 194/195 10/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 1466419 m, 6391 m/sec, 2969796 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/195 1/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 41113 m, 8222 m/sec, 76241 t fired, .
40 CTL EXCL 5/2535 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 43550 m, -284573 m/sec, 72251 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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37 CTL EXCL 10/195 1/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 73537 m, 6484 m/sec, 157817 t fired, .
40 CTL EXCL 10/181 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 89234 m, 9136 m/sec, 150955 t fired, .
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37 CTL EXCL 15/195 1/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 104815 m, 6255 m/sec, 238812 t fired, .
40 CTL EXCL 15/181 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 133209 m, 8795 m/sec, 227575 t fired, .
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37 CTL EXCL 20/195 1/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 131411 m, 5319 m/sec, 318875 t fired, .
40 CTL EXCL 20/181 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 171602 m, 7678 m/sec, 305489 t fired, .
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37 CTL EXCL 25/195 2/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 165565 m, 6830 m/sec, 401028 t fired, .
40 CTL EXCL 25/181 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 211382 m, 7956 m/sec, 381613 t fired, .
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40 CTL EXCL 30/181 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 250949 m, 7913 m/sec, 460053 t fired, .
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37 CTL EXCL 35/195 2/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 240132 m, 7541 m/sec, 563686 t fired, .
40 CTL EXCL 35/181 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 288508 m, 7511 m/sec, 539253 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 40/195 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 273137 m, 6601 m/sec, 643503 t fired, .
40 CTL EXCL 40/181 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 326659 m, 7630 m/sec, 616948 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 45/195 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 298099 m, 4992 m/sec, 723690 t fired, .
40 CTL EXCL 45/181 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 372054 m, 9079 m/sec, 691245 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 50/195 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 318607 m, 4101 m/sec, 795408 t fired, .
40 CTL EXCL 50/181 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 410376 m, 7664 m/sec, 765419 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 55/195 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 340652 m, 4409 m/sec, 869014 t fired, .
40 CTL EXCL 55/181 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 453065 m, 8537 m/sec, 841910 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 60/195 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 363665 m, 4602 m/sec, 946367 t fired, .
40 CTL EXCL 60/181 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 495644 m, 8515 m/sec, 922007 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 65/195 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 389738 m, 5214 m/sec, 1024166 t fired, .
40 CTL EXCL 65/181 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 538151 m, 8501 m/sec, 1004911 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 70/195 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 413495 m, 4751 m/sec, 1098778 t fired, .
40 CTL EXCL 70/181 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 584942 m, 9358 m/sec, 1085103 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 75/195 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 437112 m, 4723 m/sec, 1173158 t fired, .
40 CTL EXCL 75/181 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 624853 m, 7982 m/sec, 1165773 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 80/195 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 460077 m, 4593 m/sec, 1248701 t fired, .
40 CTL EXCL 80/181 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 660822 m, 7193 m/sec, 1245553 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 85/195 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 482825 m, 4549 m/sec, 1325588 t fired, .
40 CTL EXCL 85/181 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 700076 m, 7850 m/sec, 1330184 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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37 CTL EXCL 90/195 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 514241 m, 6283 m/sec, 1405065 t fired, .
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37 CTL EXCL 5/2335 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 40263 m, -213457 m/sec, 75066 t fired, .
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37 CTL EXCL 10/179 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 72139 m, 6375 m/sec, 153741 t fired, .
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34 CTL EXCL 15/194 2/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 144292 m, 8283 m/sec, 229383 t fired, .
37 CTL EXCL 15/179 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 101453 m, 5862 m/sec, 230297 t fired, .
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37 CTL EXCL 20/179 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 127394 m, 5188 m/sec, 307161 t fired, .
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37 CTL EXCL 25/179 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 158050 m, 6131 m/sec, 385488 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 55/194 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 498299 m, 8479 m/sec, 821299 t fired, .
37 CTL EXCL 55/179 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 340603 m, 4903 m/sec, 868849 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 60/194 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 541349 m, 8610 m/sec, 894133 t fired, .
37 CTL EXCL 60/179 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 363301 m, 4539 m/sec, 945116 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 65/194 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 580578 m, 7845 m/sec, 966078 t fired, .
37 CTL EXCL 65/179 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 390240 m, 5387 m/sec, 1025485 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 70/194 5/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 619770 m, 7838 m/sec, 1042555 t fired, .
37 CTL EXCL 70/179 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 414469 m, 4845 m/sec, 1102138 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 75/194 5/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 665866 m, 9219 m/sec, 1118928 t fired, .
37 CTL EXCL 75/179 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 438718 m, 4849 m/sec, 1176862 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 80/194 5/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 710799 m, 8986 m/sec, 1198391 t fired, .
37 CTL EXCL 80/179 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 462322 m, 4720 m/sec, 1257062 t fired, .
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34 CTL EXCL 85/194 5/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 756566 m, 9153 m/sec, 1274428 t fired, .
37 CTL EXCL 85/179 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 488069 m, 5149 m/sec, 1340386 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 90/194 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 795986 m, 7884 m/sec, 1345716 t fired, .
37 CTL EXCL 90/179 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 521492 m, 6684 m/sec, 1419340 t fired, .
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34 CTL EXCL 95/194 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 832061 m, 7215 m/sec, 1408492 t fired, .
37 CTL EXCL 95/179 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 551970 m, 6095 m/sec, 1487961 t fired, .
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34 CTL EXCL 100/194 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 866690 m, 6925 m/sec, 1475650 t fired, .
37 CTL EXCL 100/179 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 585787 m, 6763 m/sec, 1564325 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 105/194 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 903204 m, 7302 m/sec, 1553479 t fired, .
37 CTL EXCL 105/179 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 612031 m, 5248 m/sec, 1638230 t fired, .
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34 CTL EXCL 110/194 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 940994 m, 7558 m/sec, 1632089 t fired, .
37 CTL EXCL 110/179 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 635704 m, 4734 m/sec, 1715223 t fired, .
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37 CTL EXCL 115/179 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 660808 m, 5020 m/sec, 1795532 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 120/194 7/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1024803 m, 8274 m/sec, 1777297 t fired, .
37 CTL EXCL 120/179 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 688422 m, 5522 m/sec, 1879947 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 125/194 7/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1067905 m, 8620 m/sec, 1849313 t fired, .
37 CTL EXCL 125/179 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12 711605 m, 4636 m/sec, 1959432 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 130/194 7/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1110090 m, 8437 m/sec, 1923629 t fired, .
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34 CTL EXCL 145/194 8/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1243964 m, 8940 m/sec, 2153359 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 161/194 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1374949 m, 8835 m/sec, 2380051 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 166/194 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1417302 m, 8470 m/sec, 2457887 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 171/194 10/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1457846 m, 8108 m/sec, 2536810 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 176/194 10/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1499768 m, 8384 m/sec, 2608395 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 181/194 10/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1546738 m, 9394 m/sec, 2687558 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 191/194 11/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1642616 m, 9827 m/sec, 2849326 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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34 CTL EXCL 5/194 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 51455 m, -318232 m/sec, 76980 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/194 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 105831 m, 10875 m/sec, 161308 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/194 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 148778 m, 8589 m/sec, 237088 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/194 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 194673 m, 9179 m/sec, 314581 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/204 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07 125838 m, 12085 m/sec, 153039 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/204 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07 187252 m, 12282 m/sec, 232523 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 18/258 1/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04 79107 m, 4089 m/sec, 285109 t fired, .
Time elapsed: 1811 secs. Pages in use: 90
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: AGEF 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00010M0001C001P001G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is FamilyReunion-PT-L00010M0001C001P001G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r080-tall-162048871600938"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00010M0001C001P001G001.tgz
mv FamilyReunion-PT-L00010M0001C001P001G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;