About the Execution of LoLA for FamilyReunion-COL-L00020M0002C001P001G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2898.544 | 535590.00 | 551828.00 | 839.70 | FFFTFF?FFF?FTF?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r080-tall-162048871500852.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is FamilyReunion-COL-L00020M0002C001P001G001, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r080-tall-162048871500852
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 112K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 16K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 79K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 16:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 28 16:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Mar 28 16:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 16:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 23 10:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 23 10:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.0K Mar 22 18:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 22 18:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Mar 22 09:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Mar 22 09:11 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 24 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 135K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-00
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-01
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-02
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-03
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-04
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-05
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-06
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-07
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-08
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-09
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-10
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-11
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-12
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-13
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-14
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-15
=== Now, execution of the tool begins
BK_START 1620567010135
starting LoLA
BK_INPUT FamilyReunion-COL-L00020M0002C001P001G001
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLCardinality
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620567545725
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:141
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:184
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: start findlow
lola: CHECK FINDLOW FOR TRANS Gate2ANDJoin
lola: INVENT VAR FOR PLACE l29
lola: INVENT VAR FOR PLACE l27
lola: INVENT VAR FOR PLACE l26
lola: INVENT VAR FOR PLACE l28
lola: CHECK EQ TRANS Gate2ANDJoin
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: LAUNCH INITIAL
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: TR BINDINGS
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 2 (type SKEL/CNST) for 0 FamilyReunion-COL-L00020M0002C001P001G001-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: findlow criterion violated for transition 59
lola: LAUNCH task # 27 (type SKEL/CNST) for 25 FamilyReunion-COL-L00020M0002C001P001G001-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH INITIAL
lola: LAUNCH task # 42 (type SKEL/CNST) for 38 FamilyReunion-COL-L00020M0002C001P001G001-10
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 66 (type SKEL/FNDP) for 6 FamilyReunion-COL-L00020M0002C001P001G001-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 42 (type SKEL/CNST) for FamilyReunion-COL-L00020M0002C001P001G001-10
lola: result : true
lola: LAUNCH task # 72 (type SKEL/FNDP) for 45 FamilyReunion-COL-L00020M0002C001P001G001-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 2 (type SKEL/CNST) for FamilyReunion-COL-L00020M0002C001P001G001-00
lola: result : false
lola: FINISHED task # 27 (type SKEL/CNST) for FamilyReunion-COL-L00020M0002C001P001G001-07
lola: result : false
lola: LAUNCH task # 67 (type SKEL/EQUN) for 6 FamilyReunion-COL-L00020M0002C001P001G001-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SKEL/SRCH) for 6 FamilyReunion-COL-L00020M0002C001P001G001-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 68 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-02
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 66 (type FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-02 (obsolete)
lola: CANCELED task # 67 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-02 (obsolete)
lola: LAUNCH task # 73 (type SKEL/EQUN) for 45 FamilyReunion-COL-L00020M0002C001P001G001-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SKEL/SRCH) for 45 FamilyReunion-COL-L00020M0002C001P001G001-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 75 (type SKEL/SRCH) for 45 FamilyReunion-COL-L00020M0002C001P001G001-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: CHECK FINDLOW FOR TRANS GotIt
lola: FINISHED task # 72 (type SKEL/FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-11
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 75 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-11
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 74 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-11
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/LTLCardinality-67.sara.
lola: CANCELED task # 73 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-11 (obsolete)
lola: FINISHED task # 66 (type SKEL/FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 73 (type SKEL/EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-11
lola: result : unknown
lola: TR BINDINGS DONE
lola: Places: 3292, Transitions: 2753
lola: FINISHED task # 67 (type SKEL/EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-02
lola: result : true
lola: INVENT VAR FOR PLACE lc0
lola: INVENT VAR FOR PLACE cl1
lola: CHECK EQ TRANS GotIt
lola: @ trans RegisterRelativePubHealth
lola: @ trans Gate1XORSplit
lola: @ trans ObtainMissingDocs
lola: @ trans DisplayReqDocs
lola: @ trans Gate2ANDJoin
lola: @ trans SummonApplicant
lola: @ trans GotIt
lola: @ trans Gate3XORSplit
lola: @ trans HousingSuitCertifObtained
lola: @ trans CheckRequiredDoc
lola: @ trans ReceiveRegsitration
lola: @ trans ProvidePersonalnfo
lola: @ trans AppReqReceived
lola: @ trans ReserveAppoint
lola: @ trans SendClearanceToRel
lola: @ trans SendLangChoice
lola: @ trans ObtainRelativeFinStatement
lola: @ trans TransmitReq
lola: @ trans TickDocsObtained
lola: @ trans ReceiveAccessReq
lola: @ trans ReceiveLangChoice
lola: @ trans ReqHousingSuitCertif
lola: @ trans BringReqtoCINFORMI
lola: @ trans ExplainHowToObtainMissingDocs
lola: @ trans SendSuitabilityCertif
lola: @ trans EvaluateReq
lola: @ trans CheckHousingSuitReq
lola: findlow criterion violated for transition 64
lola: @ trans ReceiveAppoint
lola: @ trans DisplayLangChoice
lola: @ trans Gate1ANDJoin
lola: @ trans Gate2XORSplit
lola: @ trans RegisterRelative
lola: @ trans Summoned
lola: @ trans PrepIncomeCertif
lola: @ trans Gate1ANDSplit
lola: @ trans ReceiveQuestion
lola: @ trans RespReceived
lola: @ trans PrepFamReuClearReq
lola: @ trans ReqAppointCINFORMI
lola: @ trans GoToAppoint
lola: @ trans GotoOSSAndProdDoc
lola: @ trans ArchiveReq
lola: @ trans Gate2ANDSplit
lola: @ trans ReceiveDocsObtained
lola: @ trans AppointReceived
lola: @ trans CheckSanityReq
lola: @ trans ReceiveInstructions
lola: @ trans AccessMicTerminal
lola: @ trans SetUpAppoint
lola: @ trans ReceiveReqDocsReq
lola: @ trans ReceiveLangReq
lola: CHECK FINDLOW FOR TRANS HousingSuitCertifObtained
lola: @ trans CommunicateResp
lola: @ trans ObtainRelHealtCondStatement
lola: @ trans GiveAppoint
lola: @ trans ReserveAppCINFORMI
lola: @ trans ChoseFamilyReunion
lola: @ trans Gate1XORJoin
lola: @ trans ClearanceReqReceived
lola: @ trans ReceiveNeedReq
lola: @ trans ExplainProcedure
lola: @ trans ReceiveHousingSuitCertifReq
lola: @ trans ObtainFamRelCertif
lola: @ trans ReceiveAppointReq
lola: @ trans ReceiveNeedChoice
lola: @ trans DisplayNeedChoice
lola: @ trans AskCINFORMI
lola: INVENT VAR FOR PLACE pl0
lola: INVENT VAR FOR PLACE l18
lola: CHECK EQ TRANS HousingSuitCertifObtained
lola: findlow criterion violated for transition 63
lola: CHECK FINDLOW FOR TRANS ReceiveAccessReq
lola: INVENT VAR FOR PLACE m0
lola: INVENT VAR FOR PLACE lm0
lola: CHECK EQ TRANS ReceiveAccessReq
lola: CHECK FINDLOW FOR TRANS ReceiveNeedReq
lola: INVENT VAR FOR PLACE ml1
lola: INVENT VAR FOR PLACE l3
lola: CHECK EQ TRANS ReceiveNeedReq
lola: findlow criterion violated for transition 4
lola: CHECK FINDLOW FOR TRANS ReceiveNeedChoice
lola: INVENT VAR FOR PLACE m4
lola: INVENT VAR FOR PLACE lm2
lola: CHECK EQ TRANS ReceiveNeedChoice
lola: findlow criterion violated for transition 5
lola: CHECK FINDLOW FOR TRANS ReceiveDocsObtained
lola: INVENT VAR FOR PLACE lm3
lola: INVENT VAR FOR PLACE m6
lola: CHECK EQ TRANS ReceiveDocsObtained
lola: findlow criterion violated for transition 6
lola: CHECK FINDLOW FOR TRANS ReceiveHousingSuitCertifReq
lola: INVENT VAR FOR PLACE p0
lola: INVENT VAR FOR PLACE lp0
lola: CHECK EQ TRANS ReceiveHousingSuitCertifReq
lola: CHECK FINDLOW FOR TRANS ReceiveRegsitration
lola: INVENT VAR FOR PLACE l20
lola: INVENT VAR FOR PLACE pl1
lola: CHECK EQ TRANS ReceiveRegsitration
lola: findlow criterion violated for transition 58
lola: CHECK FINDLOW FOR TRANS CheckRequiredDoc
lola: INVENT VAR FOR PLACE c4
lola: INVENT VAR FOR PLACE lc2
lola: CHECK EQ TRANS CheckRequiredDoc
lola: CHECK FINDLOW FOR TRANS Summoned
lola: INVENT VAR FOR PLACE gl0
lola: INVENT VAR FOR PLACE l34
lola: CHECK EQ TRANS Summoned
lola: findlow criterion violated for transition 53
lola: CHECK FINDLOW FOR TRANS AppReqReceived
lola: INVENT VAR FOR PLACE c2
lola: INVENT VAR FOR PLACE lc1
lola: CHECK EQ TRANS AppReqReceived
lola: CHECK FINDLOW FOR TRANS Gate1ANDJoin
lola: INVENT VAR FOR PLACE p5
lola: INVENT VAR FOR PLACE p4
lola: CHECK EQ TRANS Gate1ANDJoin
lola: findlow criterion violated for transition 12
lola: CHECK FINDLOW FOR TRANS Gate1XORJoin
lola: INVENT VAR FOR PLACE l16
lola: INVENT VAR FOR PLACE l15
lola: CHECK EQ TRANS Gate1XORJoin
lola: findlow criterion violated for transition 13
lola: CHECK FINDLOW FOR TRANS ReceiveInstructions
lola: INVENT VAR FOR PLACE ml3
lola: INVENT VAR FOR PLACE l7
lola: CHECK EQ TRANS ReceiveInstructions
lola: findlow criterion violated for transition 50
lola: CHECK FINDLOW FOR TRANS ClearanceReqReceived
lola: INVENT VAR FOR PLACE g0
lola: INVENT VAR FOR PLACE cg0
lola: CHECK EQ TRANS ClearanceReqReceived
lola: CHECK FINDLOW FOR TRANS ReceiveLangChoice
lola: INVENT VAR FOR PLACE lm1
lola: INVENT VAR FOR PLACE m2
lola: CHECK EQ TRANS ReceiveLangChoice
lola: findlow criterion violated for transition 45
lola: CHECK FINDLOW FOR TRANS PrepFamReuClearReq
lola: INVENT VAR FOR PLACE lc3
lola: INVENT VAR FOR PLACE c5
lola: CHECK EQ TRANS PrepFamReuClearReq
lola: findlow criterion violated for transition 43
lola: CHECK FINDLOW FOR TRANS EvaluateReq
lola: INVENT VAR FOR PLACE lg0
lola: INVENT VAR FOR PLACE g2
lola: CHECK EQ TRANS EvaluateReq
lola: CHECK FINDLOW FOR TRANS RegisterRelative
lola: INVENT VAR FOR PLACE p10
lola: INVENT VAR FOR PLACE lp1
lola: CHECK EQ TRANS RegisterRelative
lola: CHECK FINDLOW FOR TRANS ReceiveAppointReq
lola: INVENT VAR FOR PLACE m8
lola: INVENT VAR FOR PLACE lm4
lola: CHECK EQ TRANS ReceiveAppointReq
lola: CHECK FINDLOW FOR TRANS ReceiveAppoint
lola: INVENT VAR FOR PLACE l10
lola: INVENT VAR FOR PLACE ml4
lola: CHECK EQ TRANS ReceiveAppoint
lola: findlow criterion violated for transition 39
lola: CHECK FINDLOW FOR TRANS ReceiveLangReq
lola: INVENT VAR FOR PLACE ml0
lola: INVENT VAR FOR PLACE l1
lola: CHECK EQ TRANS ReceiveLangReq
lola: findlow criterion violated for transition 35
lola: CHECK FINDLOW FOR TRANS RespReceived
lola: INVENT VAR FOR PLACE gl1
lola: INVENT VAR FOR PLACE l36
lola: CHECK EQ TRANS RespReceived
lola: findlow criterion violated for transition 34
lola: CHECK FINDLOW FOR TRANS CommunicateResp
lola: INVENT VAR FOR PLACE r0
lola: INVENT VAR FOR PLACE g3
lola: CHECK EQ TRANS CommunicateResp
lola: CHECK FINDLOW FOR TRANS ReceiveQuestion
lola: INVENT VAR FOR PLACE c0
lola: INVENT VAR FOR PLACE l14
lola: CHECK EQ TRANS ReceiveQuestion
lola: RELEASE
lola: RELEASE
lola: CHECK FINDLOW FOR TRANS ReceiveReqDocsReq
lola: INVENT VAR FOR PLACE l5
lola: INVENT VAR FOR PLACE ml2
lola: CHECK EQ TRANS ReceiveReqDocsReq
lola: findlow criterion violated for transition 26
lola: CHECK FINDLOW FOR TRANS AppointReceived
lola: INVENT VAR FOR PLACE l31
lola: INVENT VAR FOR PLACE cl2
lola: CHECK EQ TRANS AppointReceived
lola: findlow criterion violated for transition 29
lola: CHECK FINDLOW FOR TRANS SendClearanceToRel
lola: INVENT VAR FOR PLACE l39
lola: CHECK EQ TRANS SendClearanceToRel
lola: findlow criterion violated for transition 28
lola: CHECK FINDLOW FOR TRANS ReqAppointCINFORMI
lola: INVENT VAR FOR PLACE l9
lola: CHECK EQ TRANS ReqAppointCINFORMI
lola: CHECK FINDLOW FOR TRANS GotoOSSAndProdDoc
lola: INVENT VAR FOR PLACE l35
lola: CHECK EQ TRANS GotoOSSAndProdDoc
lola: rewrite Frontend/Parser/formula_rewrite.k:102
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: RELEASE
lola: CHECK FINDLOW FOR TRANS Gate1XORSplit
lola: INVENT VAR FOR PLACE l12
lola: CHECK EQ TRANS Gate1XORSplit
lola: CHECK FINDLOW FOR TRANS ObtainFamRelCertif
lola: INVENT VAR FOR PLACE l25
lola: CHECK EQ TRANS ObtainFamRelCertif
lola: CHECK FINDLOW FOR TRANS AskCINFORMI
lola: INVENT VAR FOR PLACE l13
lola: CHECK EQ TRANS AskCINFORMI
lola: CHECK FINDLOW FOR TRANS AccessMicTerminal
lola: INVENT VAR FOR PLACE l0
lola: CHECK EQ TRANS AccessMicTerminal
lola: CHECK FINDLOW FOR TRANS DisplayLangChoice
lola: INVENT VAR FOR PLACE m1
lola: CHECK EQ TRANS DisplayLangChoice
lola: CHECK FINDLOW FOR TRANS TransmitReq
lola: INVENT VAR FOR PLACE c6
lola: CHECK EQ TRANS TransmitReq
lola: CHECK FINDLOW FOR TRANS SummonApplicant
lola: INVENT VAR FOR PLACE g1
lola: CHECK EQ TRANS SummonApplicant
lola: CHECK FINDLOW FOR TRANS SendSuitabilityCertif
lola: INVENT VAR FOR PLACE p9
lola: CHECK EQ TRANS SendSuitabilityCertif
lola: CHECK FINDLOW FOR TRANS GoToAppoint
lola: INVENT VAR FOR PLACE l11
lola: CHECK EQ TRANS GoToAppoint
lola: CHECK FINDLOW FOR TRANS ReserveAppoint
lola: INVENT VAR FOR PLACE m9
lola: CHECK EQ TRANS ReserveAppoint
lola: CHECK FINDLOW FOR TRANS ProvidePersonalnfo
lola: INVENT VAR FOR PLACE l33
lola: CHECK EQ TRANS ProvidePersonalnfo
lola: RELEASE
lola: CHECK FINDLOW FOR TRANS ExplainHowToObtainMissingDocs
lola: INVENT VAR FOR PLACE m7
lola: CHECK EQ TRANS ExplainHowToObtainMissingDocs
lola: CHECK FINDLOW FOR TRANS SendLangChoice
lola: INVENT VAR FOR PLACE l2
lola: CHECK EQ TRANS SendLangChoice
lola: CHECK FINDLOW FOR TRANS ObtainRelativeFinStatement
lola: INVENT VAR FOR PLACE l24
lola: CHECK EQ TRANS ObtainRelativeFinStatement
lola: CHECK FINDLOW FOR TRANS ReserveAppCINFORMI
lola: INVENT VAR FOR PLACE l30
lola: CHECK EQ TRANS ReserveAppCINFORMI
lola: CHECK FINDLOW FOR TRANS TickDocsObtained
lola: INVENT VAR FOR PLACE l6
lola: CHECK EQ TRANS TickDocsObtained
lola: CHECK FINDLOW FOR TRANS ArchiveReq
lola: INVENT VAR FOR PLACE p7
lola: CHECK EQ TRANS ArchiveReq
lola: CHECK FINDLOW FOR TRANS CheckSanityReq
lola: INVENT VAR FOR PLACE p3
lola: CHECK EQ TRANS CheckSanityReq
lola: CHECK FINDLOW FOR TRANS Gate1ANDSplit
lola: INVENT VAR FOR PLACE p1
lola: CHECK EQ TRANS Gate1ANDSplit
lola: CHECK FINDLOW FOR TRANS SetUpAppoint
lola: INVENT VAR FOR PLACE c3
lola: CHECK EQ TRANS SetUpAppoint
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: CHECK FINDLOW FOR TRANS ReqHousingSuitCertif
lola: INVENT VAR FOR PLACE l17
lola: CHECK EQ TRANS ReqHousingSuitCertif
lola: CHECK FINDLOW FOR TRANS DisplayNeedChoice
lola: INVENT VAR FOR PLACE m3
lola: CHECK EQ TRANS DisplayNeedChoice
lola: CHECK FINDLOW FOR TRANS Gate2XORSplit
lola: Rule S: 0 transitions removed,21 places removed
lola: INVENT VAR FOR PLACE p6
lola: CHECK EQ TRANS Gate2XORSplit
lola: CHECK FINDLOW FOR TRANS ObtainRelHealtCondStatement
lola: INVENT VAR FOR PLACE l23
lola: CHECK EQ TRANS ObtainRelHealtCondStatement
lola: CHECK FINDLOW FOR TRANS ChoseFamilyReunion
lola: INVENT VAR FOR PLACE l4
lola: CHECK EQ TRANS ChoseFamilyReunion
lola: CHECK FINDLOW FOR TRANS ObtainMissingDocs
lola: INVENT VAR FOR PLACE l8
lola: CHECK EQ TRANS ObtainMissingDocs
lola: CHECK FINDLOW FOR TRANS ExplainProcedure
lola: INVENT VAR FOR PLACE cl0
lola: CHECK EQ TRANS ExplainProcedure
lola: CHECK FINDLOW FOR TRANS CheckHousingSuitReq
lola: INVENT VAR FOR PLACE p2
lola: CHECK EQ TRANS CheckHousingSuitReq
lola: CHECK FINDLOW FOR TRANS RegisterRelativePubHealth
lola: INVENT VAR FOR PLACE l19
lola: CHECK EQ TRANS RegisterRelativePubHealth
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 79 (type EXCL) for 6 FamilyReunion-COL-L00020M0002C001P001G001-02
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 77 (type FNDP) for 6 FamilyReunion-COL-L00020M0002C001P001G001-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type EQUN) for 6 FamilyReunion-COL-L00020M0002C001P001G001-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type SRCH) for 6 FamilyReunion-COL-L00020M0002C001P001G001-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-01: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ 0 0 4 0 3 0 0 1
FamilyReunion-COL-L00020M0002C001P001G001-03: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-04: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-05: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-06: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-08: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-10: CONJ 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-11: AG 0 0 0 0 4 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-12: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-13: F 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-14: LTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-15: CONJ 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
77 EF FNDP 0/3595 0/5 FamilyReunion-COL-L00020M0002C001P001G001-02 --
78 EF STEQ 0/3595 0/5 FamilyReunion-COL-L00020M0002C001P001G001-02 sara not yet started (preprocessing).
79 EF EXCL 0/112 1/32 FamilyReunion-COL-L00020M0002C001P001G001-02 --
80 EF SRCH 0/3595 1/5 FamilyReunion-COL-L00020M0002C001P001G001-02 --
Time elapsed: 5 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 80 (type SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 79 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-02
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 77 (type FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-02 (obsolete)
lola: CANCELED task # 78 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-02 (obsolete)
lola: FINISHED task # 77 (type FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/LTLCardinality-78.sara.
lola: CHECK FINDLOW FOR TRANS PrepIncomeCertif
sara: place or transition ordering is non-deterministic
lola: INVENT VAR FOR PLACE l22
lola: CHECK EQ TRANS PrepIncomeCertif
lola: planning for (null) stopped (result already fixed).
lola: FINISHED task # 78 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-02
lola: result : true
lola: CHECK FINDLOW FOR TRANS Gate3XORSplit
lola: INVENT VAR FOR PLACE l37
lola: CHECK EQ TRANS Gate3XORSplit
lola: LAUNCH task # 36 (type EXCL) for 35 FamilyReunion-COL-L00020M0002C001P001G001-09
lola: time limit : 123 sec
lola: memory limit: 32 pages
lola: CHECK FINDLOW FOR TRANS Gate2ANDSplit
lola: INVENT VAR FOR PLACE l21
lola: CHECK EQ TRANS Gate2ANDSplit
lola: FINISHED task # 36 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-09
lola: result : false
lola: markings : 664
lola: fired transitions : 664
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 38 FamilyReunion-COL-L00020M0002C001P001G001-10
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: CHECK FINDLOW FOR TRANS GiveAppoint
lola: INVENT VAR FOR PLACE m10
lola: CHECK EQ TRANS GiveAppoint
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CHECK FINDLOW FOR TRANS DisplayReqDocs
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: INVENT VAR FOR PLACE m5
lola: CHECK EQ TRANS DisplayReqDocs
lola: LAUNCH task # 82 (type FNDP) for 45 FamilyReunion-COL-L00020M0002C001P001G001-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type EQUN) for 45 FamilyReunion-COL-L00020M0002C001P001G001-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 85 (type SRCH) for 45 FamilyReunion-COL-L00020M0002C001P001G001-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-11
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: CHECK FINDLOW FOR TRANS BringReqtoCINFORMI
sara: try reading problem file /home/mcc/execution/LTLCardinality-83.sara.
lola: INVENT VAR FOR PLACE l32
lola: CHECK EQ TRANS BringReqtoCINFORMI
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: findlow criterion violated for 19 clusters
lola: Time for checking findlow: 6.000000
lola: TRANS 59: Gate2ANDJoin is minimal, eq to 59
lola: TRANS 64: GotIt is minimal, eq to 64
lola: TRANS 63: HousingSuitCertifObtained is minimal, eq to 63
lola: TRANS 60: ReceiveAccessReq is minimal, eq to 60
lola: TRANS 4: ReceiveNeedReq is minimal, eq to 4
lola: TRANS 5: ReceiveNeedChoice is minimal, eq to 5
lola: TRANS 6: ReceiveDocsObtained is minimal, eq to 6
lola: TRANS 0: ReceiveHousingSuitCertifReq is minimal, eq to 0
lola: TRANS 58: ReceiveRegsitration is minimal, eq to 58
lola: TRANS 54: CheckRequiredDoc is minimal, eq to 54
lola: TRANS 53: Summoned is minimal, eq to 53
lola: TRANS 11: AppReqReceived is minimal, eq to 11
lola: TRANS 12: Gate1ANDJoin is minimal, eq to 12
lola: TRANS 13: Gate1XORJoin is minimal, eq to 13
lola: TRANS 50: ReceiveInstructions is minimal, eq to 50
lola: TRANS 49: ClearanceReqReceived is minimal, eq to 49
lola: TRANS 45: ReceiveLangChoice is minimal, eq to 45
lola: TRANS 43: PrepFamReuClearReq is minimal, eq to 43
lola: TRANS 18: EvaluateReq is minimal, eq to 18
lola: TRANS 42: RegisterRelative is minimal, eq to 42
lola: TRANS 41: ReceiveAppointReq is minimal, eq to 41
lola: TRANS 39: ReceiveAppoint is minimal, eq to 39
lola: TRANS 35: ReceiveLangReq is minimal, eq to 35
lola: TRANS 34: RespReceived is minimal, eq to 34
lola: TRANS 24: CommunicateResp is minimal, eq to 24
lola: TRANS 32: ReceiveQuestion is minimal, eq to 32
lola: TRANS 26: ReceiveReqDocsReq is minimal, eq to 26
lola: TRANS 29: AppointReceived is minimal, eq to 29
lola: TRANS 28: SendClearanceToRel is minimal, eq to 28
lola: TRANS 27: ReqAppointCINFORMI is minimal, eq to 27
lola: TRANS 30: GotoOSSAndProdDoc is minimal, eq to 30
lola: TRANS 31: Gate1XORSplit is minimal, eq to 31
lola: TRANS 25: ObtainFamRelCertif is minimal, eq to 25
lola: TRANS 33: AskCINFORMI is minimal, eq to 33
lola: TRANS 23: AccessMicTerminal is minimal, eq to 23
lola: TRANS 22: DisplayLangChoice is minimal, eq to 22
lola: TRANS 36: TransmitReq is minimal, eq to 36
lola: TRANS 37: SummonApplicant is minimal, eq to 37
lola: TRANS 38: SendSuitabilityCertif is minimal, eq to 38
lola: TRANS 21: GoToAppoint is minimal, eq to 21
lola: TRANS 40: ReserveAppoint is minimal, eq to 40
lola: TRANS 20: ProvidePersonalnfo is minimal, eq to 20
lola: TRANS 19: ExplainHowToObtainMissingDocs is minimal, eq to 19
lola: TRANS 17: SendLangChoice is minimal, eq to 17
lola: TRANS 44: ObtainRelativeFinStatement is minimal, eq to 44
lola: TRANS 16: ReserveAppCINFORMI is minimal, eq to 16
lola: TRANS 46: TickDocsObtained is minimal, eq to 46
lola: TRANS 47: ArchiveReq is minimal, eq to 47
lola: TRANS 48: CheckSanityReq is minimal, eq to 48
lola: TRANS 15: Gate1ANDSplit is minimal, eq to 15
lola: TRANS 14: SetUpAppoint is minimal, eq to 14
lola: TRANS 51: ReqHousingSuitCertif is minimal, eq to 51
lola: TRANS 52: DisplayNeedChoice is minimal, eq to 52
lola: TRANS 10: Gate2XORSplit is minimal, eq to 10
lola: TRANS 9: ObtainRelHealtCondStatement is minimal, eq to 9
lola: TRANS 55: ChoseFamilyReunion is minimal, eq to 55
lola: TRANS 56: ObtainMissingDocs is minimal, eq to 56
lola: TRANS 57: ExplainProcedure is minimal, eq to 57
lola: TRANS 8: CheckHousingSuitReq is minimal, eq to 8
lola: TRANS 7: RegisterRelativePubHealth is minimal, eq to 7
lola: TRANS 3: PrepIncomeCertif is minimal, eq to 3
lola: TRANS 61: Gate3XORSplit is minimal, eq to 61
lola: TRANS 62: Gate2ANDSplit is minimal, eq to 62
lola: TRANS 2: GiveAppoint is minimal, eq to 2
lola: TRANS 1: DisplayReqDocs is minimal, eq to 1
lola: TRANS 65: BringReqtoCINFORMI is minimal, eq to 65
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: FINISHED task # 82 (type FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-11
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 83 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-11 (obsolete)
lola: FINISHED task # 83 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-11
lola: result : unknown
lola: LAUNCH task # 87 (type SKEL/SRCH) for 16 FamilyReunion-COL-L00020M0002C001P001G001-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type SKEL/SRCH) for 28 FamilyReunion-COL-L00020M0002C001P001G001-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 87 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-04
lola: result : false
lola: markings : 1216
lola: fired transitions : 1216
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 88 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-08
lola: result : false
lola: markings : 1216
lola: fired transitions : 1216
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ false state space
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-11: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-08: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-10: CONJ 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-12: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-13: F 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-14: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-15: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 LTL EXCL 4/276 1/32 FamilyReunion-COL-L00020M0002C001P001G001-10 52015 m, 10403 m/sec, 380019 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ false state space
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-11: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-08: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-10: CONJ 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-12: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-13: F 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-14: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-15: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 LTL EXCL 9/276 2/32 FamilyReunion-COL-L00020M0002C001P001G001-10 109831 m, 11563 m/sec, 896862 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ false state space
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL false LTL model checker
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23 LTL EXCL 105/531 28/32 FamilyReunion-COL-L00020M0002C001P001G001-06 2607440 m, 21740 m/sec, 5548924 t fired, .
Time elapsed: 515 secs. Pages in use: 61
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ false state space
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-08: CONJ false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-11: AG false findpath
FamilyReunion-COL-L00020M0002C001P001G001-12: LTL true LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-15: CONJ false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-10: CONJ 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-13: F 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 110/531 29/32 FamilyReunion-COL-L00020M0002C001P001G001-06 2708795 m, 20271 m/sec, 5812197 t fired, .
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FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ false state space
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-08: CONJ false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-11: AG false findpath
FamilyReunion-COL-L00020M0002C001P001G001-12: LTL true LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-15: CONJ false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-10: CONJ 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-13: F 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 115/531 30/32 FamilyReunion-COL-L00020M0002C001P001G001-06 2816614 m, 21563 m/sec, 6074784 t fired, .
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FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ false state space
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-08: CONJ false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-11: AG false findpath
FamilyReunion-COL-L00020M0002C001P001G001-12: LTL true LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-15: CONJ false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-10: CONJ 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-13: F 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 120/531 31/32 FamilyReunion-COL-L00020M0002C001P001G001-06 2942003 m, 25077 m/sec, 6338377 t fired, .
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# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ false state space
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-08: CONJ false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-11: AG false findpath
FamilyReunion-COL-L00020M0002C001P001G001-12: LTL true LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-15: CONJ false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-10: CONJ 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-13: F 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 535 secs. Pages in use: 61
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 FamilyReunion-COL-L00020M0002C001P001G001-05
lola: time limit : 613 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-05
lola: result : false
lola: markings : 1214
lola: fired transitions : 1214
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 FamilyReunion-COL-L00020M0002C001P001G001-04
lola: time limit : 766 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-04
lola: result : false
lola: markings : 1214
lola: fired transitions : 1214
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 FamilyReunion-COL-L00020M0002C001P001G001-03
lola: time limit : 1021 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-03
lola: result : true
lola: markings : 22
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 FamilyReunion-COL-L00020M0002C001P001G001-01
lola: time limit : 1532 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-01
lola: result : false
lola: markings : 1218
lola: fired transitions : 1219
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 86 (type EXCL) for 51 FamilyReunion-COL-L00020M0002C001P001G001-13
lola: time limit : 3065 sec
lola: memory limit: 32 pages
lola: FINISHED task # 86 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-13
lola: result : true
lola: markings : 622
lola: fired transitions : 621
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00020M0002C001P001G001-00: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-01: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-02: CONJ false state space
FamilyReunion-COL-L00020M0002C001P001G001-03: LTL true LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-05: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-06: LTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-07: INITIAL false skeleton: preprocessing
FamilyReunion-COL-L00020M0002C001P001G001-08: CONJ false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-09: LTL false LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-10: CONJ unknown CONJ
FamilyReunion-COL-L00020M0002C001P001G001-11: AG false findpath
FamilyReunion-COL-L00020M0002C001P001G001-12: LTL true LTL model checker
FamilyReunion-COL-L00020M0002C001P001G001-13: F false state space / EG
FamilyReunion-COL-L00020M0002C001P001G001-14: LTL unknown AGGR
FamilyReunion-COL-L00020M0002C001P001G001-15: CONJ false LTL model checker
Time elapsed: 535 secs. Pages in use: 61
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00020M0002C001P001G001"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00020M0002C001P001G001, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r080-tall-162048871500852"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00020M0002C001P001G001.tgz
mv FamilyReunion-COL-L00020M0002C001P001G001 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;