Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r080-tall-162048871500849.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is FamilyReunion-COL-L00020M0002C001P001G001, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r080-tall-162048871500849
=====================================================================

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preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 112K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 16K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 79K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 16:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 28 16:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Mar 28 16:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 16:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 23 10:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 23 10:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.0K Mar 22 18:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 22 18:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Mar 22 09:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Mar 22 09:11 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 24 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 135K May 5 16:51 model.pnml

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content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1620777102544

starting LoLA
BK_INPUT FamilyReunion-COL-L00020M0002C001P001G001
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution

FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: NOTDEADLOCKFREE
lola: start findlow
lola: CHECK FINDLOW FOR TRANS Gate2ANDJoin
lola: INVENT VAR FOR PLACE l29
lola: INVENT VAR FOR PLACE l27
lola: INVENT VAR FOR PLACE l26
lola: INVENT VAR FOR PLACE l28
lola: CHECK EQ TRANS Gate2ANDJoin
lola: TR BINDINGS
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: TR BINDINGS DONE
lola: Places: 3292, Transitions: 2753
lola: findlow criterion violated for transition 59
lola: @ trans RegisterRelativePubHealth
lola: @ trans Gate1XORSplit
lola: @ trans ObtainMissingDocs
lola: @ trans DisplayReqDocs
lola: @ trans Gate2ANDJoin
lola: @ trans SummonApplicant
lola: @ trans GotIt
lola: @ trans Gate3XORSplit
lola: @ trans HousingSuitCertifObtained
lola: @ trans CheckRequiredDoc
lola: @ trans ReceiveRegsitration
lola: @ trans ProvidePersonalnfo
lola: @ trans AppReqReceived
lola: @ trans ReserveAppoint
lola: @ trans SendClearanceToRel
lola: @ trans SendLangChoice
lola: @ trans ObtainRelativeFinStatement
lola: @ trans TransmitReq
lola: @ trans TickDocsObtained
lola: @ trans ReceiveAccessReq
lola: @ trans ReceiveLangChoice
lola: @ trans ReqHousingSuitCertif
lola: @ trans BringReqtoCINFORMI
lola: @ trans ExplainHowToObtainMissingDocs
lola: @ trans SendSuitabilityCertif
lola: @ trans EvaluateReq
lola: @ trans CheckHousingSuitReq
lola: CHECK FINDLOW FOR TRANS GotIt
lola: @ trans ReceiveAppoint
lola: @ trans DisplayLangChoice
lola: @ trans Gate1ANDJoin
lola: @ trans Gate2XORSplit
lola: INVENT VAR FOR PLACE lc0
lola: INVENT VAR FOR PLACE cl1
lola: CHECK EQ TRANS GotIt
lola: @ trans RegisterRelative
lola: @ trans Summoned
lola: @ trans PrepIncomeCertif
lola: @ trans Gate1ANDSplit
lola: @ trans ReceiveQuestion
lola: @ trans RespReceived
lola: @ trans PrepFamReuClearReq
lola: @ trans ReqAppointCINFORMI
lola: @ trans GoToAppoint
lola: @ trans GotoOSSAndProdDoc
lola: @ trans ArchiveReq
lola: @ trans Gate2ANDSplit
lola: @ trans ReceiveDocsObtained
lola: @ trans AppointReceived
lola: @ trans CheckSanityReq
lola: @ trans ReceiveInstructions
lola: @ trans AccessMicTerminal
lola: @ trans SetUpAppoint
lola: @ trans ReceiveReqDocsReq
lola: @ trans ReceiveLangReq
lola: @ trans CommunicateResp
lola: @ trans ObtainRelHealtCondStatement
lola: @ trans GiveAppoint
lola: @ trans ReserveAppCINFORMI
lola: @ trans ChoseFamilyReunion
lola: @ trans Gate1XORJoin
lola: @ trans ClearanceReqReceived
lola: @ trans ReceiveNeedReq
lola: @ trans ExplainProcedure
lola: @ trans ReceiveHousingSuitCertifReq
lola: @ trans ObtainFamRelCertif
lola: @ trans ReceiveAppointReq
lola: @ trans ReceiveNeedChoice
lola: @ trans DisplayNeedChoice
lola: @ trans AskCINFORMI
lola: findlow criterion violated for transition 64
lola: CHECK FINDLOW FOR TRANS HousingSuitCertifObtained
lola: INVENT VAR FOR PLACE pl0
lola: INVENT VAR FOR PLACE l18
lola: CHECK EQ TRANS HousingSuitCertifObtained
lola: findlow criterion violated for transition 63
lola: CHECK FINDLOW FOR TRANS ReceiveAccessReq
lola: INVENT VAR FOR PLACE m0
lola: INVENT VAR FOR PLACE lm0
lola: CHECK EQ TRANS ReceiveAccessReq
lola: CHECK FINDLOW FOR TRANS ReceiveNeedReq
lola: INVENT VAR FOR PLACE ml1
lola: INVENT VAR FOR PLACE l3
lola: CHECK EQ TRANS ReceiveNeedReq
lola: findlow criterion violated for transition 4
lola: CHECK FINDLOW FOR TRANS ReceiveNeedChoice
lola: INVENT VAR FOR PLACE m4
lola: INVENT VAR FOR PLACE lm2
lola: CHECK EQ TRANS ReceiveNeedChoice
lola: findlow criterion violated for transition 5
lola: CHECK FINDLOW FOR TRANS ReceiveDocsObtained
lola: INVENT VAR FOR PLACE lm3
lola: INVENT VAR FOR PLACE m6
lola: CHECK EQ TRANS ReceiveDocsObtained
lola: findlow criterion violated for transition 6
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 8 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: CHECK FINDLOW FOR TRANS ReceiveHousingSuitCertifReq
lola: INVENT VAR FOR PLACE p0
lola: INVENT VAR FOR PLACE lp0
lola: CHECK EQ TRANS ReceiveHousingSuitCertifReq
lola: CHECK FINDLOW FOR TRANS ReceiveRegsitration
lola: INVENT VAR FOR PLACE l20
lola: INVENT VAR FOR PLACE pl1
lola: CHECK EQ TRANS ReceiveRegsitration
lola: findlow criterion violated for transition 58
lola: CHECK FINDLOW FOR TRANS CheckRequiredDoc
lola: INVENT VAR FOR PLACE c4
lola: INVENT VAR FOR PLACE lc2
lola: CHECK EQ TRANS CheckRequiredDoc
lola: CHECK FINDLOW FOR TRANS Summoned
lola: INVENT VAR FOR PLACE gl0
lola: INVENT VAR FOR PLACE l34
lola: CHECK EQ TRANS Summoned
lola: findlow criterion violated for transition 53
lola: CHECK FINDLOW FOR TRANS AppReqReceived
lola: INVENT VAR FOR PLACE c2
lola: INVENT VAR FOR PLACE lc1
lola: CHECK EQ TRANS AppReqReceived
lola: CHECK FINDLOW FOR TRANS Gate1ANDJoin
lola: INVENT VAR FOR PLACE p5
lola: INVENT VAR FOR PLACE p4
lola: CHECK EQ TRANS Gate1ANDJoin
lola: findlow criterion violated for transition 12
lola: CHECK FINDLOW FOR TRANS Gate1XORJoin
lola: INVENT VAR FOR PLACE l16
lola: INVENT VAR FOR PLACE l15
lola: CHECK EQ TRANS Gate1XORJoin
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 13 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: findlow criterion violated for transition 13
lola: CHECK FINDLOW FOR TRANS ReceiveInstructions
lola: INVENT VAR FOR PLACE ml3
lola: INVENT VAR FOR PLACE l7
lola: CHECK EQ TRANS ReceiveInstructions
lola: findlow criterion violated for transition 50
lola: CHECK FINDLOW FOR TRANS ClearanceReqReceived
lola: INVENT VAR FOR PLACE g0
lola: INVENT VAR FOR PLACE cg0
lola: CHECK EQ TRANS ClearanceReqReceived
lola: CHECK FINDLOW FOR TRANS ReceiveLangChoice
lola: INVENT VAR FOR PLACE lm1
lola: INVENT VAR FOR PLACE m2
lola: CHECK EQ TRANS ReceiveLangChoice
lola: findlow criterion violated for transition 45
lola: CHECK FINDLOW FOR TRANS PrepFamReuClearReq
lola: INVENT VAR FOR PLACE lc3
lola: INVENT VAR FOR PLACE c5
lola: CHECK EQ TRANS PrepFamReuClearReq
lola: findlow criterion violated for transition 43
lola: CHECK FINDLOW FOR TRANS EvaluateReq
lola: INVENT VAR FOR PLACE lg0
lola: INVENT VAR FOR PLACE g2
lola: CHECK EQ TRANS EvaluateReq
lola: CHECK FINDLOW FOR TRANS RegisterRelative
lola: INVENT VAR FOR PLACE p10
lola: INVENT VAR FOR PLACE lp1
lola: CHECK EQ TRANS RegisterRelative
lola: CHECK FINDLOW FOR TRANS ReceiveAppointReq
lola: INVENT VAR FOR PLACE m8
lola: INVENT VAR FOR PLACE lm4
lola: CHECK EQ TRANS ReceiveAppointReq
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

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lola: CHECK FINDLOW FOR TRANS ReceiveAppoint
lola: INVENT VAR FOR PLACE l10
lola: INVENT VAR FOR PLACE ml4
lola: CHECK EQ TRANS ReceiveAppoint
lola: findlow criterion violated for transition 39
lola: CHECK FINDLOW FOR TRANS ReceiveLangReq
lola: INVENT VAR FOR PLACE ml0
lola: INVENT VAR FOR PLACE l1
lola: CHECK EQ TRANS ReceiveLangReq
lola: findlow criterion violated for transition 35
lola: CHECK FINDLOW FOR TRANS RespReceived
lola: INVENT VAR FOR PLACE gl1
lola: INVENT VAR FOR PLACE l36
lola: CHECK EQ TRANS RespReceived
lola: findlow criterion violated for transition 34
lola: CHECK FINDLOW FOR TRANS CommunicateResp
lola: INVENT VAR FOR PLACE r0
lola: INVENT VAR FOR PLACE g3
lola: CHECK EQ TRANS CommunicateResp
lola: CHECK FINDLOW FOR TRANS ReceiveQuestion
lola: INVENT VAR FOR PLACE c0
lola: INVENT VAR FOR PLACE l14
lola: CHECK EQ TRANS ReceiveQuestion
lola: CHECK FINDLOW FOR TRANS ReceiveReqDocsReq
lola: INVENT VAR FOR PLACE l5
lola: INVENT VAR FOR PLACE ml2
lola: CHECK EQ TRANS ReceiveReqDocsReq
lola: findlow criterion violated for transition 26
lola: CHECK FINDLOW FOR TRANS AppointReceived
lola: INVENT VAR FOR PLACE l31
lola: INVENT VAR FOR PLACE cl2
lola: CHECK EQ TRANS AppointReceived
lola: findlow criterion violated for transition 29
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

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lola: CHECK FINDLOW FOR TRANS SendClearanceToRel
lola: INVENT VAR FOR PLACE l39
lola: CHECK EQ TRANS SendClearanceToRel
lola: findlow criterion violated for transition 28
lola: CHECK FINDLOW FOR TRANS ReqAppointCINFORMI
lola: INVENT VAR FOR PLACE l9
lola: CHECK EQ TRANS ReqAppointCINFORMI
lola: CHECK FINDLOW FOR TRANS GotoOSSAndProdDoc
lola: INVENT VAR FOR PLACE l35
lola: CHECK EQ TRANS GotoOSSAndProdDoc
lola: CHECK FINDLOW FOR TRANS Gate1XORSplit
lola: INVENT VAR FOR PLACE l12
lola: CHECK EQ TRANS Gate1XORSplit
lola: CHECK FINDLOW FOR TRANS ObtainFamRelCertif
lola: INVENT VAR FOR PLACE l25
lola: CHECK EQ TRANS ObtainFamRelCertif
lola: CHECK FINDLOW FOR TRANS AskCINFORMI
lola: INVENT VAR FOR PLACE l13
lola: CHECK EQ TRANS AskCINFORMI
lola: CHECK FINDLOW FOR TRANS AccessMicTerminal
lola: INVENT VAR FOR PLACE l0
lola: CHECK EQ TRANS AccessMicTerminal
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

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lola: CHECK FINDLOW FOR TRANS DisplayLangChoice
lola: INVENT VAR FOR PLACE m1
lola: CHECK EQ TRANS DisplayLangChoice
lola: CHECK FINDLOW FOR TRANS TransmitReq
lola: INVENT VAR FOR PLACE c6
lola: CHECK EQ TRANS TransmitReq
lola: CHECK FINDLOW FOR TRANS SummonApplicant
lola: INVENT VAR FOR PLACE g1
lola: CHECK EQ TRANS SummonApplicant
lola: CHECK FINDLOW FOR TRANS SendSuitabilityCertif
lola: INVENT VAR FOR PLACE p9
lola: CHECK EQ TRANS SendSuitabilityCertif
lola: CHECK FINDLOW FOR TRANS GoToAppoint
lola: INVENT VAR FOR PLACE l11
lola: CHECK EQ TRANS GoToAppoint
lola: CHECK FINDLOW FOR TRANS ReserveAppoint
lola: INVENT VAR FOR PLACE m9
lola: CHECK EQ TRANS ReserveAppoint
lola: CHECK FINDLOW FOR TRANS ProvidePersonalnfo
lola: INVENT VAR FOR PLACE l33
lola: CHECK EQ TRANS ProvidePersonalnfo
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

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lola: CHECK FINDLOW FOR TRANS ExplainHowToObtainMissingDocs
lola: INVENT VAR FOR PLACE m7
lola: CHECK EQ TRANS ExplainHowToObtainMissingDocs
lola: CHECK FINDLOW FOR TRANS SendLangChoice
lola: INVENT VAR FOR PLACE l2
lola: CHECK EQ TRANS SendLangChoice
lola: CHECK FINDLOW FOR TRANS ObtainRelativeFinStatement
lola: INVENT VAR FOR PLACE l24
lola: CHECK EQ TRANS ObtainRelativeFinStatement
lola: CHECK FINDLOW FOR TRANS ReserveAppCINFORMI
lola: INVENT VAR FOR PLACE l30
lola: CHECK EQ TRANS ReserveAppCINFORMI
lola: CHECK FINDLOW FOR TRANS TickDocsObtained
lola: INVENT VAR FOR PLACE l6
lola: CHECK EQ TRANS TickDocsObtained
lola: CHECK FINDLOW FOR TRANS ArchiveReq
lola: INVENT VAR FOR PLACE p7
lola: CHECK EQ TRANS ArchiveReq
lola: CHECK FINDLOW FOR TRANS CheckSanityReq
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

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lola: INVENT VAR FOR PLACE p3
lola: CHECK EQ TRANS CheckSanityReq
lola: CHECK FINDLOW FOR TRANS Gate1ANDSplit
lola: INVENT VAR FOR PLACE p1
lola: CHECK EQ TRANS Gate1ANDSplit
lola: CHECK FINDLOW FOR TRANS SetUpAppoint
lola: INVENT VAR FOR PLACE c3
lola: CHECK EQ TRANS SetUpAppoint
lola: CHECK FINDLOW FOR TRANS ReqHousingSuitCertif
lola: INVENT VAR FOR PLACE l17
lola: CHECK EQ TRANS ReqHousingSuitCertif
lola: CHECK FINDLOW FOR TRANS DisplayNeedChoice
lola: INVENT VAR FOR PLACE m3
lola: CHECK EQ TRANS DisplayNeedChoice
lola: CHECK FINDLOW FOR TRANS Gate2XORSplit
lola: INVENT VAR FOR PLACE p6
lola: CHECK EQ TRANS Gate2XORSplit
lola: CHECK FINDLOW FOR TRANS ObtainRelHealtCondStatement
lola: INVENT VAR FOR PLACE l23
lola: CHECK EQ TRANS ObtainRelHealtCondStatement
lola: CHECK FINDLOW FOR TRANS ChoseFamilyReunion
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

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lola: INVENT VAR FOR PLACE l4
lola: CHECK EQ TRANS ChoseFamilyReunion
lola: CHECK FINDLOW FOR TRANS ObtainMissingDocs
lola: INVENT VAR FOR PLACE l8
lola: CHECK EQ TRANS ObtainMissingDocs
lola: CHECK FINDLOW FOR TRANS ExplainProcedure
lola: INVENT VAR FOR PLACE cl0
lola: CHECK EQ TRANS ExplainProcedure
lola: CHECK FINDLOW FOR TRANS CheckHousingSuitReq
lola: INVENT VAR FOR PLACE p2
lola: CHECK EQ TRANS CheckHousingSuitReq
lola: CHECK FINDLOW FOR TRANS RegisterRelativePubHealth
lola: INVENT VAR FOR PLACE l19
lola: CHECK EQ TRANS RegisterRelativePubHealth
lola: CHECK FINDLOW FOR TRANS PrepIncomeCertif
lola: INVENT VAR FOR PLACE l22
lola: CHECK EQ TRANS PrepIncomeCertif
lola: CHECK FINDLOW FOR TRANS Gate3XORSplit
lola: INVENT VAR FOR PLACE l37
lola: CHECK EQ TRANS Gate3XORSplit
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-00: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: CHECK FINDLOW FOR TRANS Gate2ANDSplit
lola: INVENT VAR FOR PLACE l21
lola: CHECK EQ TRANS Gate2ANDSplit
lola: CHECK FINDLOW FOR TRANS GiveAppoint
lola: INVENT VAR FOR PLACE m10
lola: CHECK EQ TRANS GiveAppoint
lola: CHECK FINDLOW FOR TRANS DisplayReqDocs
lola: INVENT VAR FOR PLACE m5
lola: CHECK EQ TRANS DisplayReqDocs
lola: CHECK FINDLOW FOR TRANS BringReqtoCINFORMI
lola: INVENT VAR FOR PLACE l32
lola: CHECK EQ TRANS BringReqtoCINFORMI
lola: findlow criterion violated for 19 clusters
lola: Time for checking findlow: 48.000000
lola: TRANS 59: Gate2ANDJoin is minimal, eq to 59
lola: TRANS 64: GotIt is minimal, eq to 64
lola: TRANS 63: HousingSuitCertifObtained is minimal, eq to 63
lola: TRANS 60: ReceiveAccessReq is minimal, eq to 60
lola: TRANS 4: ReceiveNeedReq is minimal, eq to 4
lola: TRANS 5: ReceiveNeedChoice is minimal, eq to 5
lola: TRANS 6: ReceiveDocsObtained is minimal, eq to 6
lola: TRANS 0: ReceiveHousingSuitCertifReq is minimal, eq to 0
lola: TRANS 58: ReceiveRegsitration is minimal, eq to 58
lola: TRANS 54: CheckRequiredDoc is minimal, eq to 54
lola: TRANS 53: Summoned is minimal, eq to 53
lola: TRANS 11: AppReqReceived is minimal, eq to 11
lola: TRANS 12: Gate1ANDJoin is minimal, eq to 12
lola: TRANS 13: Gate1XORJoin is minimal, eq to 13
lola: TRANS 50: ReceiveInstructions is minimal, eq to 50
lola: TRANS 49: ClearanceReqReceived is minimal, eq to 49
lola: TRANS 45: ReceiveLangChoice is minimal, eq to 45
lola: TRANS 43: PrepFamReuClearReq is minimal, eq to 43
lola: TRANS 18: EvaluateReq is minimal, eq to 18
lola: TRANS 42: RegisterRelative is minimal, eq to 42
lola: TRANS 41: ReceiveAppointReq is minimal, eq to 41
lola: TRANS 39: ReceiveAppoint is minimal, eq to 39
lola: TRANS 35: ReceiveLangReq is minimal, eq to 35
lola: TRANS 34: RespReceived is minimal, eq to 34
lola: TRANS 24: CommunicateResp is minimal, eq to 24
lola: TRANS 32: ReceiveQuestion is minimal, eq to 32
lola: TRANS 26: ReceiveReqDocsReq is minimal, eq to 26
lola: TRANS 29: AppointReceived is minimal, eq to 29
lola: TRANS 28: SendClearanceToRel is minimal, eq to 28
lola: TRANS 27: ReqAppointCINFORMI is minimal, eq to 27
lola: TRANS 30: GotoOSSAndProdDoc is minimal, eq to 30
lola: TRANS 31: Gate1XORSplit is minimal, eq to 31
lola: TRANS 25: ObtainFamRelCertif is minimal, eq to 25
lola: TRANS 33: AskCINFORMI is minimal, eq to 33
lola: TRANS 23: AccessMicTerminal is minimal, eq to 23
lola: TRANS 22: DisplayLangChoice is minimal, eq to 22
lola: TRANS 36: TransmitReq is minimal, eq to 36
lola: TRANS 37: SummonApplicant is minimal, eq to 37
lola: TRANS 38: SendSuitabilityCertif is minimal, eq to 38
lola: TRANS 21: GoToAppoint is minimal, eq to 21
lola: TRANS 40: ReserveAppoint is minimal, eq to 40
lola: TRANS 20: ProvidePersonalnfo is minimal, eq to 20
lola: TRANS 19: ExplainHowToObtainMissingDocs is minimal, eq to 19
lola: TRANS 17: SendLangChoice is minimal, eq to 17
lola: TRANS 44: ObtainRelativeFinStatement is minimal, eq to 44
lola: TRANS 16: ReserveAppCINFORMI is minimal, eq to 16
lola: TRANS 46: TickDocsObtained is minimal, eq to 46
lola: TRANS 47: ArchiveReq is minimal, eq to 47
lola: TRANS 48: CheckSanityReq is minimal, eq to 48
lola: TRANS 15: Gate1ANDSplit is minimal, eq to 15
lola: TRANS 14: SetUpAppoint is minimal, eq to 14
lola: TRANS 51: ReqHousingSuitCertif is minimal, eq to 51
lola: TRANS 52: DisplayNeedChoice is minimal, eq to 52
lola: TRANS 10: Gate2XORSplit is minimal, eq to 10
lola: TRANS 9: ObtainRelHealtCondStatement is minimal, eq to 9
lola: TRANS 55: ChoseFamilyReunion is minimal, eq to 55
lola: TRANS 56: ObtainMissingDocs is minimal, eq to 56
lola: TRANS 57: ExplainProcedure is minimal, eq to 57
lola: TRANS 8: CheckHousingSuitReq is minimal, eq to 8
lola: TRANS 7: RegisterRelativePubHealth is minimal, eq to 7
lola: TRANS 3: PrepIncomeCertif is minimal, eq to 3
lola: TRANS 61: Gate3XORSplit is minimal, eq to 61
lola: TRANS 62: Gate2ANDSplit is minimal, eq to 62
lola: TRANS 2: GiveAppoint is minimal, eq to 2
lola: TRANS 1: DisplayReqDocs is minimal, eq to 1
lola: TRANS 65: BringReqtoCINFORMI is minimal, eq to 65
lola: HLNOFINDLOW
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13 EFEG EXCL 9/214 1/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04 29852 m, 3584 m/sec, 41221 t fired, .

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13 EFEG EXCL 15/214 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04 67311 m, 4156 m/sec, 93043 t fired, .

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13 EFEG EXCL 20/214 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04 86745 m, 3886 m/sec, 120174 t fired, .

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13 EFEG EXCL 25/214 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04 105371 m, 3725 m/sec, 147755 t fired, .

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13 EFEG EXCL 30/214 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04 126362 m, 4198 m/sec, 177709 t fired, .

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13 EFEG EXCL 35/214 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04 148221 m, 4371 m/sec, 209512 t fired, .

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13 EFEG EXCL 40/214 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04 168857 m, 4127 m/sec, 237775 t fired, .

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13 EFEG EXCL 45/214 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04 189165 m, 4061 m/sec, 266605 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 185/218 6/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 311187 m, 1328 m/sec, 1125271 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 190/218 6/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 318128 m, 1388 m/sec, 1155980 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 1 0 0 1 0 0 0
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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 195/218 6/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 327588 m, 1892 m/sec, 1185900 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 200/218 7/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 335865 m, 1655 m/sec, 1215993 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 205/218 7/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 343176 m, 1462 m/sec, 1246385 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

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46 CTL EXCL 210/218 7/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 352017 m, 1768 m/sec, 1277868 t fired, .

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46 CTL EXCL 215/218 7/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 360963 m, 1789 m/sec, 1307608 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 4/218 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 12008 m, -69791 m/sec, 28721 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

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46 CTL EXCL 9/218 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 22054 m, 2009 m/sec, 61169 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 14/218 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 30919 m, 1773 m/sec, 94061 t fired, .

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46 CTL EXCL 19/218 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 42700 m, 2356 m/sec, 125724 t fired, .

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46 CTL EXCL 39/218 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 87264 m, 2399 m/sec, 254674 t fired, .

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46 CTL EXCL 44/218 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 95875 m, 1722 m/sec, 287213 t fired, .

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46 CTL EXCL 49/218 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15 103968 m, 1618 m/sec, 321874 t fired, .

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28 CTL EXCL 20/224 1/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09 27887 m, 1243 m/sec, 124990 t fired, .
31 CTL EXCL 19/205 1/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 34563 m, 1474 m/sec, 123902 t fired, .

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28 CTL EXCL 30/224 1/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09 42716 m, 1505 m/sec, 190953 t fired, .
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31 CTL EXCL 34/205 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 56560 m, 1475 m/sec, 221653 t fired, .

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31 CTL EXCL 39/205 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 63006 m, 1289 m/sec, 253582 t fired, .

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28 CTL EXCL 45/224 2/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09 64820 m, 1467 m/sec, 287992 t fired, .
31 CTL EXCL 44/205 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 70275 m, 1453 m/sec, 285523 t fired, .

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28 CTL EXCL 50/224 2/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09 70984 m, 1232 m/sec, 319422 t fired, .
31 CTL EXCL 49/205 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 78480 m, 1641 m/sec, 316322 t fired, .

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31 CTL EXCL 54/205 2/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 86183 m, 1540 m/sec, 349217 t fired, .

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28 CTL EXCL 60/224 2/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09 85488 m, 1389 m/sec, 381210 t fired, .
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31 CTL EXCL 64/205 3/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 99745 m, 1271 m/sec, 414469 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 70/224 2/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09 99510 m, 1223 m/sec, 445310 t fired, .
31 CTL EXCL 69/205 3/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 107465 m, 1544 m/sec, 446780 t fired, .

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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-01: AXAF false state space /EXEG
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-11: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 75/224 3/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09 104742 m, 1046 m/sec, 476774 t fired, .
31 CTL EXCL 74/205 3/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 114833 m, 1473 m/sec, 478775 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10: CTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-13: AFAG 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 80/224 3/32 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-09 110844 m, 1220 m/sec, 509382 t fired, .
31 CTL EXCL 79/205 3/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-10 123026 m, 1638 m/sec, 511010 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-04: EFEG 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00020M0002C001P001G001-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00020M0002C001P001G001"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00020M0002C001P001G001, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r080-tall-162048871500849"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00020M0002C001P001G001.tgz
mv FamilyReunion-COL-L00020M0002C001P001G001 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;