About the Execution of LoLA for FamilyReunion-COL-L00010M0001C001P001G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4344.964 | 575498.00 | 566397.00 | 1257.90 | T?FFF?????TFFT?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r080-tall-162048871500845.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r080-tall-162048871500845
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 13K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 130K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 81K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 16:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 16:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Mar 28 16:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 16:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Mar 23 10:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 23 10:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.6K Mar 22 18:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 22 18:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Mar 22 09:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Mar 22 09:11 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 24 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 134K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-00
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-01
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-02
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-03
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-04
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-05
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-06
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-07
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-08
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-09
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-10
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-11
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-12
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-13
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-14
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-15
=== Now, execution of the tool begins
BK_START 1620566851224
starting LoLA
BK_INPUT FamilyReunion-COL-L00010M0001C001P001G001
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620567426722
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: NOTDEADLOCKFREE
lola: start findlow
lola: CHECK FINDLOW FOR TRANS Gate2ANDJoin
lola: TR BINDINGS
lola: NOTDEADLOCKFREE
lola: INVENT VAR FOR PLACE l29
lola: INVENT VAR FOR PLACE l27
lola: INVENT VAR FOR PLACE l26
lola: INVENT VAR FOR PLACE l28
lola: CHECK EQ TRANS Gate2ANDJoin
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: TR BINDINGS DONE
lola: Places: 1486, Transitions: 1234
lola: findlow criterion violated for transition 59
lola: @ trans RegisterRelativePubHealth
lola: @ trans Gate1XORSplit
lola: @ trans ObtainMissingDocs
lola: @ trans DisplayReqDocs
lola: @ trans Gate2ANDJoin
lola: @ trans SummonApplicant
lola: @ trans GotIt
lola: @ trans Gate3XORSplit
lola: @ trans HousingSuitCertifObtained
lola: @ trans CheckRequiredDoc
lola: @ trans ReceiveRegsitration
lola: @ trans ProvidePersonalnfo
lola: @ trans AppReqReceived
lola: @ trans ReserveAppoint
lola: @ trans SendClearanceToRel
lola: @ trans SendLangChoice
lola: @ trans ObtainRelativeFinStatement
lola: @ trans TransmitReq
lola: @ trans TickDocsObtained
lola: @ trans ReceiveAccessReq
lola: @ trans ReceiveLangChoice
lola: @ trans ReqHousingSuitCertif
lola: @ trans BringReqtoCINFORMI
lola: CHECK FINDLOW FOR TRANS GotIt
lola: @ trans ExplainHowToObtainMissingDocs
lola: @ trans SendSuitabilityCertif
lola: @ trans EvaluateReq
lola: @ trans CheckHousingSuitReq
lola: @ trans ReceiveAppoint
lola: @ trans DisplayLangChoice
lola: @ trans Gate1ANDJoin
lola: @ trans Gate2XORSplit
lola: @ trans RegisterRelative
lola: @ trans Summoned
lola: @ trans PrepIncomeCertif
lola: @ trans Gate1ANDSplit
lola: @ trans ReceiveQuestion
lola: @ trans RespReceived
lola: INVENT VAR FOR PLACE lc0
lola: INVENT VAR FOR PLACE cl1
lola: CHECK EQ TRANS GotIt
lola: @ trans PrepFamReuClearReq
lola: @ trans ReqAppointCINFORMI
lola: @ trans GoToAppoint
lola: @ trans GotoOSSAndProdDoc
lola: @ trans ArchiveReq
lola: @ trans Gate2ANDSplit
lola: @ trans ReceiveDocsObtained
lola: @ trans AppointReceived
lola: @ trans CheckSanityReq
lola: @ trans ReceiveInstructions
lola: @ trans AccessMicTerminal
lola: @ trans SetUpAppoint
lola: @ trans ReceiveReqDocsReq
lola: @ trans ReceiveLangReq
lola: @ trans CommunicateResp
lola: @ trans ObtainRelHealtCondStatement
lola: @ trans GiveAppoint
lola: @ trans ReserveAppCINFORMI
lola: @ trans ChoseFamilyReunion
lola: @ trans Gate1XORJoin
lola: @ trans ClearanceReqReceived
lola: @ trans ReceiveNeedReq
lola: @ trans ExplainProcedure
lola: @ trans ReceiveHousingSuitCertifReq
lola: @ trans ObtainFamRelCertif
lola: @ trans ReceiveAppointReq
lola: @ trans ReceiveNeedChoice
lola: @ trans DisplayNeedChoice
lola: @ trans AskCINFORMI
lola: findlow criterion violated for transition 64
lola: CHECK FINDLOW FOR TRANS HousingSuitCertifObtained
lola: INVENT VAR FOR PLACE pl0
lola: INVENT VAR FOR PLACE l18
lola: CHECK EQ TRANS HousingSuitCertifObtained
lola: findlow criterion violated for transition 63
lola: CHECK FINDLOW FOR TRANS ReceiveAccessReq
lola: INVENT VAR FOR PLACE m0
lola: INVENT VAR FOR PLACE lm0
lola: CHECK EQ TRANS ReceiveAccessReq
lola: CHECK FINDLOW FOR TRANS ReceiveNeedReq
lola: INVENT VAR FOR PLACE ml1
lola: INVENT VAR FOR PLACE l3
lola: CHECK EQ TRANS ReceiveNeedReq
lola: findlow criterion violated for transition 4
lola: CHECK FINDLOW FOR TRANS ReceiveNeedChoice
lola: INVENT VAR FOR PLACE m4
lola: INVENT VAR FOR PLACE lm2
lola: CHECK EQ TRANS ReceiveNeedChoice
lola: findlow criterion violated for transition 5
lola: CHECK FINDLOW FOR TRANS ReceiveDocsObtained
lola: INVENT VAR FOR PLACE lm3
lola: INVENT VAR FOR PLACE m6
lola: CHECK EQ TRANS ReceiveDocsObtained
lola: findlow criterion violated for transition 6
lola: CHECK FINDLOW FOR TRANS ReceiveHousingSuitCertifReq
lola: INVENT VAR FOR PLACE p0
lola: INVENT VAR FOR PLACE lp0
lola: CHECK EQ TRANS ReceiveHousingSuitCertifReq
lola: CHECK FINDLOW FOR TRANS ReceiveRegsitration
lola: INVENT VAR FOR PLACE l20
lola: INVENT VAR FOR PLACE pl1
lola: CHECK EQ TRANS ReceiveRegsitration
lola: findlow criterion violated for transition 58
lola: CHECK FINDLOW FOR TRANS CheckRequiredDoc
lola: INVENT VAR FOR PLACE c4
lola: INVENT VAR FOR PLACE lc2
lola: CHECK EQ TRANS CheckRequiredDoc
lola: CHECK FINDLOW FOR TRANS Summoned
lola: INVENT VAR FOR PLACE gl0
lola: INVENT VAR FOR PLACE l34
lola: CHECK EQ TRANS Summoned
lola: findlow criterion violated for transition 53
lola: CHECK FINDLOW FOR TRANS AppReqReceived
lola: INVENT VAR FOR PLACE c2
lola: INVENT VAR FOR PLACE lc1
lola: CHECK EQ TRANS AppReqReceived
lola: CHECK FINDLOW FOR TRANS Gate1ANDJoin
lola: INVENT VAR FOR PLACE p5
lola: INVENT VAR FOR PLACE p4
lola: CHECK EQ TRANS Gate1ANDJoin
lola: findlow criterion violated for transition 12
lola: CHECK FINDLOW FOR TRANS Gate1XORJoin
lola: INVENT VAR FOR PLACE l16
lola: INVENT VAR FOR PLACE l15
lola: CHECK EQ TRANS Gate1XORJoin
lola: findlow criterion violated for transition 13
lola: CHECK FINDLOW FOR TRANS ReceiveInstructions
lola: INVENT VAR FOR PLACE ml3
lola: INVENT VAR FOR PLACE l7
lola: CHECK EQ TRANS ReceiveInstructions
lola: findlow criterion violated for transition 50
lola: CHECK FINDLOW FOR TRANS ClearanceReqReceived
lola: INVENT VAR FOR PLACE g0
lola: INVENT VAR FOR PLACE cg0
lola: CHECK EQ TRANS ClearanceReqReceived
lola: CHECK FINDLOW FOR TRANS ReceiveLangChoice
lola: INVENT VAR FOR PLACE lm1
lola: INVENT VAR FOR PLACE m2
lola: CHECK EQ TRANS ReceiveLangChoice
lola: findlow criterion violated for transition 45
lola: CHECK FINDLOW FOR TRANS PrepFamReuClearReq
lola: INVENT VAR FOR PLACE lc3
lola: INVENT VAR FOR PLACE c5
lola: CHECK EQ TRANS PrepFamReuClearReq
lola: findlow criterion violated for transition 43
lola: CHECK FINDLOW FOR TRANS EvaluateReq
lola: INVENT VAR FOR PLACE lg0
lola: INVENT VAR FOR PLACE g2
lola: CHECK EQ TRANS EvaluateReq
lola: CHECK FINDLOW FOR TRANS RegisterRelative
lola: INVENT VAR FOR PLACE p10
lola: INVENT VAR FOR PLACE lp1
lola: CHECK EQ TRANS RegisterRelative
lola: CHECK FINDLOW FOR TRANS ReceiveAppointReq
lola: INVENT VAR FOR PLACE m8
lola: INVENT VAR FOR PLACE lm4
lola: CHECK EQ TRANS ReceiveAppointReq
lola: CHECK FINDLOW FOR TRANS ReceiveAppoint
lola: INVENT VAR FOR PLACE l10
lola: INVENT VAR FOR PLACE ml4
lola: CHECK EQ TRANS ReceiveAppoint
lola: findlow criterion violated for transition 39
lola: CHECK FINDLOW FOR TRANS ReceiveLangReq
lola: INVENT VAR FOR PLACE ml0
lola: INVENT VAR FOR PLACE l1
lola: CHECK EQ TRANS ReceiveLangReq
lola: findlow criterion violated for transition 35
lola: CHECK FINDLOW FOR TRANS RespReceived
lola: INVENT VAR FOR PLACE gl1
lola: INVENT VAR FOR PLACE l36
lola: CHECK EQ TRANS RespReceived
lola: findlow criterion violated for transition 34
lola: CHECK FINDLOW FOR TRANS CommunicateResp
lola: INVENT VAR FOR PLACE r0
lola: INVENT VAR FOR PLACE g3
lola: CHECK EQ TRANS CommunicateResp
lola: CHECK FINDLOW FOR TRANS ReceiveQuestion
lola: INVENT VAR FOR PLACE c0
lola: INVENT VAR FOR PLACE l14
lola: CHECK EQ TRANS ReceiveQuestion
lola: CHECK FINDLOW FOR TRANS ReceiveReqDocsReq
lola: INVENT VAR FOR PLACE l5
lola: INVENT VAR FOR PLACE ml2
lola: CHECK EQ TRANS ReceiveReqDocsReq
lola: findlow criterion violated for transition 26
lola: CHECK FINDLOW FOR TRANS AppointReceived
lola: INVENT VAR FOR PLACE l31
lola: INVENT VAR FOR PLACE cl2
lola: CHECK EQ TRANS AppointReceived
lola: findlow criterion violated for transition 29
lola: CHECK FINDLOW FOR TRANS SendClearanceToRel
lola: INVENT VAR FOR PLACE l39
lola: CHECK EQ TRANS SendClearanceToRel
lola: findlow criterion violated for transition 28
lola: CHECK FINDLOW FOR TRANS ReqAppointCINFORMI
lola: INVENT VAR FOR PLACE l9
lola: CHECK EQ TRANS ReqAppointCINFORMI
lola: CHECK FINDLOW FOR TRANS GotoOSSAndProdDoc
lola: INVENT VAR FOR PLACE l35
lola: CHECK EQ TRANS GotoOSSAndProdDoc
lola: CHECK FINDLOW FOR TRANS Gate1XORSplit
lola: INVENT VAR FOR PLACE l12
lola: CHECK EQ TRANS Gate1XORSplit
lola: CHECK FINDLOW FOR TRANS ObtainFamRelCertif
lola: INVENT VAR FOR PLACE l25
lola: CHECK EQ TRANS ObtainFamRelCertif
lola: CHECK FINDLOW FOR TRANS AskCINFORMI
lola: INVENT VAR FOR PLACE l13
lola: CHECK EQ TRANS AskCINFORMI
lola: CHECK FINDLOW FOR TRANS AccessMicTerminal
lola: INVENT VAR FOR PLACE l0
lola: CHECK EQ TRANS AccessMicTerminal
lola: CHECK FINDLOW FOR TRANS DisplayLangChoice
lola: INVENT VAR FOR PLACE m1
lola: CHECK EQ TRANS DisplayLangChoice
lola: CHECK FINDLOW FOR TRANS TransmitReq
lola: INVENT VAR FOR PLACE c6
lola: CHECK EQ TRANS TransmitReq
lola: CHECK FINDLOW FOR TRANS SummonApplicant
lola: INVENT VAR FOR PLACE g1
lola: CHECK EQ TRANS SummonApplicant
lola: CHECK FINDLOW FOR TRANS SendSuitabilityCertif
lola: INVENT VAR FOR PLACE p9
lola: CHECK EQ TRANS SendSuitabilityCertif
lola: CHECK FINDLOW FOR TRANS GoToAppoint
lola: INVENT VAR FOR PLACE l11
lola: CHECK EQ TRANS GoToAppoint
lola: CHECK FINDLOW FOR TRANS ReserveAppoint
lola: INVENT VAR FOR PLACE m9
lola: CHECK EQ TRANS ReserveAppoint
lola: CHECK FINDLOW FOR TRANS ProvidePersonalnfo
lola: INVENT VAR FOR PLACE l33
lola: CHECK EQ TRANS ProvidePersonalnfo
lola: CHECK FINDLOW FOR TRANS ExplainHowToObtainMissingDocs
lola: INVENT VAR FOR PLACE m7
lola: CHECK EQ TRANS ExplainHowToObtainMissingDocs
lola: CHECK FINDLOW FOR TRANS SendLangChoice
lola: INVENT VAR FOR PLACE l2
lola: CHECK EQ TRANS SendLangChoice
lola: CHECK FINDLOW FOR TRANS ObtainRelativeFinStatement
lola: INVENT VAR FOR PLACE l24
lola: CHECK EQ TRANS ObtainRelativeFinStatement
lola: CHECK FINDLOW FOR TRANS ReserveAppCINFORMI
lola: INVENT VAR FOR PLACE l30
lola: CHECK EQ TRANS ReserveAppCINFORMI
lola: CHECK FINDLOW FOR TRANS TickDocsObtained
lola: INVENT VAR FOR PLACE l6
lola: CHECK EQ TRANS TickDocsObtained
lola: CHECK FINDLOW FOR TRANS ArchiveReq
lola: INVENT VAR FOR PLACE p7
lola: CHECK EQ TRANS ArchiveReq
lola: CHECK FINDLOW FOR TRANS CheckSanityReq
lola: INVENT VAR FOR PLACE p3
lola: CHECK EQ TRANS CheckSanityReq
lola: CHECK FINDLOW FOR TRANS Gate1ANDSplit
lola: INVENT VAR FOR PLACE p1
lola: CHECK EQ TRANS Gate1ANDSplit
lola: CHECK FINDLOW FOR TRANS SetUpAppoint
lola: INVENT VAR FOR PLACE c3
lola: CHECK EQ TRANS SetUpAppoint
lola: CHECK FINDLOW FOR TRANS ReqHousingSuitCertif
lola: INVENT VAR FOR PLACE l17
lola: CHECK EQ TRANS ReqHousingSuitCertif
lola: CHECK FINDLOW FOR TRANS DisplayNeedChoice
lola: INVENT VAR FOR PLACE m3
lola: CHECK EQ TRANS DisplayNeedChoice
lola: CHECK FINDLOW FOR TRANS Gate2XORSplit
lola: INVENT VAR FOR PLACE p6
lola: CHECK EQ TRANS Gate2XORSplit
lola: CHECK FINDLOW FOR TRANS ObtainRelHealtCondStatement
lola: INVENT VAR FOR PLACE l23
lola: CHECK EQ TRANS ObtainRelHealtCondStatement
lola: CHECK FINDLOW FOR TRANS ChoseFamilyReunion
lola: INVENT VAR FOR PLACE l4
lola: CHECK EQ TRANS ChoseFamilyReunion
lola: CHECK FINDLOW FOR TRANS ObtainMissingDocs
lola: INVENT VAR FOR PLACE l8
lola: CHECK EQ TRANS ObtainMissingDocs
lola: CHECK FINDLOW FOR TRANS ExplainProcedure
lola: INVENT VAR FOR PLACE cl0
lola: CHECK EQ TRANS ExplainProcedure
lola: CHECK FINDLOW FOR TRANS CheckHousingSuitReq
lola: INVENT VAR FOR PLACE p2
lola: CHECK EQ TRANS CheckHousingSuitReq
lola: CHECK FINDLOW FOR TRANS RegisterRelativePubHealth
lola: INVENT VAR FOR PLACE l19
lola: CHECK EQ TRANS RegisterRelativePubHealth
lola: CHECK FINDLOW FOR TRANS PrepIncomeCertif
lola: INVENT VAR FOR PLACE l22
lola: CHECK EQ TRANS PrepIncomeCertif
lola: CHECK FINDLOW FOR TRANS Gate3XORSplit
lola: INVENT VAR FOR PLACE l37
lola: CHECK EQ TRANS Gate3XORSplit
lola: CHECK FINDLOW FOR TRANS Gate2ANDSplit
lola: INVENT VAR FOR PLACE l21
lola: CHECK EQ TRANS Gate2ANDSplit
lola: CHECK FINDLOW FOR TRANS GiveAppoint
lola: INVENT VAR FOR PLACE m10
lola: CHECK EQ TRANS GiveAppoint
lola: CHECK FINDLOW FOR TRANS DisplayReqDocs
lola: INVENT VAR FOR PLACE m5
lola: CHECK EQ TRANS DisplayReqDocs
lola: CHECK FINDLOW FOR TRANS BringReqtoCINFORMI
lola: INVENT VAR FOR PLACE l32
lola: CHECK EQ TRANS BringReqtoCINFORMI
lola: findlow criterion violated for 19 clusters
lola: Time for checking findlow: 4.000000
lola: TRANS 59: Gate2ANDJoin is minimal, eq to 59
lola: TRANS 64: GotIt is minimal, eq to 64
lola: TRANS 63: HousingSuitCertifObtained is minimal, eq to 63
lola: TRANS 60: ReceiveAccessReq is minimal, eq to 60
lola: TRANS 4: ReceiveNeedReq is minimal, eq to 4
lola: TRANS 5: ReceiveNeedChoice is minimal, eq to 5
lola: TRANS 6: ReceiveDocsObtained is minimal, eq to 6
lola: TRANS 0: ReceiveHousingSuitCertifReq is minimal, eq to 0
lola: TRANS 58: ReceiveRegsitration is minimal, eq to 58
lola: TRANS 54: CheckRequiredDoc is minimal, eq to 54
lola: TRANS 53: Summoned is minimal, eq to 53
lola: TRANS 11: AppReqReceived is minimal, eq to 11
lola: TRANS 12: Gate1ANDJoin is minimal, eq to 12
lola: TRANS 13: Gate1XORJoin is minimal, eq to 13
lola: TRANS 50: ReceiveInstructions is minimal, eq to 50
lola: TRANS 49: ClearanceReqReceived is minimal, eq to 49
lola: TRANS 45: ReceiveLangChoice is minimal, eq to 45
lola: TRANS 43: PrepFamReuClearReq is minimal, eq to 43
lola: TRANS 18: EvaluateReq is minimal, eq to 18
lola: TRANS 42: RegisterRelative is minimal, eq to 42
lola: TRANS 41: ReceiveAppointReq is minimal, eq to 41
lola: TRANS 39: ReceiveAppoint is minimal, eq to 39
lola: TRANS 35: ReceiveLangReq is minimal, eq to 35
lola: TRANS 34: RespReceived is minimal, eq to 34
lola: TRANS 24: CommunicateResp is minimal, eq to 24
lola: TRANS 32: ReceiveQuestion is minimal, eq to 32
lola: TRANS 26: ReceiveReqDocsReq is minimal, eq to 26
lola: TRANS 29: AppointReceived is minimal, eq to 29
lola: TRANS 28: SendClearanceToRel is minimal, eq to 28
lola: TRANS 27: ReqAppointCINFORMI is minimal, eq to 27
lola: TRANS 30: GotoOSSAndProdDoc is minimal, eq to 30
lola: TRANS 31: Gate1XORSplit is minimal, eq to 31
lola: TRANS 25: ObtainFamRelCertif is minimal, eq to 25
lola: TRANS 33: AskCINFORMI is minimal, eq to 33
lola: TRANS 23: AccessMicTerminal is minimal, eq to 23
lola: TRANS 22: DisplayLangChoice is minimal, eq to 22
lola: TRANS 36: TransmitReq is minimal, eq to 36
lola: TRANS 37: SummonApplicant is minimal, eq to 37
lola: TRANS 38: SendSuitabilityCertif is minimal, eq to 38
lola: TRANS 21: GoToAppoint is minimal, eq to 21
lola: TRANS 40: ReserveAppoint is minimal, eq to 40
lola: TRANS 20: ProvidePersonalnfo is minimal, eq to 20
lola: TRANS 19: ExplainHowToObtainMissingDocs is minimal, eq to 19
lola: TRANS 17: SendLangChoice is minimal, eq to 17
lola: TRANS 44: ObtainRelativeFinStatement is minimal, eq to 44
lola: TRANS 16: ReserveAppCINFORMI is minimal, eq to 16
lola: TRANS 46: TickDocsObtained is minimal, eq to 46
lola: TRANS 47: ArchiveReq is minimal, eq to 47
lola: TRANS 48: CheckSanityReq is minimal, eq to 48
lola: TRANS 15: Gate1ANDSplit is minimal, eq to 15
lola: TRANS 14: SetUpAppoint is minimal, eq to 14
lola: TRANS 51: ReqHousingSuitCertif is minimal, eq to 51
lola: TRANS 52: DisplayNeedChoice is minimal, eq to 52
lola: TRANS 10: Gate2XORSplit is minimal, eq to 10
lola: TRANS 9: ObtainRelHealtCondStatement is minimal, eq to 9
lola: TRANS 55: ChoseFamilyReunion is minimal, eq to 55
lola: TRANS 56: ObtainMissingDocs is minimal, eq to 56
lola: TRANS 57: ExplainProcedure is minimal, eq to 57
lola: TRANS 8: CheckHousingSuitReq is minimal, eq to 8
lola: TRANS 7: RegisterRelativePubHealth is minimal, eq to 7
lola: TRANS 3: PrepIncomeCertif is minimal, eq to 3
lola: TRANS 61: Gate3XORSplit is minimal, eq to 61
lola: TRANS 62: Gate2ANDSplit is minimal, eq to 62
lola: TRANS 2: GiveAppoint is minimal, eq to 2
lola: TRANS 1: DisplayReqDocs is minimal, eq to 1
lola: TRANS 65: BringReqtoCINFORMI is minimal, eq to 65
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
lola: HLNOFINDLOW
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 0 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 1 0 0 0 0 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 1 0 0 0 0 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-12: AG 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 5 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 0 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 1 0 0 0 0 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 1 0 0 0 0 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-12: AG 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 10 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 0 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 1 0 0 0 0 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 1 0 0 0 0 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-12: AG 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 15 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 0 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 1 0 0 0 0 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 1 0 0 0 0 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-12: AG 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 20 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: RELEASE
lola: Rule S: 0 transitions removed,11 places removed
lola: LAUNCH task # 52 (type SKEL/SRCH) for 28 FamilyReunion-COL-L00010M0001C001P001G001-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SKEL/SRCH) for 16 FamilyReunion-COL-L00010M0001C001P001G001-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type SKEL/SRCH) for FamilyReunion-COL-L00010M0001C001P001G001-04
lola: result : false
lola: markings : 646
lola: fired transitions : 646
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 52 (type SKEL/SRCH) for FamilyReunion-COL-L00010M0001C001P001G001-08
lola: result : false
lola: markings : 646
lola: fired transitions : 646
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 57 (type EXCL) for 40 FamilyReunion-COL-L00010M0001C001P001G001-12
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 40 FamilyReunion-COL-L00010M0001C001P001G001-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 40 FamilyReunion-COL-L00010M0001C001P001G001-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SRCH) for 40 FamilyReunion-COL-L00010M0001C001P001G001-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 58 (type SRCH) for FamilyReunion-COL-L00010M0001C001P001G001-12
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
lola: FINISHED task # 57 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-12
lola: result : true
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 55 (type FNDP) for FamilyReunion-COL-L00010M0001C001P001G001-12 (obsolete)
lola: CANCELED task # 56 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-12 (obsolete)
lola: LAUNCH task # 47 (type EXCL) for 46 FamilyReunion-COL-L00010M0001C001P001G001-14
lola: time limit : 223 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/LTLFireability-56.sara.
lola: FINISHED task # 55 (type FNDP) for FamilyReunion-COL-L00010M0001C001P001G001-12
lola: result : true
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 56 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-12
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 2/223 2/32 FamilyReunion-COL-L00010M0001C001P001G001-14 158606 m, 31721 m/sec, 422877 t fired, .
Time elapsed: 25 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 7/223 5/32 FamilyReunion-COL-L00010M0001C001P001G001-14 539948 m, 76268 m/sec, 1450740 t fired, .
Time elapsed: 30 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 12/223 8/32 FamilyReunion-COL-L00010M0001C001P001G001-14 906975 m, 73405 m/sec, 2481535 t fired, .
Time elapsed: 35 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 17/223 11/32 FamilyReunion-COL-L00010M0001C001P001G001-14 1262785 m, 71162 m/sec, 3515157 t fired, .
Time elapsed: 40 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 22/223 14/32 FamilyReunion-COL-L00010M0001C001P001G001-14 1617502 m, 70943 m/sec, 4547640 t fired, .
Time elapsed: 45 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 27/223 17/32 FamilyReunion-COL-L00010M0001C001P001G001-14 1973627 m, 71225 m/sec, 5581438 t fired, .
Time elapsed: 50 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 32/223 20/32 FamilyReunion-COL-L00010M0001C001P001G001-14 2329196 m, 71113 m/sec, 6617588 t fired, .
Time elapsed: 55 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 37/223 22/32 FamilyReunion-COL-L00010M0001C001P001G001-14 2683887 m, 70938 m/sec, 7650302 t fired, .
Time elapsed: 60 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 42/223 25/32 FamilyReunion-COL-L00010M0001C001P001G001-14 3036020 m, 70426 m/sec, 8676516 t fired, .
Time elapsed: 65 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 47/223 28/32 FamilyReunion-COL-L00010M0001C001P001G001-14 3386978 m, 70191 m/sec, 9705046 t fired, .
Time elapsed: 70 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 LTL EXCL 52/223 31/32 FamilyReunion-COL-L00010M0001C001P001G001-14 3737193 m, 70043 m/sec, 10730659 t fired, .
Time elapsed: 75 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 47 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 50 (type EXCL) for 49 FamilyReunion-COL-L00010M0001C001P001G001-15
lola: time limit : 234 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-15
lola: result : false
lola: markings : 645
lola: fired transitions : 646
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 FamilyReunion-COL-L00010M0001C001P001G001-13
lola: time limit : 251 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 FamilyReunion-COL-L00010M0001C001P001G001-10
lola: time limit : 270 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-10
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 FamilyReunion-COL-L00010M0001C001P001G001-09
lola: time limit : 293 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 5/293 5/32 FamilyReunion-COL-L00010M0001C001P001G001-09 396579 m, 79315 m/sec, 550750 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 10/293 9/32 FamilyReunion-COL-L00010M0001C001P001G001-09 774512 m, 75586 m/sec, 1100866 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 15/293 13/32 FamilyReunion-COL-L00010M0001C001P001G001-09 1157723 m, 76642 m/sec, 1648886 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 20/293 17/32 FamilyReunion-COL-L00010M0001C001P001G001-09 1545173 m, 77490 m/sec, 2198550 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 25/293 20/32 FamilyReunion-COL-L00010M0001C001P001G001-09 1916192 m, 74203 m/sec, 2739437 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 30/293 24/32 FamilyReunion-COL-L00010M0001C001P001G001-09 2282752 m, 73312 m/sec, 3285545 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 35/293 28/32 FamilyReunion-COL-L00010M0001C001P001G001-09 2648500 m, 73149 m/sec, 3836230 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 LTL EXCL 40/293 32/32 FamilyReunion-COL-L00010M0001C001P001G001-09 2977633 m, 65826 m/sec, 4388734 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 32 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 29 (type EXCL) for 28 FamilyReunion-COL-L00010M0001C001P001G001-08
lola: time limit : 315 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 5/315 3/32 FamilyReunion-COL-L00010M0001C001P001G001-08 132058 m, 26411 m/sec, 596659 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 10/315 5/32 FamilyReunion-COL-L00010M0001C001P001G001-08 259471 m, 25482 m/sec, 1190359 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 15/315 6/32 FamilyReunion-COL-L00010M0001C001P001G001-08 380385 m, 24182 m/sec, 1783447 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 20/315 8/32 FamilyReunion-COL-L00010M0001C001P001G001-08 501731 m, 24269 m/sec, 2375191 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 25/315 10/32 FamilyReunion-COL-L00010M0001C001P001G001-08 607702 m, 21194 m/sec, 2966808 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 30/315 11/32 FamilyReunion-COL-L00010M0001C001P001G001-08 698289 m, 18117 m/sec, 3558011 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 35/315 13/32 FamilyReunion-COL-L00010M0001C001P001G001-08 819209 m, 24184 m/sec, 4137718 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 40/315 15/32 FamilyReunion-COL-L00010M0001C001P001G001-08 943254 m, 24809 m/sec, 4723351 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 45/315 16/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1053400 m, 22029 m/sec, 5316552 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 50/315 18/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1161516 m, 21623 m/sec, 5906395 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 55/315 20/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1257042 m, 19105 m/sec, 6495535 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 60/315 21/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1348705 m, 18332 m/sec, 7083908 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 65/315 22/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1457110 m, 21681 m/sec, 7659011 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 70/315 24/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1581076 m, 24793 m/sec, 8236340 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 75/315 26/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1704032 m, 24591 m/sec, 8818408 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 80/315 27/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1810202 m, 21234 m/sec, 9404720 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 85/315 29/32 FamilyReunion-COL-L00010M0001C001P001G001-08 1926964 m, 23352 m/sec, 9976575 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 90/315 31/32 FamilyReunion-COL-L00010M0001C001P001G001-08 2044538 m, 23514 m/sec, 10555575 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 95/315 32/32 FamilyReunion-COL-L00010M0001C001P001G001-08 2164483 m, 23989 m/sec, 11151733 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 29 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 25 FamilyReunion-COL-L00010M0001C001P001G001-07
lola: time limit : 337 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 5/337 1/32 FamilyReunion-COL-L00010M0001C001P001G001-07 109264 m, 21852 m/sec, 582044 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 10/337 2/32 FamilyReunion-COL-L00010M0001C001P001G001-07 208898 m, 19926 m/sec, 1164801 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 15/337 3/32 FamilyReunion-COL-L00010M0001C001P001G001-07 310343 m, 20289 m/sec, 1743514 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 20/337 4/32 FamilyReunion-COL-L00010M0001C001P001G001-07 412811 m, 20493 m/sec, 2328413 t fired, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 25/337 4/32 FamilyReunion-COL-L00010M0001C001P001G001-07 511661 m, 19770 m/sec, 2914910 t fired, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 30/337 5/32 FamilyReunion-COL-L00010M0001C001P001G001-07 619106 m, 21489 m/sec, 3495190 t fired, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 35/337 6/32 FamilyReunion-COL-L00010M0001C001P001G001-07 720097 m, 20198 m/sec, 4078335 t fired, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 40/337 6/32 FamilyReunion-COL-L00010M0001C001P001G001-07 820055 m, 19991 m/sec, 4655339 t fired, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 45/337 7/32 FamilyReunion-COL-L00010M0001C001P001G001-07 922534 m, 20495 m/sec, 5237103 t fired, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 50/337 8/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1020513 m, 19595 m/sec, 5824664 t fired, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 55/337 9/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1118246 m, 19546 m/sec, 6406831 t fired, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 60/337 9/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1222506 m, 20852 m/sec, 6999783 t fired, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 65/337 10/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1325242 m, 20547 m/sec, 7585624 t fired, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 70/337 11/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1421154 m, 19182 m/sec, 8165247 t fired, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 75/337 12/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1510420 m, 17853 m/sec, 8748948 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 80/337 12/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1601356 m, 18187 m/sec, 9330796 t fired, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 85/337 13/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1693426 m, 18414 m/sec, 9919634 t fired, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 90/337 14/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1781104 m, 17535 m/sec, 10506577 t fired, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 95/337 14/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1877787 m, 19336 m/sec, 11086854 t fired, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 100/337 15/32 FamilyReunion-COL-L00010M0001C001P001G001-07 1967394 m, 17921 m/sec, 11668928 t fired, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 105/337 16/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2057655 m, 18052 m/sec, 12248092 t fired, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 110/337 16/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2149505 m, 18370 m/sec, 12833880 t fired, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 115/337 17/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2237259 m, 17550 m/sec, 13422267 t fired, .
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 120/337 17/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2325131 m, 17574 m/sec, 14007918 t fired, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 125/337 18/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2417931 m, 18560 m/sec, 14602370 t fired, .
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 130/337 19/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2513017 m, 19017 m/sec, 15189081 t fired, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 135/337 20/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2609770 m, 19350 m/sec, 15769696 t fired, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 140/337 20/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2703798 m, 18805 m/sec, 16350397 t fired, .
Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 145/337 21/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2797351 m, 18710 m/sec, 16938715 t fired, .
Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 150/337 22/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2891725 m, 18874 m/sec, 17519272 t fired, .
Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 155/337 22/32 FamilyReunion-COL-L00010M0001C001P001G001-07 2988309 m, 19316 m/sec, 18096872 t fired, .
Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 160/337 23/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3079589 m, 18256 m/sec, 18675311 t fired, .
Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 165/337 24/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3173498 m, 18781 m/sec, 19254905 t fired, .
Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 170/337 24/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3266275 m, 18555 m/sec, 19843198 t fired, .
Time elapsed: 395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 175/337 25/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3356136 m, 17972 m/sec, 20422178 t fired, .
Time elapsed: 400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 180/337 26/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3450528 m, 18878 m/sec, 21014166 t fired, .
Time elapsed: 405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 185/337 26/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3546086 m, 19111 m/sec, 21603515 t fired, .
Time elapsed: 410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 190/337 27/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3636279 m, 18038 m/sec, 22184615 t fired, .
Time elapsed: 415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 195/337 28/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3720328 m, 16809 m/sec, 22766296 t fired, .
Time elapsed: 420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 200/337 28/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3804886 m, 16911 m/sec, 23353641 t fired, .
Time elapsed: 425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 205/337 29/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3886108 m, 16244 m/sec, 23940992 t fired, .
Time elapsed: 430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 210/337 30/32 FamilyReunion-COL-L00010M0001C001P001G001-07 3975076 m, 17793 m/sec, 24521592 t fired, .
Time elapsed: 435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 215/337 30/32 FamilyReunion-COL-L00010M0001C001P001G001-07 4058282 m, 16641 m/sec, 25106923 t fired, .
Time elapsed: 440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 220/337 31/32 FamilyReunion-COL-L00010M0001C001P001G001-07 4141564 m, 16656 m/sec, 25686149 t fired, .
Time elapsed: 445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 225/337 31/32 FamilyReunion-COL-L00010M0001C001P001G001-07 4226768 m, 17040 m/sec, 26273595 t fired, .
Time elapsed: 450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 230/337 32/32 FamilyReunion-COL-L00010M0001C001P001G001-07 4308068 m, 16260 m/sec, 26860358 t fired, .
Time elapsed: 455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 26 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 23 (type EXCL) for 22 FamilyReunion-COL-L00010M0001C001P001G001-06
lola: time limit : 348 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 5/348 6/32 FamilyReunion-COL-L00010M0001C001P001G001-06 372390 m, 74478 m/sec, 514823 t fired, .
Time elapsed: 465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 10/348 12/32 FamilyReunion-COL-L00010M0001C001P001G001-06 713285 m, 68179 m/sec, 1030067 t fired, .
Time elapsed: 470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 15/348 17/32 FamilyReunion-COL-L00010M0001C001P001G001-06 1050877 m, 67518 m/sec, 1543827 t fired, .
Time elapsed: 475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 20/348 22/32 FamilyReunion-COL-L00010M0001C001P001G001-06 1369374 m, 63699 m/sec, 2058797 t fired, .
Time elapsed: 480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 25/348 27/32 FamilyReunion-COL-L00010M0001C001P001G001-06 1719296 m, 69984 m/sec, 2566663 t fired, .
Time elapsed: 485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 30/348 31/32 FamilyReunion-COL-L00010M0001C001P001G001-06 2074110 m, 70962 m/sec, 3076227 t fired, .
Time elapsed: 490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 17 (type EXCL) for 16 FamilyReunion-COL-L00010M0001C001P001G001-04
lola: time limit : 388 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-04
lola: result : false
lola: markings : 644
lola: fired transitions : 644
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 FamilyReunion-COL-L00010M0001C001P001G001-03
lola: time limit : 443 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-03
lola: result : false
lola: markings : 644
lola: fired transitions : 644
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 FamilyReunion-COL-L00010M0001C001P001G001-00
lola: time limit : 517 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-00
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 6 FamilyReunion-COL-L00010M0001C001P001G001-02
lola: time limit : 621 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-02
lola: result : false
lola: markings : 354
lola: fired transitions : 354
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 FamilyReunion-COL-L00010M0001C001P001G001-01
lola: time limit : 1035 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 5/1035 5/32 FamilyReunion-COL-L00010M0001C001P001G001-01 362159 m, 72431 m/sec, 618180 t fired, .
Time elapsed: 500 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 10/1035 9/32 FamilyReunion-COL-L00010M0001C001P001G001-01 755143 m, 78596 m/sec, 1295124 t fired, .
Time elapsed: 505 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 15/1035 13/32 FamilyReunion-COL-L00010M0001C001P001G001-01 1168469 m, 82665 m/sec, 2017485 t fired, .
Time elapsed: 510 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 20/1035 18/32 FamilyReunion-COL-L00010M0001C001P001G001-01 1582380 m, 82782 m/sec, 2733926 t fired, .
Time elapsed: 515 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 25/1035 22/32 FamilyReunion-COL-L00010M0001C001P001G001-01 2012287 m, 85981 m/sec, 3496350 t fired, .
Time elapsed: 520 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 30/1035 27/32 FamilyReunion-COL-L00010M0001C001P001G001-01 2433904 m, 84323 m/sec, 4225486 t fired, .
Time elapsed: 525 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 LTL EXCL 35/1035 31/32 FamilyReunion-COL-L00010M0001C001P001G001-01 2861826 m, 85584 m/sec, 4972864 t fired, .
Time elapsed: 530 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 535 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 FamilyReunion-COL-L00010M0001C001P001G001-05
lola: time limit : 1532 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 5/1532 5/32 FamilyReunion-COL-L00010M0001C001P001G001-05 548754 m, 109750 m/sec, 758022 t fired, .
Time elapsed: 540 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 10/1532 9/32 FamilyReunion-COL-L00010M0001C001P001G001-05 1060355 m, 102320 m/sec, 1525235 t fired, .
Time elapsed: 545 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 15/1532 14/32 FamilyReunion-COL-L00010M0001C001P001G001-05 1563824 m, 100693 m/sec, 2293192 t fired, .
Time elapsed: 550 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 20/1532 18/32 FamilyReunion-COL-L00010M0001C001P001G001-05 2091415 m, 105518 m/sec, 3051548 t fired, .
Time elapsed: 555 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 25/1532 22/32 FamilyReunion-COL-L00010M0001C001P001G001-05 2602193 m, 102155 m/sec, 3805130 t fired, .
Time elapsed: 560 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 30/1532 26/32 FamilyReunion-COL-L00010M0001C001P001G001-05 3103503 m, 100262 m/sec, 4555022 t fired, .
Time elapsed: 565 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 LTL EXCL 35/1532 30/32 FamilyReunion-COL-L00010M0001C001P001G001-05 3569140 m, 93127 m/sec, 5318936 t fired, .
Time elapsed: 570 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 20 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 575 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 38 (type EXCL) for 37 FamilyReunion-COL-L00010M0001C001P001G001-11
lola: time limit : 3025 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-11
lola: result : false
lola: markings : 344
lola: fired transitions : 345
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-01: LTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-05: LTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-06: LTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-07: LTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-08: LTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-09: LTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-10: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-11: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-12: AG false state space
FamilyReunion-COL-L00010M0001C001P001G001-13: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-14: LTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-15: LTL false LTL model checker
Time elapsed: 575 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00010M0001C001P001G001"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r080-tall-162048871500845"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00010M0001C001P001G001.tgz
mv FamilyReunion-COL-L00010M0001C001P001G001 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;