Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r064-tall-162038397200438.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool itstools
Input is DLCround-PT-13a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r064-tall-162038397200438
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 13K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 121K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 95K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Mar 28 15:59 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 15:59 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K Mar 28 15:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 28 15:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Mar 23 09:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K Mar 23 09:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Mar 22 16:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 22 16:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 4 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 987K May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-13a-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1620527863117

Running Version 0
[2021-05-09 02:37:50] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -spotpath, /home/mcc/BenchKit/bin//..//ltlfilt, -z3path, /home/mcc/BenchKit/bin//..//z3/bin/z3, -yices2path, /home/mcc/BenchKit/bin//..//yices/bin/yices, -its, -ltsmin, -greatspnpath, /home/mcc/BenchKit/bin//..//greatspn/, -order, META, -manyOrder, -smt, -timeout, 3600]
[2021-05-09 02:37:50] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2021-05-09 02:37:50] [INFO ] Load time of PNML (sax parser for PT used): 249 ms
[2021-05-09 02:37:50] [INFO ] Transformed 463 places.
[2021-05-09 02:37:50] [INFO ] Transformed 3847 transitions.
[2021-05-09 02:37:50] [INFO ] Found NUPN structural information;
[2021-05-09 02:37:50] [INFO ] Parsed PT model containing 463 places and 3847 transitions in 328 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 9 ms.
Working with output stream class java.io.PrintStream
Ensure Unique test removed 352 transitions
Reduce redundant transitions removed 352 transitions.
FORMULA DLCround-PT-13a-ReachabilityCardinality-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-13a-ReachabilityCardinality-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-13a-ReachabilityCardinality-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-13a-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-13a-ReachabilityCardinality-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-13a-ReachabilityCardinality-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-13a-ReachabilityCardinality-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 244 ms. (steps per millisecond=40 ) properties (out of 9) seen :1
FORMULA DLCround-PT-13a-ReachabilityCardinality-00 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 97 ms. (steps per millisecond=103 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 90 ms. (steps per millisecond=111 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 71 ms. (steps per millisecond=140 ) properties (out of 8) seen :0
Running SMT prover for 8 properties.
[2021-05-09 02:37:51] [INFO ] Flow matrix only has 266 transitions (discarded 3229 similar events)
// Phase 1: matrix 266 rows 463 cols
[2021-05-09 02:37:51] [INFO ] Computed 312 place invariants in 10 ms
[2021-05-09 02:37:51] [INFO ] [Real]Absence check using 312 positive place invariants in 92 ms returned sat
[2021-05-09 02:37:51] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2021-05-09 02:37:51] [INFO ] [Real]Absence check using state equation in 151 ms returned sat
[2021-05-09 02:37:51] [INFO ] Solution in real domain found non-integer solution.
[2021-05-09 02:37:52] [INFO ] [Nat]Absence check using 312 positive place invariants in 52 ms returned unsat
[2021-05-09 02:37:52] [INFO ] [Real]Absence check using 312 positive place invariants in 53 ms returned unsat
[2021-05-09 02:37:52] [INFO ] [Real]Absence check using 312 positive place invariants in 77 ms returned unsat
[2021-05-09 02:37:52] [INFO ] [Real]Absence check using 312 positive place invariants in 64 ms returned sat
[2021-05-09 02:37:52] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2021-05-09 02:37:52] [INFO ] [Real]Absence check using state equation in 156 ms returned sat
[2021-05-09 02:37:52] [INFO ] Solution in real domain found non-integer solution.
[2021-05-09 02:37:52] [INFO ] [Real]Absence check using 312 positive place invariants in 48 ms returned unsat
[2021-05-09 02:37:53] [INFO ] [Real]Absence check using 312 positive place invariants in 47 ms returned sat
[2021-05-09 02:37:53] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2021-05-09 02:37:53] [INFO ] [Real]Absence check using state equation in 89 ms returned sat
[2021-05-09 02:37:53] [INFO ] Solution in real domain found non-integer solution.
[2021-05-09 02:37:53] [INFO ] [Nat]Absence check using 312 positive place invariants in 40 ms returned unsat
[2021-05-09 02:37:53] [INFO ] [Real]Absence check using 312 positive place invariants in 47 ms returned sat
[2021-05-09 02:37:53] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2021-05-09 02:37:53] [INFO ] [Real]Absence check using state equation in 103 ms returned sat
[2021-05-09 02:37:53] [INFO ] Solution in real domain found non-integer solution.
[2021-05-09 02:37:53] [INFO ] [Nat]Absence check using 312 positive place invariants in 17 ms returned unsat
[2021-05-09 02:37:53] [INFO ] [Real]Absence check using 312 positive place invariants in 47 ms returned sat
[2021-05-09 02:37:53] [INFO ] [Real]Adding state equation constraints to refine reachable states.
[2021-05-09 02:37:53] [INFO ] [Real]Absence check using state equation in 96 ms returned sat
[2021-05-09 02:37:53] [INFO ] Solution in real domain found non-integer solution.
[2021-05-09 02:37:53] [INFO ] [Nat]Absence check using 312 positive place invariants in 46 ms returned unsat
FORMULA DLCround-PT-13a-ReachabilityCardinality-15 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA DLCround-PT-13a-ReachabilityCardinality-10 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA DLCround-PT-13a-ReachabilityCardinality-08 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA DLCround-PT-13a-ReachabilityCardinality-05 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA DLCround-PT-13a-ReachabilityCardinality-04 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA DLCround-PT-13a-ReachabilityCardinality-03 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA DLCround-PT-13a-ReachabilityCardinality-02 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA DLCround-PT-13a-ReachabilityCardinality-01 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 8 Parikh solutions to 0 different solutions.
All properties solved without resorting to model-checking.

BK_STOP 1620527877770

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/bin//../
+ BINDIR=/home/mcc/BenchKit/bin//../
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit/bin//..//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//..//greatspn/ -order META -manyOrder -smt -timeout 3600
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
++ cut -d . -f 9
++ ls /home/mcc/BenchKit/bin//..//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202104292328.jar
+ VERSION=0
+ echo 'Running Version 0'
+ /home/mcc/BenchKit/bin//..//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -spotpath /home/mcc/BenchKit/bin//..//ltlfilt -z3path /home/mcc/BenchKit/bin//..//z3/bin/z3 -yices2path /home/mcc/BenchKit/bin//..//yices/bin/yices -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//..//greatspn/ -order META -manyOrder -smt -timeout 3600 -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss128m -Xms40m -Xmx16000m

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-13a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool itstools"
echo " Input is DLCround-PT-13a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r064-tall-162038397200438"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-13a.tgz
mv DLCround-PT-13a execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;