fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r064-tall-162038396900247
Last Updated
Jun 28, 2021

About the Execution of ITS-Tools for DLCflexbar-PT-7a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1034.655 29990.00 41736.00 336.50 TFTTFTFFTTTTTFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r064-tall-162038396900247.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool itstools
Input is DLCflexbar-PT-7a, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r064-tall-162038396900247
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.6M
-rw-r--r-- 1 mcc users 17K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 157K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 85K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Mar 23 04:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K Mar 23 04:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Mar 22 14:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 22 14:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 6.2M May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-00
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-01
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-02
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-03
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-04
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-05
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-06
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-07
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-08
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-09
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-10
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-11
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-12
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-13
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-14
FORMULA_NAME DLCflexbar-PT-7a-ReachabilityFireability-15

=== Now, execution of the tool begins

BK_START 1620498769196

Running Version 0
[2021-05-08 18:32:50] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityFireability, -spotpath, /home/mcc/BenchKit/bin//..//ltlfilt, -z3path, /home/mcc/BenchKit/bin//..//z3/bin/z3, -yices2path, /home/mcc/BenchKit/bin//..//yices/bin/yices, -its, -ltsmin, -greatspnpath, /home/mcc/BenchKit/bin//..//greatspn/, -order, META, -manyOrder, -smt, -timeout, 3600]
[2021-05-08 18:32:50] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2021-05-08 18:32:51] [INFO ] Load time of PNML (sax parser for PT used): 514 ms
[2021-05-08 18:32:51] [INFO ] Transformed 2913 places.
[2021-05-08 18:32:51] [INFO ] Transformed 23319 transitions.
[2021-05-08 18:32:51] [INFO ] Found NUPN structural information;
[2021-05-08 18:32:51] [INFO ] Parsed PT model containing 2913 places and 23319 transitions in 648 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityFireability.xml in 25 ms.
Working with output stream class java.io.PrintStream
Ensure Unique test removed 2519 transitions
Reduce redundant transitions removed 2519 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 619 ms. (steps per millisecond=16 ) properties (out of 16) seen :13
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-15 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-13 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-07 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-03 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-01 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 327 ms. (steps per millisecond=30 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 301 ms. (steps per millisecond=33 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 316 ms. (steps per millisecond=31 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2021-05-08 18:32:53] [INFO ] Flow matrix only has 1246 transitions (discarded 19554 similar events)
// Phase 1: matrix 1246 rows 2913 cols
[2021-05-08 18:32:53] [INFO ] Computed 2171 place invariants in 33 ms
[2021-05-08 18:32:54] [INFO ] [Real]Absence check using 2171 positive place invariants in 737 ms returned sat
[2021-05-08 18:32:54] [INFO ] SMT Verify possible in real domain returnedunsat :0 sat :0 real:3
[2021-05-08 18:32:56] [INFO ] [Nat]Absence check using 2171 positive place invariants in 723 ms returned sat
[2021-05-08 18:32:56] [INFO ] [Nat]Adding state equation constraints to refine reachable states.
[2021-05-08 18:32:57] [INFO ] [Nat]Absence check using state equation in 1225 ms returned unsat :0 sat :3
[2021-05-08 18:32:57] [INFO ] State equation strengthened by 284 read => feed constraints.
[2021-05-08 18:32:58] [INFO ] [Nat]Added 284 Read/Feed constraints in 99 ms returned sat
Attempting to minimize the solution found.
Minimization took 274 ms.
[2021-05-08 18:32:58] [INFO ] SMT Verify possible in nat domain returned unsat :0 sat :3
Fused 3 Parikh solutions to 2 different solutions.
Incomplete Parikh walk after 75900 steps, including 988 resets, run finished after 9738 ms. (steps per millisecond=7 ) properties (out of 3) seen :2 could not realise parikh vector
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-04 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-00 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Incomplete Parikh walk after 75800 steps, including 989 resets, run finished after 9304 ms. (steps per millisecond=8 ) properties (out of 1) seen :0 could not realise parikh vector
Support contains 15 out of 2913 places. Attempting structural reductions.
Starting structural reductions, iteration 0 : 2913/2913 places, 20800/20800 transitions.
Graph (trivial) has 1090 edges and 2913 vertex of which 244 / 2913 are part of one of the 114 SCC in 14 ms
Free SCC test removed 130 places
Drop transitions removed 12547 transitions
Reduce isomorphic transitions removed 12547 transitions.
Graph (complete) has 10571 edges and 2783 vertex of which 337 are kept as prefixes of interest. Removing 2446 places using SCC suffix rule.14 ms
Discarding 2446 places :
Also discarding 6822 output transitions
Drop transitions removed 6822 transitions
Drop transitions removed 442 transitions
Reduce isomorphic transitions removed 442 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 446 rules applied. Total rules applied 448 place count 337 transition count 985
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 6 rules applied. Total rules applied 454 place count 333 transition count 983
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 455 place count 332 transition count 983
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 455 place count 332 transition count 979
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 463 place count 328 transition count 979
Discarding 281 places :
Symmetric choice reduction at 3 with 281 rule applications. Total rules 744 place count 47 transition count 105
Iterating global reduction 3 with 281 rules applied. Total rules applied 1025 place count 47 transition count 105
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 1029 place count 47 transition count 101
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 4 with 12 rules applied. Total rules applied 1041 place count 41 transition count 95
Drop transitions removed 4 transitions
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 4 with 14 rules applied. Total rules applied 1055 place count 41 transition count 81
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 5 with 21 rules applied. Total rules applied 1076 place count 41 transition count 60
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 5 with 4 rules applied. Total rules applied 1080 place count 37 transition count 60
Discarding 3 places :
Symmetric choice reduction at 6 with 3 rule applications. Total rules 1083 place count 34 transition count 48
Iterating global reduction 6 with 3 rules applied. Total rules applied 1086 place count 34 transition count 48
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 1088 place count 33 transition count 47
Drop transitions removed 7 transitions
Redundant transition composition rules discarded 7 transitions
Iterating global reduction 6 with 7 rules applied. Total rules applied 1095 place count 33 transition count 40
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 1096 place count 32 transition count 40
Free-agglomeration rule applied 1 times.
Iterating global reduction 7 with 1 rules applied. Total rules applied 1097 place count 32 transition count 39
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 1098 place count 31 transition count 39
Applied a total of 1098 rules in 215 ms. Remains 31 /2913 variables (removed 2882) and now considering 39/20800 (removed 20761) transitions.
Finished structural reductions, in 1 iterations. Remains : 31/2913 places, 39/20800 transitions.
[2021-05-08 18:33:18] [INFO ] Flatten gal took : 23 ms
[2021-05-08 18:33:18] [INFO ] Flatten gal took : 17 ms
[2021-05-08 18:33:18] [INFO ] Time to serialize gal into /tmp/ReachabilityCardinality7235384049227156623.gal : 4 ms
[2021-05-08 18:33:18] [INFO ] Time to serialize properties into /tmp/ReachabilityCardinality12767411979117223978.prop : 1 ms
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202104292328/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /tmp/ReachabilityCardinality7235384049227156623.gal, -t, CGAL, -reachable-file, /tmp/ReachabilityCardinality12767411979117223978.prop, --nowitness, --gen-order, FOLLOW], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.202104292328/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /tmp/ReachabilityCardinality7235384049227156623.gal -t CGAL -reachable-file /tmp/ReachabilityCardinality12767411979117223978.prop --nowitness --gen-order FOLLOW
Loading property file /tmp/ReachabilityCardinality12767411979117223978.prop.
SDD proceeding with computation,1 properties remain. new max is 4
SDD size :1 after 9
SDD proceeding with computation,1 properties remain. new max is 8
SDD size :9 after 33
SDD proceeding with computation,1 properties remain. new max is 16
SDD size :33 after 97
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
petri\_inst\_inst,481,0.01532,3916,2,108,8,446,7,0,156,248,0
Total reachable state count : 481

Verifying 1 reachability properties.
Reachability property DLCflexbar-PT-7a-ReachabilityFireability-10 is true.
FORMULA DLCflexbar-PT-7a-ReachabilityFireability-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCflexbar-PT-7a-ReachabilityFireability-10,3,0.016546,4288,2,40,8,446,7,0,180,248,0
All properties solved without resorting to model-checking.

BK_STOP 1620498799186

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/bin//../
+ BINDIR=/home/mcc/BenchKit/bin//../
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityFireability = StateSpace ]]
+ /home/mcc/BenchKit/bin//..//runeclipse.sh /home/mcc/execution ReachabilityFireability -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//..//greatspn/ -order META -manyOrder -smt -timeout 3600
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
++ cut -d . -f 9
++ ls /home/mcc/BenchKit/bin//..//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202104292328.jar
+ VERSION=0
+ echo 'Running Version 0'
+ /home/mcc/BenchKit/bin//..//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityFireability -spotpath /home/mcc/BenchKit/bin//..//ltlfilt -z3path /home/mcc/BenchKit/bin//..//z3/bin/z3 -yices2path /home/mcc/BenchKit/bin//..//yices/bin/yices -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//..//greatspn/ -order META -manyOrder -smt -timeout 3600 -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss128m -Xms40m -Xmx16000m

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-7a"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool itstools"
echo " Input is DLCflexbar-PT-7a, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r064-tall-162038396900247"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-7a.tgz
mv DLCflexbar-PT-7a execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;