About the Execution of LoLA for DLCshifumi-PT-5b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3243.588 | 688262.00 | 980786.00 | 1365.80 | TFFFFFFTFTTTFFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r061-tall-162038393300510.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCshifumi-PT-5b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038393300510
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 11M
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 13K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 108K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Mar 28 15:59 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 15:59 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 15:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 15:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Mar 23 09:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16K Mar 23 09:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Mar 22 16:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 12K Mar 22 16:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 9.7M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-00
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-01
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-02
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-03
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-04
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-05
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-06
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-07
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-08
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-09
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-10
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-11
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-12
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-13
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-14
FORMULA_NAME DLCshifumi-PT-5b-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1620463795524
starting LoLA
BK_INPUT DLCshifumi-PT-5b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-5b-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620464483786
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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DLCshifumi-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-07: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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DLCshifumi-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG 0 0 0 0 0 0 0 0
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DLCshifumi-PT-5b-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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DLCshifumi-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG 0 0 0 0 0 0 0 0
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DLCshifumi-PT-5b-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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DLCshifumi-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
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DLCshifumi-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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DLCshifumi-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
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DLCshifumi-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
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lola: fired transitions : 109
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-81.sara.
sara: place or transition ordering is non-deterministic
lola: CANCELED task # 80 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 81 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 84 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 94 (type EXCL) for 3 DLCshifumi-PT-5b-ReachabilityCardinality-01
lola: time limit : 419 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 96 (type FNDP) for 36 DLCshifumi-PT-5b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 97 (type EQUN) for 36 DLCshifumi-PT-5b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 99 (type SRCH) for 36 DLCshifumi-PT-5b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-04
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: result : false
lola: markings : 16
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 80 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 18628
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 94 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-01
lola: result : true
lola: markings : 48
lola: fired transitions : 69
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 100 (type EXCL) for 36 DLCshifumi-PT-5b-ReachabilityCardinality-12
lola: time limit : 489 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 100 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-12
lola: result : false
lola: markings : 6
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: CANCELED task # 96 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 97 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 99 (type SRCH) for DLCshifumi-PT-5b-ReachabilityCardinality-12 (obsolete)
lola: FINISHED task # 96 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-12
lola: result : unknown
lola: fired transitions : 8071
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-97.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 131 (type EXCL) for 18 DLCshifumi-PT-5b-ReachabilityCardinality-06
lola: time limit : 367 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 119 (type FNDP) for 18 DLCshifumi-PT-5b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type EQUN) for 18 DLCshifumi-PT-5b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 130 (type SRCH) for 18 DLCshifumi-PT-5b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: FINISHED task # 130 (type SRCH) for DLCshifumi-PT-5b-ReachabilityCardinality-06
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: result : true
lola: markings : 2
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 119 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 128 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 131 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-06 (obsolete)
lola: FINISHED task # 81 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-04
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 119 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-06
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-128.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 125 (type EXCL) for 21 DLCshifumi-PT-5b-ReachabilityCardinality-07
lola: time limit : 367 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 104 (type FNDP) for 24 DLCshifumi-PT-5b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type EQUN) for 24 DLCshifumi-PT-5b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type SRCH) for 6 DLCshifumi-PT-5b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 131 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-06
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-5b-ReachabilityCardinality-01: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-04: EF false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-05: AG false findpath
DLCshifumi-PT-5b-ReachabilityCardinality-06: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-09: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG true tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG 0 4 1 0 1 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-03: AG 3 0 0 0 1 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-08: EF 0 3 2 0 1 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-10: EF 2 0 0 0 1 0 0 0
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG 3 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
104 EF FNDP 0/419 0/5 DLCshifumi-PT-5b-ReachabilityCardinality-08 --
108 EF STEQ 0/489 0/5 DLCshifumi-PT-5b-ReachabilityCardinality-08 sara not yet started (preprocessing).
113 EF SRCH 0/489 0/5 DLCshifumi-PT-5b-ReachabilityCardinality-02 --
125 EF EXCL 0/419 0/32 DLCshifumi-PT-5b-ReachabilityCardinality-07 --
Time elapsed: 661 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 125 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-07
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 97 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-12
lola: result : false
lola: LAUNCH task # 139 (type EXCL) for 39 DLCshifumi-PT-5b-ReachabilityCardinality-13
lola: time limit : 489 sec
lola: memory limit: 32 pages
lola: FINISHED task # 128 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-06
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-108.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 113 (type SRCH) for DLCshifumi-PT-5b-ReachabilityCardinality-02
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 107 (type FNDP) for 30 DLCshifumi-PT-5b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 139 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-13
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 1.000000
lola: memory pages used : 1
lola: FINISHED task # 108 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-08
lola: result : false
lola: CANCELED task # 104 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 142 (type EXCL) for 30 DLCshifumi-PT-5b-ReachabilityCardinality-10
lola: time limit : 979 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 111 (type FNDP) for 9 DLCshifumi-PT-5b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 120 (type EQUN) for 9 DLCshifumi-PT-5b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 104 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 19991
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 142 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-10
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 107 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 137 (type EXCL) for 9 DLCshifumi-PT-5b-ReachabilityCardinality-03
lola: time limit : 1469 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 136 (type SRCH) for 9 DLCshifumi-PT-5b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 137 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-03
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 111 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 120 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 136 (type SRCH) for DLCshifumi-PT-5b-ReachabilityCardinality-03 (obsolete)
lola: FINISHED task # 111 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-03
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 107 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-10
lola: result : true
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-120.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 120 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-03
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-5b-ReachabilityCardinality-01: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-03: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-04: EF false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-05: AG false findpath
DLCshifumi-PT-5b-ReachabilityCardinality-06: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-07: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-08: EF false state equation
DLCshifumi-PT-5b-ReachabilityCardinality-09: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-10: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG true tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 666 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-5b-ReachabilityCardinality-01: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-03: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-04: EF false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-05: AG false findpath
DLCshifumi-PT-5b-ReachabilityCardinality-06: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-07: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-08: EF false state equation
DLCshifumi-PT-5b-ReachabilityCardinality-09: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-10: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG true tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 671 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 14.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-5b-ReachabilityCardinality-01: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-03: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-04: EF false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-05: AG false findpath
DLCshifumi-PT-5b-ReachabilityCardinality-06: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-07: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-08: EF false state equation
DLCshifumi-PT-5b-ReachabilityCardinality-09: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-10: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG true tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 676 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-5b-ReachabilityCardinality-01: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-03: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-04: EF false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-05: AG false findpath
DLCshifumi-PT-5b-ReachabilityCardinality-06: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-07: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-08: EF false state equation
DLCshifumi-PT-5b-ReachabilityCardinality-09: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-10: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG true tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 681 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-5b-ReachabilityCardinality-01: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-03: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-04: EF false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-05: AG false findpath
DLCshifumi-PT-5b-ReachabilityCardinality-06: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-07: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-08: EF false state equation
DLCshifumi-PT-5b-ReachabilityCardinality-09: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-10: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG true tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 686 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 149 (type EXCL) for 0 DLCshifumi-PT-5b-ReachabilityCardinality-00
lola: time limit : 2912 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 145 (type FNDP) for 0 DLCshifumi-PT-5b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 146 (type EQUN) for 0 DLCshifumi-PT-5b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 148 (type SRCH) for 0 DLCshifumi-PT-5b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 145 (type FNDP) for DLCshifumi-PT-5b-ReachabilityCardinality-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 146 (type EQUN) for DLCshifumi-PT-5b-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 148 (type SRCH) for DLCshifumi-PT-5b-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 149 (type EXCL) for DLCshifumi-PT-5b-ReachabilityCardinality-00 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-5b-ReachabilityCardinality-00: EF true findpath
DLCshifumi-PT-5b-ReachabilityCardinality-01: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-02: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-03: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-04: EF false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-05: AG false findpath
DLCshifumi-PT-5b-ReachabilityCardinality-06: AG false tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-07: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-08: EF false state equation
DLCshifumi-PT-5b-ReachabilityCardinality-09: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-10: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-11: AG true tandem / insertion
DLCshifumi-PT-5b-ReachabilityCardinality-12: EF false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-13: AG false tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCshifumi-PT-5b-ReachabilityCardinality-15: EF true tandem / relaxed
Time elapsed: 688 secs. Pages in use: 2
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-146.sara.
sara: place or transition ordering is non-deterministic
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-5b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCshifumi-PT-5b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393300510"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-5b.tgz
mv DLCshifumi-PT-5b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;