MCC'2021- Execution of r061-tall-162038393200402

About the Execution of LoLA for DLCround-PT-11a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16245.084	2614829.00	5072835.00	9140.40	F?F?????????TTFT	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.
Waiting for the VM to be
..................................
============
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCround-PT-11a,
Time confinement is 3600
Memory confinement is
Number of cores is 4
Run identifier is r061-tall-16
==================================

--------------------
preparation of the directory
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 11K May
-rw-r--r-- 1 mcc users 106K
-rw-r--r-- 1 mcc users 9.8K May
-rw-r--r-- 1 mcc users 85K
-rw-r--r-- 1 mcc users 4.2K May
-rw-r--r-- 1 mcc users 6.4K May
-rw-r--r-- 1 mcc users 3.3K
-rw-r--r-- 1 mcc users 23K
-rw-r--r-- 1 mcc users 2.0K
-rw-r--r-- 1 mcc users 17K
-rw-r--r-- 1 mcc users 2.6K
-rw-r--r-- 1 mcc users 12K
-rw-r--r-- 1 mcc users 2.7K
-rw-r--r-- 1 mcc users 16K
-rw-r--r-- 1 mcc users 1.6K
-rw-r--r-- 1 mcc users 3.6K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 762K May

--------------------
content from stdout:

=== Data for post analysis

The expected result is a
BOOL_VECTOR

here is the order used to
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi
FORMULA_NAME DLCround-PT-11a-CTLFi

=== Now, execution of the

BK_START 1620750344763

starting LoLA
BK_INPUT DLCround-PT-11a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/
current directory: /home/mcc/execu
CTLFireability

FORMULA DLCround-PT-11a-CTLFireability-12

FORMULA DLCround-PT-11a-CTLFireability-00

FORMULA DLCround-PT-11a-CTLFireability-02

FORMULA DLCround-PT-11a-CTLFireability-14

FORMULA DLCround-PT-11a-CTLFireability-15

FORMULA DLCround-PT-11a-CTLFireability-13

BK_STOP 1620752959592

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file
lola: reading net from
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file /home/mcc/
lola: Reading formula.
lola: Using XML format
lola: reading XML formula
lola: reading formula from
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: RELEASE
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Rule S: 0 transitions
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
FINISHED FORMULA: CATEGORY

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 65 secs.
# running tasks: 0 of 4 Visible:
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
FINISHED FORMULA: CATEGORY

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 70 secs.
# running tasks: 0 of 4 Visible:
lola: Created skeleton
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: LAUNCH task # 39
lola: time limit : 147 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Created skeleton
lola: FINISHED task # 39
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 1 (type
lola: time limit : 185 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 56
lola: time limit : 196 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Created skeleton
lola: LAUNCH task # 51
lola: time limit : 220 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 31
lola: time limit : 235 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 0/251

Time elapsed: 75 secs.
# running tasks: 1 of 4 Visible:
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Created skeleton
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 5/293

Time elapsed: 80 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 10/293

Time elapsed: 85 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 15/293

Time elapsed: 90 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 20/293

Time elapsed: 95 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 25/293

Time elapsed: 100 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 30/293

Time elapsed: 105 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 35/293

Time elapsed: 110 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 40/293

Time elapsed: 115 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 45/293

Time elapsed: 120 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 50/293

Time elapsed: 125 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 55/293

Time elapsed: 130 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 60/293

Time elapsed: 135 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 65/293

Time elapsed: 140 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 70/293

Time elapsed: 145 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 75/293

Time elapsed: 150 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 80/293

Time elapsed: 155 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 85/293

Time elapsed: 160 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 90/293

Time elapsed: 165 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 95/293

Time elapsed: 170 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 100/293

Time elapsed: 175 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 105/293

Time elapsed: 180 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 110/293

Time elapsed: 185 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 115/293

Time elapsed: 190 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 120/293

Time elapsed: 195 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 125/293

Time elapsed: 200 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 130/293

Time elapsed: 205 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 135/293

Time elapsed: 210 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 140/293

Time elapsed: 215 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 145/293

Time elapsed: 220 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 150/293

Time elapsed: 225 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 155/293

Time elapsed: 230 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 160/293

Time elapsed: 235 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 165/293

Time elapsed: 240 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 170/293

Time elapsed: 245 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 175/293

Time elapsed: 250 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 180/293

Time elapsed: 255 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 186/293

Time elapsed: 261 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 191/293

Time elapsed: 266 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 196/293

Time elapsed: 271 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 201/293

Time elapsed: 276 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 206/293

Time elapsed: 281 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 211/293

Time elapsed: 286 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 216/293

Time elapsed: 291 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 221/293

Time elapsed: 296 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 226/293

Time elapsed: 301 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 231/293

Time elapsed: 306 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 236/293

Time elapsed: 311 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 241/293

Time elapsed: 316 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 246/293

Time elapsed: 321 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 251/293

Time elapsed: 326 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 256/293

Time elapsed: 331 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 261/293

Time elapsed: 336 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 266/293

Time elapsed: 341 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 271/293

Time elapsed: 346 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 276/293

Time elapsed: 351 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 281/293

Time elapsed: 356 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 286/293

Time elapsed: 361 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 291/293

Time elapsed: 366 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 31
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 371 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 54
lola: time limit : 293 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 31
lola: time limit : 3229 sec
lola: memory limit: 5 pages
lola: FINISHED task # 54
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 5/293

Time elapsed: 376 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 10/293

Time elapsed: 381 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 15/293

Time elapsed: 386 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 20/293

Time elapsed: 391 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 25/293

Time elapsed: 396 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 30/293

Time elapsed: 401 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 35/293

Time elapsed: 406 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 40/293

Time elapsed: 411 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 45/293

Time elapsed: 416 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 50/293

Time elapsed: 421 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 55/293

Time elapsed: 426 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 60/293

Time elapsed: 431 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 65/293

Time elapsed: 436 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 70/293

Time elapsed: 441 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 75/293

Time elapsed: 446 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 80/293

Time elapsed: 451 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 85/293

Time elapsed: 456 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 90/293

Time elapsed: 461 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 95/293

Time elapsed: 466 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 100/293

Time elapsed: 471 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 105/293

Time elapsed: 476 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 110/293

Time elapsed: 481 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 115/293

Time elapsed: 486 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 120/293

Time elapsed: 491 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 125/293

Time elapsed: 496 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 130/293

Time elapsed: 501 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 135/293

Time elapsed: 506 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 140/293

Time elapsed: 511 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 145/293

Time elapsed: 516 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 150/293

Time elapsed: 521 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 155/293

Time elapsed: 526 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 160/293

Time elapsed: 531 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 165/293

Time elapsed: 536 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 170/293

Time elapsed: 541 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 175/293

Time elapsed: 546 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 180/293

Time elapsed: 551 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 185/293

Time elapsed: 556 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 190/293

Time elapsed: 561 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 195/293

Time elapsed: 566 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 200/293

Time elapsed: 571 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
31 CTL EXCL 205/293

Time elapsed: 576 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 31
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:
DLCround-PT-11a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 581 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 48
lola: time limit : 301 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 34
lola: time limit : 335 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 5/335

Time elapsed: 586 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 10/335

Time elapsed: 591 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 15/335

Time elapsed: 596 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 20/335

Time elapsed: 601 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 25/335

Time elapsed: 606 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 30/335

Time elapsed: 611 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 35/335

Time elapsed: 616 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 40/335

Time elapsed: 621 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 45/335

Time elapsed: 626 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 50/335

Time elapsed: 631 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 55/335

Time elapsed: 636 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 60/335

Time elapsed: 641 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 65/335

Time elapsed: 646 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 70/335

Time elapsed: 651 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 75/335

Time elapsed: 656 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 80/335

Time elapsed: 661 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 85/335

Time elapsed: 666 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 90/335

Time elapsed: 671 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 95/335

Time elapsed: 676 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 100/335

Time elapsed: 681 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 105/335

Time elapsed: 686 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 110/335

Time elapsed: 691 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 115/335

Time elapsed: 696 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 120/335

Time elapsed: 701 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 125/335

Time elapsed: 706 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 130/335

Time elapsed: 711 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 135/335

Time elapsed: 716 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 140/335

Time elapsed: 721 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 145/335

Time elapsed: 726 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 150/335

Time elapsed: 731 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 155/335

Time elapsed: 736 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 160/335

Time elapsed: 741 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 165/335

Time elapsed: 746 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 170/335

Time elapsed: 751 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 175/335

Time elapsed: 756 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 180/335

Time elapsed: 761 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 185/335

Time elapsed: 766 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 190/335

Time elapsed: 771 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 195/335

Time elapsed: 776 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 200/335

Time elapsed: 781 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 205/335

Time elapsed: 786 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 210/335

Time elapsed: 791 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 215/335

Time elapsed: 796 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 220/335

Time elapsed: 801 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 225/335

Time elapsed: 806 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 230/335

Time elapsed: 811 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 235/335

Time elapsed: 816 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 240/335

Time elapsed: 821 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 245/335

Time elapsed: 826 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 250/335

Time elapsed: 831 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 255/335

Time elapsed: 836 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 260/335

Time elapsed: 841 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 265/335

Time elapsed: 846 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 270/335

Time elapsed: 851 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 275/335

Time elapsed: 856 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 280/335

Time elapsed: 861 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 285/335

Time elapsed: 866 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 290/335

Time elapsed: 871 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 295/335

Time elapsed: 876 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 300/335

Time elapsed: 881 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 305/335

Time elapsed: 886 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 310/335

Time elapsed: 891 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 315/335

Time elapsed: 896 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 320/335

Time elapsed: 901 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 325/335

Time elapsed: 906 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 330/335

Time elapsed: 911 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 335/335

Time elapsed: 916 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 34
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 921 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 28
lola: time limit : 334 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 34
lola: time limit : 2679 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 5/334
34 CTL EXCL 5/2679

Time elapsed: 926 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 10/334
34 CTL EXCL 10/297

Time elapsed: 931 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 15/334
34 CTL EXCL 15/297

Time elapsed: 936 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 20/334
34 CTL EXCL 20/297

Time elapsed: 941 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 25/334
34 CTL EXCL 25/297

Time elapsed: 946 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 30/334
34 CTL EXCL 30/297

Time elapsed: 951 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 35/334
34 CTL EXCL 35/297

Time elapsed: 956 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 40/334
34 CTL EXCL 40/297

Time elapsed: 961 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 45/334
34 CTL EXCL 45/297

Time elapsed: 966 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 50/334
34 CTL EXCL 50/297

Time elapsed: 971 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 55/334
34 CTL EXCL 55/297

Time elapsed: 976 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 60/334
34 CTL EXCL 60/297

Time elapsed: 981 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 65/334
34 CTL EXCL 65/297

Time elapsed: 986 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 70/334
34 CTL EXCL 70/297

Time elapsed: 991 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 75/334
34 CTL EXCL 75/297

Time elapsed: 996 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 80/334
34 CTL EXCL 80/297

Time elapsed: 1001 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 85/334
34 CTL EXCL 85/297

Time elapsed: 1006 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 90/334
34 CTL EXCL 90/297

Time elapsed: 1011 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 95/334
34 CTL EXCL 95/297

Time elapsed: 1016 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 100/334
34 CTL EXCL 100/297

Time elapsed: 1021 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 106/334
34 CTL EXCL 106/297

Time elapsed: 1027 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 111/334
34 CTL EXCL 111/297

Time elapsed: 1032 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 116/334
34 CTL EXCL 116/297

Time elapsed: 1037 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 121/334
34 CTL EXCL 121/297

Time elapsed: 1042 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 126/334
34 CTL EXCL 126/297

Time elapsed: 1047 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 131/334
34 CTL EXCL 131/297

Time elapsed: 1052 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 136/334
34 CTL EXCL 136/297

Time elapsed: 1057 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 141/334
34 CTL EXCL 141/297

Time elapsed: 1062 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 146/334
34 CTL EXCL 146/297

Time elapsed: 1067 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 151/334
34 CTL EXCL 151/297

Time elapsed: 1072 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 156/334
34 CTL EXCL 156/297

Time elapsed: 1077 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 161/334
34 CTL EXCL 161/297

Time elapsed: 1082 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 166/334
34 CTL EXCL 166/297

Time elapsed: 1087 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 171/334
34 CTL EXCL 171/297

Time elapsed: 1092 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 176/334
34 CTL EXCL 176/297

Time elapsed: 1097 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 181/334
34 CTL EXCL 181/297

Time elapsed: 1102 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 186/334
34 CTL EXCL 186/297

Time elapsed: 1107 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 191/334
34 CTL EXCL 191/297

Time elapsed: 1112 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 196/334
34 CTL EXCL 196/297

Time elapsed: 1117 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 201/334
34 CTL EXCL 201/297

Time elapsed: 1122 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 206/334
34 CTL EXCL 206/297

Time elapsed: 1127 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 211/334
34 CTL EXCL 211/297

Time elapsed: 1132 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 216/334
34 CTL EXCL 216/297

Time elapsed: 1137 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 221/334
34 CTL EXCL 221/297

Time elapsed: 1142 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 226/334
34 CTL EXCL 226/297

Time elapsed: 1147 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 231/334
34 CTL EXCL 231/297

Time elapsed: 1152 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 236/334
34 CTL EXCL 236/297

Time elapsed: 1157 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 241/334
34 CTL EXCL 241/297

Time elapsed: 1162 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 246/334
34 CTL EXCL 246/297

Time elapsed: 1167 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 251/334
34 CTL EXCL 251/297

Time elapsed: 1172 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 256/334
34 CTL EXCL 256/297

Time elapsed: 1177 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 261/334
34 CTL EXCL 261/297

Time elapsed: 1182 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 266/334
34 CTL EXCL 266/297

Time elapsed: 1187 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 271/334
34 CTL EXCL 271/297

Time elapsed: 1192 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 276/334
34 CTL EXCL 276/297

Time elapsed: 1197 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 281/334
34 CTL EXCL 281/297

Time elapsed: 1202 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 286/334
34 CTL EXCL 286/297

Time elapsed: 1207 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 291/334
34 CTL EXCL 291/297

Time elapsed: 1212 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 296/334
34 CTL EXCL 296/297

Time elapsed: 1217 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 34
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 301/334

Time elapsed: 1222 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 34
lola: time limit : 2378 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 306/334
34 CTL EXCL 5/2378

Time elapsed: 1227 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 311/334
34 CTL EXCL 10/264

Time elapsed: 1232 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 316/334
34 CTL EXCL 15/264

Time elapsed: 1237 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 321/334
34 CTL EXCL 20/264

Time elapsed: 1242 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 326/334
34 CTL EXCL 25/264

Time elapsed: 1247 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 331/334
34 CTL EXCL 30/264

Time elapsed: 1252 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 28
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 35/264

Time elapsed: 1257 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 28
lola: time limit : 2343 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 1/2343
34 CTL EXCL 40/297

Time elapsed: 1262 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 6/2343
34 CTL EXCL 45/264

Time elapsed: 1267 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 11/2343
34 CTL EXCL 50/264

Time elapsed: 1272 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 16/2343
34 CTL EXCL 55/264

Time elapsed: 1277 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 21/2343
34 CTL EXCL 60/264

Time elapsed: 1282 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 26/2343
34 CTL EXCL 65/264

Time elapsed: 1287 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 31/2343
34 CTL EXCL 70/264

Time elapsed: 1292 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 36/2343
34 CTL EXCL 75/264

Time elapsed: 1297 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 41/2343
34 CTL EXCL 80/264

Time elapsed: 1302 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 46/2343
34 CTL EXCL 85/264

Time elapsed: 1307 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 51/2343
34 CTL EXCL 90/264

Time elapsed: 1312 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 56/2343
34 CTL EXCL 95/264

Time elapsed: 1317 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 61/2343
34 CTL EXCL 100/264

Time elapsed: 1322 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 66/2343
34 CTL EXCL 105/264

Time elapsed: 1327 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 71/2343
34 CTL EXCL 110/264

Time elapsed: 1332 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 76/2343
34 CTL EXCL 115/264

Time elapsed: 1337 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 81/2343
34 CTL EXCL 120/264

Time elapsed: 1342 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 86/2343
34 CTL EXCL 125/264

Time elapsed: 1347 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 91/2343
34 CTL EXCL 130/264

Time elapsed: 1352 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 96/2343
34 CTL EXCL 135/264

Time elapsed: 1357 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 101/2343
34 CTL EXCL 140/264

Time elapsed: 1362 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 107/2343
34 CTL EXCL 146/264

Time elapsed: 1368 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 112/2343
34 CTL EXCL 151/264

Time elapsed: 1373 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 117/2343
34 CTL EXCL 156/264

Time elapsed: 1378 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 122/2343
34 CTL EXCL 161/264

Time elapsed: 1383 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 127/2343
34 CTL EXCL 166/264

Time elapsed: 1388 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 132/2343
34 CTL EXCL 171/264

Time elapsed: 1393 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 137/2343
34 CTL EXCL 176/264

Time elapsed: 1398 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 142/2343
34 CTL EXCL 181/264

Time elapsed: 1403 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 147/2343
34 CTL EXCL 186/264

Time elapsed: 1408 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 152/2343
34 CTL EXCL 191/264

Time elapsed: 1413 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 157/2343
34 CTL EXCL 196/264

Time elapsed: 1418 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 162/2343
34 CTL EXCL 201/264

Time elapsed: 1423 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 167/2343
34 CTL EXCL 206/264

Time elapsed: 1428 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 172/2343
34 CTL EXCL 211/264

Time elapsed: 1433 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 177/2343
34 CTL EXCL 216/264

Time elapsed: 1438 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 182/2343
34 CTL EXCL 221/264

Time elapsed: 1443 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 187/2343
34 CTL EXCL 226/264

Time elapsed: 1448 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 192/2343
34 CTL EXCL 231/264

Time elapsed: 1453 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 197/2343
34 CTL EXCL 236/264

Time elapsed: 1458 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 202/2343
34 CTL EXCL 241/264

Time elapsed: 1463 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 207/2343
34 CTL EXCL 246/264

Time elapsed: 1468 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 212/2343
34 CTL EXCL 251/264

Time elapsed: 1473 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 217/2343
34 CTL EXCL 256/264

Time elapsed: 1478 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 222/2343
34 CTL EXCL 261/264

Time elapsed: 1483 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 34
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 227/2343

Time elapsed: 1488 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 34
lola: time limit : 2112 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 232/292
34 CTL EXCL 4/2112

Time elapsed: 1493 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 237/292
34 CTL EXCL 9/234

Time elapsed: 1498 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 242/292
34 CTL EXCL 14/234

Time elapsed: 1503 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 247/292
34 CTL EXCL 19/234

Time elapsed: 1508 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 252/292
34 CTL EXCL 24/234

Time elapsed: 1513 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 257/292
34 CTL EXCL 29/234

Time elapsed: 1518 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 262/292
34 CTL EXCL 34/234

Time elapsed: 1523 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 267/292
34 CTL EXCL 39/234

Time elapsed: 1528 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 272/292
34 CTL EXCL 44/234

Time elapsed: 1533 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 277/292
34 CTL EXCL 49/234

Time elapsed: 1538 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 282/292
34 CTL EXCL 54/234

Time elapsed: 1543 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 287/292
34 CTL EXCL 59/234

Time elapsed: 1548 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 292/292
34 CTL EXCL 64/234

Time elapsed: 1553 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 28
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 69/234

Time elapsed: 1558 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 28
lola: time limit : 2042 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 0/2042
34 CTL EXCL 80/263

Time elapsed: 1569 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 5/2042
34 CTL EXCL 85/234

Time elapsed: 1574 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 10/2042
34 CTL EXCL 90/234

Time elapsed: 1579 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 15/2042
34 CTL EXCL 95/234

Time elapsed: 1584 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 20/2042
34 CTL EXCL 100/234

Time elapsed: 1589 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 25/2042
34 CTL EXCL 105/234

Time elapsed: 1594 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 30/2042
34 CTL EXCL 110/234

Time elapsed: 1599 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 35/2042
34 CTL EXCL 115/234

Time elapsed: 1604 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 40/2042
34 CTL EXCL 120/234

Time elapsed: 1609 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 45/2042
34 CTL EXCL 125/234

Time elapsed: 1614 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 50/2042
34 CTL EXCL 130/234

Time elapsed: 1619 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 55/2042
34 CTL EXCL 135/234

Time elapsed: 1624 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 60/2042
34 CTL EXCL 140/234

Time elapsed: 1629 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 65/2042
34 CTL EXCL 145/234

Time elapsed: 1634 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 70/2042
34 CTL EXCL 150/234

Time elapsed: 1639 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 75/2042
34 CTL EXCL 155/234

Time elapsed: 1644 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 80/2042
34 CTL EXCL 160/234

Time elapsed: 1649 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 85/2042
34 CTL EXCL 165/234

Time elapsed: 1654 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 90/2042
34 CTL EXCL 170/234

Time elapsed: 1659 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 95/2042
34 CTL EXCL 175/234

Time elapsed: 1664 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 100/2042
34 CTL EXCL 180/234

Time elapsed: 1669 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 105/2042
34 CTL EXCL 185/234

Time elapsed: 1674 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 110/2042
34 CTL EXCL 190/234

Time elapsed: 1679 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 115/2042
34 CTL EXCL 195/234

Time elapsed: 1684 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 120/2042
34 CTL EXCL 200/234

Time elapsed: 1689 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 125/2042
34 CTL EXCL 205/234

Time elapsed: 1694 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 130/2042
34 CTL EXCL 210/234

Time elapsed: 1699 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 135/2042
34 CTL EXCL 215/234

Time elapsed: 1704 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 140/2042
34 CTL EXCL 220/234

Time elapsed: 1709 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 145/2042
34 CTL EXCL 225/234

Time elapsed: 1714 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 150/2042
34 CTL EXCL 230/234

Time elapsed: 1719 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 34
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 155/2042

Time elapsed: 1724 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 34
lola: time limit : 1876 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 160/253
34 CTL EXCL 4/1876

Time elapsed: 1729 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 165/253
34 CTL EXCL 9/208

Time elapsed: 1734 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 170/253
34 CTL EXCL 14/208

Time elapsed: 1739 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 175/253
34 CTL EXCL 19/208

Time elapsed: 1744 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 180/253
34 CTL EXCL 24/208

Time elapsed: 1749 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 185/253
34 CTL EXCL 29/208

Time elapsed: 1754 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 190/253
34 CTL EXCL 34/208

Time elapsed: 1759 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 195/253
34 CTL EXCL 39/208

Time elapsed: 1764 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 200/253
34 CTL EXCL 44/208

Time elapsed: 1769 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 205/253
34 CTL EXCL 49/208

Time elapsed: 1774 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 210/253
34 CTL EXCL 54/208

Time elapsed: 1779 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 215/253
34 CTL EXCL 59/208

Time elapsed: 1784 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 220/253
34 CTL EXCL 64/208

Time elapsed: 1789 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 225/253
34 CTL EXCL 69/208

Time elapsed: 1794 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 230/253
34 CTL EXCL 74/208

Time elapsed: 1799 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 235/253
34 CTL EXCL 79/208

Time elapsed: 1804 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 240/253
34 CTL EXCL 84/208

Time elapsed: 1809 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 245/253
34 CTL EXCL 89/208

Time elapsed: 1814 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 250/253
34 CTL EXCL 94/208

Time elapsed: 1819 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 28
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 99/208

Time elapsed: 1824 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 28
lola: time limit : 1776 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 0/1776
34 CTL EXCL 138/234

Time elapsed: 1863 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 5/1776
34 CTL EXCL 143/208

Time elapsed: 1868 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 11/1776
34 CTL EXCL 149/208

Time elapsed: 1874 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 16/1776
34 CTL EXCL 154/208

Time elapsed: 1879 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 21/1776
34 CTL EXCL 159/208

Time elapsed: 1884 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 26/1776
34 CTL EXCL 164/208

Time elapsed: 1889 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 31/1776
34 CTL EXCL 169/208

Time elapsed: 1894 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 36/1776
34 CTL EXCL 174/208

Time elapsed: 1899 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 41/1776
34 CTL EXCL 179/208

Time elapsed: 1904 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 46/1776
34 CTL EXCL 184/208

Time elapsed: 1909 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 51/1776
34 CTL EXCL 189/208

Time elapsed: 1914 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 56/1776
34 CTL EXCL 194/208

Time elapsed: 1919 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 61/1776
34 CTL EXCL 199/208

Time elapsed: 1924 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 66/1776
34 CTL EXCL 204/208

Time elapsed: 1929 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 34
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 71/1776

Time elapsed: 1934 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 34
lola: time limit : 1666 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 85/217
34 CTL EXCL 0/1666

Time elapsed: 1948 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 90/217
34 CTL EXCL 5/183

Time elapsed: 1953 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 95/217
34 CTL EXCL 10/183

Time elapsed: 1958 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 100/217
34 CTL EXCL 15/183

Time elapsed: 1963 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 105/217
34 CTL EXCL 20/183

Time elapsed: 1968 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 110/217
34 CTL EXCL 25/183

Time elapsed: 1973 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 115/217
34 CTL EXCL 30/183

Time elapsed: 1978 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 120/217
34 CTL EXCL 35/183

Time elapsed: 1983 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 125/217
34 CTL EXCL 40/183

Time elapsed: 1988 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 130/217
34 CTL EXCL 45/183

Time elapsed: 1993 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 135/217
34 CTL EXCL 50/183

Time elapsed: 1998 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 140/217
34 CTL EXCL 55/183

Time elapsed: 2003 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 145/217
34 CTL EXCL 60/183

Time elapsed: 2008 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 150/217
34 CTL EXCL 65/183

Time elapsed: 2013 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 155/217
34 CTL EXCL 70/183

Time elapsed: 2018 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 160/217
34 CTL EXCL 75/183

Time elapsed: 2023 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 165/217
34 CTL EXCL 80/183

Time elapsed: 2028 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 170/217
34 CTL EXCL 85/183

Time elapsed: 2033 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 175/217
34 CTL EXCL 90/183

Time elapsed: 2038 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 180/217
34 CTL EXCL 95/183

Time elapsed: 2043 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 185/217
34 CTL EXCL 100/183

Time elapsed: 2048 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 190/217
34 CTL EXCL 105/183

Time elapsed: 2053 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 195/217
34 CTL EXCL 110/183

Time elapsed: 2058 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 200/217
34 CTL EXCL 115/183

Time elapsed: 2063 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 205/217
34 CTL EXCL 120/183

Time elapsed: 2068 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 211/217
34 CTL EXCL 126/183

Time elapsed: 2074 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 216/217
34 CTL EXCL 131/183

Time elapsed: 2079 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 28
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 136/183

Time elapsed: 2084 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 28
lola: time limit : 1516 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 0/1516
34 CTL EXCL 179/206

Time elapsed: 2127 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 34
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 5/1516

Time elapsed: 2132 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 34
lola: time limit : 1468 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 42/184
34 CTL EXCL 0/1468

Time elapsed: 2169 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 47/184
34 CTL EXCL 5/159

Time elapsed: 2174 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 52/184
34 CTL EXCL 10/159

Time elapsed: 2179 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 57/184
34 CTL EXCL 15/159

Time elapsed: 2184 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 62/184
34 CTL EXCL 20/159

Time elapsed: 2189 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 67/184
34 CTL EXCL 25/159

Time elapsed: 2194 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 72/184
34 CTL EXCL 30/159

Time elapsed: 2199 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 77/184
34 CTL EXCL 35/159

Time elapsed: 2204 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 82/184
34 CTL EXCL 40/159

Time elapsed: 2209 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 87/184
34 CTL EXCL 45/159

Time elapsed: 2214 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 92/184
34 CTL EXCL 50/159

Time elapsed: 2219 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 97/184
34 CTL EXCL 55/159

Time elapsed: 2224 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 102/184
34 CTL EXCL 60/159

Time elapsed: 2229 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 107/184
34 CTL EXCL 65/159

Time elapsed: 2234 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 112/184
34 CTL EXCL 70/159

Time elapsed: 2239 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 117/184
34 CTL EXCL 75/159

Time elapsed: 2244 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 122/184
34 CTL EXCL 80/159

Time elapsed: 2249 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 127/184
34 CTL EXCL 85/159

Time elapsed: 2254 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 132/184
34 CTL EXCL 90/159

Time elapsed: 2259 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 137/184
34 CTL EXCL 95/159

Time elapsed: 2264 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 142/184
34 CTL EXCL 100/159

Time elapsed: 2269 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 147/184
34 CTL EXCL 105/159

Time elapsed: 2274 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 152/184
34 CTL EXCL 110/159

Time elapsed: 2279 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 157/184
34 CTL EXCL 115/159

Time elapsed: 2284 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 162/184
34 CTL EXCL 120/159

Time elapsed: 2289 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 168/184
34 CTL EXCL 126/159

Time elapsed: 2295 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 173/184
34 CTL EXCL 131/159

Time elapsed: 2300 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 178/184
34 CTL EXCL 136/159

Time elapsed: 2305 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 183/184
34 CTL EXCL 141/159

Time elapsed: 2310 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 28
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 146/159

Time elapsed: 2315 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 28
lola: time limit : 1285 sec
lola: memory limit: 5 pages
lola: CANCELED task # 34
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 0/1285

Time elapsed: 2435 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 34
lola: time limit : 1165 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 104/145
34 CTL EXCL 0/1165

Time elapsed: 2539 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 109/145
34 CTL EXCL 5/117

Time elapsed: 2544 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 114/145
34 CTL EXCL 10/117

Time elapsed: 2549 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 119/145
34 CTL EXCL 15/117

Time elapsed: 2554 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 124/145
34 CTL EXCL 20/117

Time elapsed: 2559 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 129/145
34 CTL EXCL 25/117

Time elapsed: 2564 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 134/145
34 CTL EXCL 30/117

Time elapsed: 2569 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 139/145
34 CTL EXCL 35/117

Time elapsed: 2574 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
28 CTL EXCL 144/145
34 CTL EXCL 40/117

Time elapsed: 2579 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 28
FINISHED FORMULA: CATEGORY
DLCround-PT-11a-CTLFireability-00:
DLCround-PT-11a-CTLFireability-02: SP ACTL
DLCround-PT-11a-CTLFireability-12:
DLCround-PT-11a-CTLFireability-13:
DLCround-PT-11a-CTLFireability-14:
DLCround-PT-11a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-11a-CTLFireability-01:
DLCround-PT-11a-CTLFireability-03:
DLCround-PT-11a-CTLFireability-04:
DLCround-PT-11a-CTLFireability-05:
DLCround-PT-11a-CTLFireability-06:
DLCround-PT-11a-CTLFireability-07:
DLCround-PT-11a-CTLFireability-08:
DLCround-PT-11a-CTLFireability-09:
DLCround-PT-11a-CTLFireability-10:
DLCround-PT-11a-CTLFireability-11:

TASK CATEGORY TYPE TIME/TLIMIT
34 CTL EXCL 45/117

Time elapsed: 2584 secs.
# running tasks: 2 of 4 Visible:
/home/mcc/BenchKit/BenchKit_head.sh: line 62:
r061-tall-162038393200402.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off ready (probing ssh) ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... ========================================================= examination is CTLFireability seconds 16384 MBytes 2038393200402 =================================== to be used: 5 16:58 CTLCardinality.txt May 10 09:42 CTLCardinality.xml 5 16:58 CTLFireability.txt May 10 09:42 CTLFireability.xml 6 14:48 GenericPropertiesDefinition.xml 6 14:48 GenericPropertiesVerdict.xml Mar 28 15:58 LTLCardinality.txt Mar 28 15:58 LTLCardinality.xml Mar 28 15:58 LTLFireability.txt Mar 28 15:58 LTLFireability.xml Mar 23 08:36 ReachabilityCardinality.txt Mar 23 08:36 ReachabilityCardinality.xml Mar 22 16:09 ReachabilityFireability.txt Mar 22 16:09 ReachabilityFireability.xml Mar 22 09:10 UpperBounds.txt Mar 22 09:10 UpperBounds.xml 6 May 5 16:51 equiv_col 4 May 5 16:51 instance 6 May 5 16:51 iscolored 5 16:51 model.pnml generated by BenchKit (invocation template) vector of booleans build the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 tool begins bin tion TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT (--pnmlnet) /home/mcc/execution/model.pnml place/transition net execution/model.pnml (--xmlformula) /home/mcc/execution/CTLFireability.xml rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:550 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:314 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:472 rmula_rewrite.k:250 rmula_rewrite.k:478 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:299 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:250 rmula_rewrite.k:397 rmula_rewrite.k:250 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:457 rmula_rewrite.k:394 rmula_rewrite.k:475 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:547 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:388 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:250 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:317 rmula_rewrite.k:299 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:391 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:250 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:314 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:317 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:325 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 removed,0 places removed in 0.000000 secs. in 1.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 1.000000 secs. in 2.000000 secs. VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 16 in 3.000000 secs. in 2.000000 secs. in 0.000000 secs. in 1.000000 secs. VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 16 in 0.000000 secs. in 0.000000 secs. rmula_rewrite.k:809 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:811 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:810 rmula_rewrite.k:811 rmula_rewrite.k:810 rmula_rewrite.k:814 rmula_rewrite.k:813 (type EXCL) for 36 DLCround-PT-11a-CTLFireability-12 rmula_rewrite.k:814 rmula_rewrite.k:813 rmula_rewrite.k:811 rmula_rewrite.k:679 rmula_rewrite.k:679 rmula_rewrite.k:679 rmula_rewrite.k:679 in 0.000000 secs. (type EXCL) for DLCround-PT-11a-CTLFireability-12 : true 504 24608 0.000000 1 EXCL) for 0 DLCround-PT-11a-CTLFireability-00 (type EXCL) for DLCround-PT-11a-CTLFireability-00 : false 35 320 0.000000 1 (type EXCL) for 6 DLCround-PT-11a-CTLFireability-02 (type EXCL) for DLCround-PT-11a-CTLFireability-02 : false 38 320 0.000000 1 in 0.000000 secs. rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:808 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:814 rmula_rewrite.k:814 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:807 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:809 rmula_rewrite.k:812 rmula_rewrite.k:814 rmula_rewrite.k:813 rmula_rewrite.k:809 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:811 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:813 in 3.000000 secs. (type EXCL) for 50 DLCround-PT-11a-CTLFireability-14 (type EXCL) for DLCround-PT-11a-CTLFireability-14 : false 1 1 0.000000 1 (type EXCL) for 30 DLCround-PT-11a-CTLFireability-10 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:814 rmula_rewrite.k:811 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-10 1736 m, 347 m/sec, 28123 t fired, . Pages in use: 1 16 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:812 rmula_rewrite.k:809 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:813 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:813 in 0.000000 secs. in 0.000000 secs. rmula_rewrite.k:811 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:807 rmula_rewrite.k:808 rmula_rewrite.k:812 rmula_rewrite.k:815 rmula_rewrite.k:812 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:813 rmula_rewrite.k:812 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-10 53797 m, 10412 m/sec, 926527 t fired, . Pages in use: 1 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-10 108322 m, 10905 m/sec, 1855447 t fired, . Pages in use: 1 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-10 167633 m, 11862 m/sec, 2865042 t fired, . Pages in use: 1 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-10 217129 m, 9899 m/sec, 3706521 t fired, . Pages in use: 1 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-10 283925 m, 13359 m/sec, 4822606 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-10 340352 m, 11285 m/sec, 5894020 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-10 374964 m, 6922 m/sec, 7061926 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-10 403432 m, 5693 m/sec, 8052579 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-10 436336 m, 6580 m/sec, 9187148 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-10 461853 m, 5103 m/sec, 10081588 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 488698 m, 5369 m/sec, 11009092 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 519222 m, 6104 m/sec, 12071345 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 544553 m, 5066 m/sec, 12943364 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 567886 m, 4666 m/sec, 13737042 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 590637 m, 4550 m/sec, 14525385 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 608578 m, 3588 m/sec, 15168674 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 629509 m, 4186 m/sec, 15915353 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 649772 m, 4052 m/sec, 16652208 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 680060 m, 6057 m/sec, 17743612 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-10 707083 m, 5404 m/sec, 18695479 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 729214 m, 4426 m/sec, 19476559 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 751313 m, 4419 m/sec, 20264414 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 773137 m, 4364 m/sec, 21041982 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 802056 m, 5783 m/sec, 22054796 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 830042 m, 5597 m/sec, 23049929 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 850818 m, 4155 m/sec, 23788649 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 873525 m, 4541 m/sec, 24608763 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 903111 m, 5917 m/sec, 25672152 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 919720 m, 3321 m/sec, 26264350 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-10 948347 m, 5725 m/sec, 27290544 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 969264 m, 4183 m/sec, 28040876 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 990818 m, 4310 m/sec, 28815680 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 1018565 m, 5549 m/sec, 29818767 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 1043370 m, 4961 m/sec, 30718140 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 1066841 m, 4694 m/sec, 31557790 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 1092949 m, 5221 m/sec, 32452752 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 1119635 m, 5337 m/sec, 33377367 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 1142335 m, 4540 m/sec, 34147649 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 1172354 m, 6003 m/sec, 35150201 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-10 1193905 m, 4310 m/sec, 35865629 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1216542 m, 4527 m/sec, 36627134 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1244736 m, 5638 m/sec, 37618112 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1267437 m, 4540 m/sec, 38415174 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1295935 m, 5699 m/sec, 39407950 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1321594 m, 5131 m/sec, 40327043 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1349640 m, 5609 m/sec, 41342298 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1371776 m, 4427 m/sec, 42141310 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1403070 m, 6258 m/sec, 43261741 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-10 1429858 m, 5357 m/sec, 44237703 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1452804 m, 4589 m/sec, 45047442 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1475462 m, 4531 m/sec, 45870319 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1498322 m, 4572 m/sec, 46696548 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1529362 m, 6208 m/sec, 47794154 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1552611 m, 4649 m/sec, 48622154 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1576451 m, 4768 m/sec, 49471373 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1606500 m, 6009 m/sec, 50558737 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1634987 m, 5697 m/sec, 51585284 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-10 1656311 m, 4264 m/sec, 52352130 t fired, . Pages in use: 7 16 (type EXCL) for DLCround-PT-11a-CTLFireability-10 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 7 16 (type EXCL) for 53 DLCround-PT-11a-CTLFireability-15 (type EXCL) for 30 DLCround-PT-11a-CTLFireability-10 (type EXCL) for DLCround-PT-11a-CTLFireability-15 : true 18 78 0.000000 1 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-10 44665 m, -322329 m/sec, 768577 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-10 84520 m, 7971 m/sec, 1457671 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-10 138733 m, 10842 m/sec, 2381916 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-10 209731 m, 14199 m/sec, 3584761 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 262681 m, 10590 m/sec, 4481933 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 316726 m, 10809 m/sec, 5364641 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 350986 m, 6852 m/sec, 6249141 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 371982 m, 4199 m/sec, 6962012 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 391614 m, 3926 m/sec, 7643363 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 418727 m, 5422 m/sec, 8585567 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 441709 m, 4596 m/sec, 9367430 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 460693 m, 3796 m/sec, 10042168 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-10 481773 m, 4216 m/sec, 10769740 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 501915 m, 4028 m/sec, 11468745 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 524099 m, 4436 m/sec, 12240086 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 546445 m, 4469 m/sec, 13005205 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 569558 m, 4622 m/sec, 13795978 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 590400 m, 4168 m/sec, 14516353 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 615118 m, 4943 m/sec, 15405995 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 642482 m, 5472 m/sec, 16386053 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 669000 m, 5303 m/sec, 17348841 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-10 696195 m, 5439 m/sec, 18302753 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 723653 m, 5491 m/sec, 19281981 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 744800 m, 4229 m/sec, 20033995 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 763543 m, 3748 m/sec, 20696148 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 789937 m, 5278 m/sec, 21627499 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 811006 m, 4213 m/sec, 22368437 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 838722 m, 5543 m/sec, 23361332 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 866355 m, 5526 m/sec, 24346991 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 892255 m, 5180 m/sec, 25285406 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 929450 m, 7439 m/sec, 26610407 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-10 953545 m, 4819 m/sec, 27477813 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 978216 m, 4934 m/sec, 28359583 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 1009377 m, 6232 m/sec, 29481284 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 1036158 m, 5356 m/sec, 30455050 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 1058293 m, 4427 m/sec, 31252622 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 1078730 m, 4087 m/sec, 31959868 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 1113628 m, 6979 m/sec, 33174912 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 1142998 m, 5874 m/sec, 34170072 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 1170716 m, 5543 m/sec, 35094394 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-10 1188979 m, 3652 m/sec, 35702186 t fired, . Pages in use: 7 16 (type EXCL) for DLCround-PT-11a-CTLFireability-10 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 7 16 (type EXCL) for 47 DLCround-PT-11a-CTLFireability-13 (type EXCL) for DLCround-PT-11a-CTLFireability-13 : true 4 6 0.000000 1 (type EXCL) for 33 DLCround-PT-11a-CTLFireability-11 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 24814 m, 4962 m/sec, 984325 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 44802 m, 3997 m/sec, 1801279 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 61683 m, 3376 m/sec, 2482961 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 81348 m, 3933 m/sec, 3322776 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 101475 m, 4025 m/sec, 4171342 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 122888 m, 4282 m/sec, 5007440 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 152516 m, 5925 m/sec, 6170950 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 172287 m, 3954 m/sec, 6950489 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 195443 m, 4631 m/sec, 7839477 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-11 222781 m, 5467 m/sec, 8933607 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 244888 m, 4421 m/sec, 9847302 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 274584 m, 5939 m/sec, 10950673 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 290270 m, 3137 m/sec, 11605743 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 313234 m, 4592 m/sec, 12542021 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 343121 m, 5977 m/sec, 13671798 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 369418 m, 5259 m/sec, 14570183 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 388406 m, 3797 m/sec, 15204628 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 407705 m, 3859 m/sec, 15894035 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 427852 m, 4029 m/sec, 16600090 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 453727 m, 5175 m/sec, 17518047 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-11 474470 m, 4148 m/sec, 18240049 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 493659 m, 3837 m/sec, 18945823 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 522159 m, 5700 m/sec, 19932510 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 541640 m, 3896 m/sec, 20634614 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 563310 m, 4334 m/sec, 21411849 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 588107 m, 4959 m/sec, 22318412 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 618590 m, 6096 m/sec, 23343147 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 639638 m, 4209 m/sec, 24071939 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 664188 m, 4910 m/sec, 24968945 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 692013 m, 5565 m/sec, 25956943 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-11 718001 m, 5197 m/sec, 26851299 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 746547 m, 5709 m/sec, 27859708 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 766608 m, 4012 m/sec, 28586132 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 792362 m, 5150 m/sec, 29508414 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 811182 m, 3764 m/sec, 30202251 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 834719 m, 4707 m/sec, 31019742 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 866140 m, 6284 m/sec, 32132220 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 891221 m, 5016 m/sec, 33021285 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 909344 m, 3624 m/sec, 33656201 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-11 943954 m, 6922 m/sec, 34888464 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 964547 m, 4118 m/sec, 35630106 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 982936 m, 3677 m/sec, 36252299 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1007556 m, 4924 m/sec, 37124156 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1033796 m, 5248 m/sec, 38064581 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1058569 m, 4954 m/sec, 38941454 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1084439 m, 5174 m/sec, 39908784 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1106285 m, 4369 m/sec, 40694688 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1127944 m, 4331 m/sec, 41486135 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1145873 m, 3585 m/sec, 42155899 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1157926 m, 2410 m/sec, 42594260 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-11 1177905 m, 3995 m/sec, 43332723 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1203576 m, 5134 m/sec, 44268213 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1222653 m, 3815 m/sec, 44949688 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1251092 m, 5687 m/sec, 45954899 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1274939 m, 4769 m/sec, 46846375 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1301844 m, 5381 m/sec, 47798212 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1323416 m, 4314 m/sec, 48588238 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1343891 m, 4095 m/sec, 49322283 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1371459 m, 5513 m/sec, 50334377 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1392836 m, 4275 m/sec, 51116441 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-11 1416690 m, 4770 m/sec, 51999772 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-11 1440155 m, 4693 m/sec, 52865498 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-11 1459271 m, 3823 m/sec, 53573124 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-11 1476762 m, 3498 m/sec, 54186277 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-11 1498452 m, 4338 m/sec, 54897398 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-11 1513715 m, 3052 m/sec, 55437833 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-11 1532944 m, 3845 m/sec, 56160696 t fired, . Pages in use: 7 16 (type EXCL) for DLCround-PT-11a-CTLFireability-11 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 7 16 (type EXCL) for 27 DLCround-PT-11a-CTLFireability-09 (type EXCL) for 33 DLCround-PT-11a-CTLFireability-11 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-09 30820 m, 6164 m/sec, 478268 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 18901 m, -302808 m/sec, 738458 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-09 64046 m, 6645 m/sec, 1041939 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 38740 m, 3967 m/sec, 1538691 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-09 98164 m, 6823 m/sec, 1566445 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 55569 m, 3365 m/sec, 2245616 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-09 130343 m, 6435 m/sec, 2094457 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 74963 m, 3878 m/sec, 3051318 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-09 160244 m, 5980 m/sec, 2608182 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 93269 m, 3661 m/sec, 3810902 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-09 182257 m, 4402 m/sec, 3016292 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 108221 m, 2990 m/sec, 4448640 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-09 210182 m, 5585 m/sec, 3518231 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 130105 m, 4376 m/sec, 5292009 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-11a-CTLFireability-09 231466 m, 4256 m/sec, 3918530 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 149167 m, 3812 m/sec, 6036102 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 255660 m, 4838 m/sec, 4375443 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 166963 m, 3559 m/sec, 6757069 t fired, . Pages in use: 11 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 276593 m, 4186 m/sec, 4737532 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 183719 m, 3351 m/sec, 7396127 t fired, . Pages in use: 11 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 306042 m, 5889 m/sec, 5196835 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 205093 m, 4274 m/sec, 8225234 t fired, . Pages in use: 11 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 331484 m, 5088 m/sec, 5662456 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 225880 m, 4157 m/sec, 9061417 t fired, . Pages in use: 11 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 363082 m, 6319 m/sec, 6185381 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 247206 m, 4265 m/sec, 9945422 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 386984 m, 4780 m/sec, 6622120 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 269988 m, 4556 m/sec, 10779922 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 406670 m, 3937 m/sec, 6994948 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 285912 m, 3184 m/sec, 11425029 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 431721 m, 5010 m/sec, 7475148 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 307675 m, 4352 m/sec, 12300685 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 451778 m, 4011 m/sec, 7873388 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 326473 m, 3759 m/sec, 13028824 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-11a-CTLFireability-09 473962 m, 4436 m/sec, 8265673 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 346826 m, 4070 m/sec, 13794455 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 496054 m, 4418 m/sec, 8694719 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 367757 m, 4186 m/sec, 14509734 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 517825 m, 4354 m/sec, 9107943 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 389417 m, 4332 m/sec, 15242298 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 547020 m, 5839 m/sec, 9643731 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 412958 m, 4708 m/sec, 16094487 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 570218 m, 4639 m/sec, 10009415 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 432797 m, 3967 m/sec, 16781231 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 590734 m, 4103 m/sec, 10389207 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 451245 m, 3689 m/sec, 17431245 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 614993 m, 4851 m/sec, 10848516 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 469751 m, 3701 m/sec, 18081902 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 642980 m, 5597 m/sec, 11296297 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 490836 m, 4217 m/sec, 18839374 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 667994 m, 5002 m/sec, 11703049 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 510763 m, 3985 m/sec, 19538808 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 690158 m, 4432 m/sec, 12150563 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 531898 m, 4227 m/sec, 20288087 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-11a-CTLFireability-09 710932 m, 4154 m/sec, 12563918 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 551315 m, 3883 m/sec, 20980910 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 730424 m, 3898 m/sec, 12941654 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 569984 m, 3733 m/sec, 21660972 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 743957 m, 2706 m/sec, 13224565 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 584471 m, 2897 m/sec, 22183361 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 768051 m, 4818 m/sec, 13660611 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 607187 m, 4543 m/sec, 22970467 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 789365 m, 4262 m/sec, 14055968 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 626612 m, 3885 m/sec, 23613675 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 807612 m, 3649 m/sec, 14403921 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 643228 m, 3323 m/sec, 24204930 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 823774 m, 3232 m/sec, 14715736 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 657776 m, 2909 m/sec, 24745523 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 847092 m, 4663 m/sec, 15120096 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 678683 m, 4181 m/sec, 25476603 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 872770 m, 5135 m/sec, 15547722 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 698178 m, 3899 m/sec, 26186122 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 894511 m, 4348 m/sec, 15884928 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 715786 m, 3521 m/sec, 26772145 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 915600 m, 4217 m/sec, 16305259 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 736472 m, 4137 m/sec, 27505908 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-11a-CTLFireability-09 934543 m, 3788 m/sec, 16689959 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 754308 m, 3567 m/sec, 28142967 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 960718 m, 5235 m/sec, 17221194 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 779604 m, 5059 m/sec, 29046798 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 984408 m, 4738 m/sec, 17681408 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 798350 m, 3749 m/sec, 29727754 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 1007519 m, 4622 m/sec, 18126013 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 820163 m, 4362 m/sec, 30513807 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 1035936 m, 5683 m/sec, 18667263 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 845365 m, 5040 m/sec, 31417228 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 1060161 m, 4845 m/sec, 19137923 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 868853 m, 4697 m/sec, 32224278 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 1088107 m, 5589 m/sec, 19585043 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 889591 m, 4147 m/sec, 32967565 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 1115094 m, 5397 m/sec, 19986045 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 905834 m, 3248 m/sec, 33530453 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 1137925 m, 4566 m/sec, 20317389 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 920262 m, 2885 m/sec, 34040789 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 1165498 m, 5514 m/sec, 20752305 t fired, . 4/5 DLCround-PT-11a-CTLFireability-11 940301 m, 4007 m/sec, 34748689 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-11a-CTLFireability-09 1191423 m, 5185 m/sec, 21146486 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 960194 m, 3978 m/sec, 35481861 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1214264 m, 4568 m/sec, 21489604 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 977699 m, 3501 m/sec, 36081236 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1239720 m, 5091 m/sec, 21858512 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 997445 m, 3949 m/sec, 36762527 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1269333 m, 5922 m/sec, 22227567 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 1017395 m, 3990 m/sec, 37461495 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1303535 m, 6840 m/sec, 22721619 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 1042312 m, 4983 m/sec, 38357324 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1328406 m, 4974 m/sec, 23072908 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 1060547 m, 3647 m/sec, 39007328 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1353243 m, 4967 m/sec, 23454486 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 1079001 m, 3690 m/sec, 39706103 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1374164 m, 4184 m/sec, 23769713 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 1093129 m, 2825 m/sec, 40224977 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1399150 m, 4997 m/sec, 24180040 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 1111438 m, 3661 m/sec, 40875462 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-11a-CTLFireability-09 1420183 m, 4206 m/sec, 24516341 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 1126400 m, 2992 m/sec, 41425863 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-09 1456277 m, 7218 m/sec, 25063452 t fired, . 5/5 DLCround-PT-11a-CTLFireability-11 1150022 m, 4724 m/sec, 42302339 t fired, . Pages in use: 24 16 (type EXCL) for DLCround-PT-11a-CTLFireability-11 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-09 1491722 m, 7089 m/sec, 25522796 t fired, . Pages in use: 24 16 (type EXCL) for 33 DLCround-PT-11a-CTLFireability-11 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-09 1525836 m, 6822 m/sec, 25958760 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 16771 m, -226650 m/sec, 651359 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-09 1549831 m, 4799 m/sec, 26297461 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 30195 m, 2684 m/sec, 1193788 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-09 1571076 m, 4249 m/sec, 26594751 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 41201 m, 2201 m/sec, 1645823 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-09 1600088 m, 5802 m/sec, 27029463 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 56386 m, 3037 m/sec, 2280394 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-09 1619734 m, 3929 m/sec, 27290959 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 66561 m, 2035 m/sec, 2695692 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-11a-CTLFireability-09 1644959 m, 5045 m/sec, 27678579 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 81297 m, 2947 m/sec, 3320747 t fired, . Pages in use: 27 16 (type EXCL) for DLCround-PT-11a-CTLFireability-09 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-11 94957 m, 2732 m/sec, 3889853 t fired, . Pages in use: 27 16 (type EXCL) for 27 DLCround-PT-11a-CTLFireability-09 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 6321 m, -327727 m/sec, 89658 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 103749 m, 1758 m/sec, 4271931 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 27467 m, 4229 m/sec, 423983 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 115012 m, 2252 m/sec, 4714031 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 45201 m, 3546 m/sec, 717706 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 124289 m, 1855 m/sec, 5058178 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 60240 m, 3007 m/sec, 980090 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 136217 m, 2385 m/sec, 5551259 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 79583 m, 3868 m/sec, 1286519 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 149093 m, 2575 m/sec, 6033263 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 96311 m, 3345 m/sec, 1540405 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 156267 m, 1434 m/sec, 6323328 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 115123 m, 3762 m/sec, 1863962 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 166162 m, 1979 m/sec, 6730638 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 141221 m, 5219 m/sec, 2280736 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 180869 m, 2941 m/sec, 7283873 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 163486 m, 4453 m/sec, 2670252 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 191528 m, 2131 m/sec, 7685765 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 182908 m, 3884 m/sec, 3030257 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 203443 m, 2383 m/sec, 8158606 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 201506 m, 3719 m/sec, 3354441 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 215008 m, 2313 m/sec, 8614529 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 219109 m, 3520 m/sec, 3684277 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 225201 m, 2038 m/sec, 9032189 t fired, . Pages in use: 30 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 237868 m, 3751 m/sec, 4030616 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 235168 m, 1993 m/sec, 9441365 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 255217 m, 3469 m/sec, 4368410 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 248651 m, 2696 m/sec, 10001776 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 275840 m, 4124 m/sec, 4723375 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 262102 m, 2690 m/sec, 10473227 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 296121 m, 4056 m/sec, 5035912 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 274921 m, 2563 m/sec, 10964112 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 316535 m, 4082 m/sec, 5383887 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 284074 m, 1830 m/sec, 11344207 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 335677 m, 3828 m/sec, 5728373 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 293067 m, 1798 m/sec, 11727211 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 353350 m, 3534 m/sec, 6044439 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 307425 m, 2871 m/sec, 12289466 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 374602 m, 4250 m/sec, 6396822 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 324070 m, 3329 m/sec, 12936561 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 393355 m, 3750 m/sec, 6728849 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 333656 m, 1917 m/sec, 13306863 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 410110 m, 3351 m/sec, 7060973 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 343309 m, 1930 m/sec, 13678252 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 432910 m, 4560 m/sec, 7500361 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 357980 m, 2934 m/sec, 14189070 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 450104 m, 3438 m/sec, 7845537 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 368970 m, 2198 m/sec, 14552943 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 471058 m, 4190 m/sec, 8206636 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 383101 m, 2826 m/sec, 15032977 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 490212 m, 3830 m/sec, 8575652 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 395270 m, 2433 m/sec, 15454955 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 506089 m, 3175 m/sec, 8896111 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 407221 m, 2390 m/sec, 15877501 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 527652 m, 4312 m/sec, 9296590 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 419520 m, 2459 m/sec, 16324903 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 551312 m, 4732 m/sec, 9712345 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 434939 m, 3083 m/sec, 16849489 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 570482 m, 3834 m/sec, 10014272 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 445313 m, 2074 m/sec, 17224695 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 590974 m, 4098 m/sec, 10393934 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 457571 m, 2451 m/sec, 17654338 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 607130 m, 3231 m/sec, 10697648 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 468008 m, 2087 m/sec, 18025819 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 620483 m, 2670 m/sec, 10940918 t fired, . 2/5 DLCround-PT-11a-CTLFireability-11 477115 m, 1821 m/sec, 18338602 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 642567 m, 4416 m/sec, 11290455 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 488241 m, 2225 m/sec, 18740998 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 664458 m, 4378 m/sec, 11631317 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 502727 m, 2897 m/sec, 19261236 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 683394 m, 3787 m/sec, 11992827 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 516454 m, 2745 m/sec, 19739115 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 700035 m, 3328 m/sec, 12349247 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 525190 m, 1747 m/sec, 20046056 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 716279 m, 3248 m/sec, 12673565 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 537225 m, 2407 m/sec, 20476905 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 732301 m, 3204 m/sec, 12978328 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 551172 m, 2789 m/sec, 20975114 t fired, . Pages in use: 40 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 745126 m, 2565 m/sec, 13250686 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 564973 m, 2760 m/sec, 21476611 t fired, . Pages in use: 41 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 762247 m, 3424 m/sec, 13556198 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 579289 m, 2863 m/sec, 21997943 t fired, . Pages in use: 41 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 777492 m, 3049 m/sec, 13826316 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 589553 m, 2052 m/sec, 22368899 t fired, . Pages in use: 41 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 791921 m, 2885 m/sec, 14109402 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 597220 m, 1533 m/sec, 22644579 t fired, . Pages in use: 41 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 810170 m, 3649 m/sec, 14451981 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 613664 m, 3288 m/sec, 23182190 t fired, . Pages in use: 42 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 825803 m, 3126 m/sec, 14760297 t fired, . 3/5 DLCround-PT-11a-CTLFireability-11 625769 m, 2421 m/sec, 23584163 t fired, . Pages in use: 42 16 (type EXCL) for DLCround-PT-11a-CTLFireability-11 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 842441 m, 3327 m/sec, 15047129 t fired, . Pages in use: 42 16 (type EXCL) for 33 DLCround-PT-11a-CTLFireability-11 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 859951 m, 3502 m/sec, 15349782 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 5269 m, -124100 m/sec, 203847 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 875638 m, 3137 m/sec, 15589145 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 13757 m, 1697 m/sec, 526435 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 892907 m, 3453 m/sec, 15853881 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 22845 m, 1817 m/sec, 902821 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 904318 m, 2282 m/sec, 16082794 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 27658 m, 962 m/sec, 1091793 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 915972 m, 2330 m/sec, 16312650 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 35269 m, 1522 m/sec, 1390776 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 927811 m, 2367 m/sec, 16559953 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 40111 m, 968 m/sec, 1598157 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 940860 m, 2609 m/sec, 16820268 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 43487 m, 675 m/sec, 1743695 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-11a-CTLFireability-09 950860 m, 2000 m/sec, 17032497 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 47696 m, 841 m/sec, 1925933 t fired, . Pages in use: 45 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-09 963869 m, 2601 m/sec, 17285518 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 52572 m, 975 m/sec, 2125734 t fired, . Pages in use: 46 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-09 977880 m, 2802 m/sec, 17555367 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 61756 m, 1836 m/sec, 2485792 t fired, . Pages in use: 46 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-09 991620 m, 2748 m/sec, 17816914 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 67296 m, 1108 m/sec, 2730425 t fired, . Pages in use: 46 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-09 1007751 m, 3226 m/sec, 18130891 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 75537 m, 1648 m/sec, 3074844 t fired, . Pages in use: 46 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-11a-CTLFireability-09 1020795 m, 2608 m/sec, 18371792 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 80878 m, 1068 m/sec, 3305943 t fired, . Pages in use: 46 16 (type EXCL) for DLCround-PT-11a-CTLFireability-09 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-11 86762 m, 1176 m/sec, 3525530 t fired, . Pages in use: 46 16 (type EXCL) for 27 DLCround-PT-11a-CTLFireability-09 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 96 m, -204139 m/sec, 1401 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 97379 m, 2123 m/sec, 3996695 t fired, . Pages in use: 49 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 13872 m, 2755 m/sec, 207148 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 102040 m, 932 m/sec, 4198052 t fired, . Pages in use: 49 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 29680 m, 3161 m/sec, 458690 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 104348 m, 461 m/sec, 4300213 t fired, . Pages in use: 49 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 45429 m, 3149 m/sec, 721229 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 108278 m, 786 m/sec, 4450533 t fired, . Pages in use: 49 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 61963 m, 3306 m/sec, 1009482 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 112805 m, 905 m/sec, 4625258 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 81018 m, 3811 m/sec, 1309358 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 118502 m, 1139 m/sec, 4849532 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 98733 m, 3543 m/sec, 1581947 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 124403 m, 1180 m/sec, 5063164 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 116128 m, 3479 m/sec, 1879169 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 131621 m, 1443 m/sec, 5354442 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 132208 m, 3216 m/sec, 2130300 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 135789 m, 833 m/sec, 5531368 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 147543 m, 3067 m/sec, 2387769 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 142751 m, 1392 m/sec, 5790504 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 160433 m, 2578 m/sec, 2615024 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 145360 m, 521 m/sec, 5887660 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 173774 m, 2668 m/sec, 2856058 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 148213 m, 570 m/sec, 5998378 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 188168 m, 2878 m/sec, 3116345 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 152053 m, 768 m/sec, 6153335 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 199200 m, 2206 m/sec, 3311386 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 157701 m, 1129 m/sec, 6384073 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 211344 m, 2428 m/sec, 3540826 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 160732 m, 606 m/sec, 6511323 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 221439 m, 2019 m/sec, 3728472 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 163416 m, 536 m/sec, 6620070 t fired, . Pages in use: 51 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 229859 m, 1684 m/sec, 3894371 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 167471 m, 811 m/sec, 6774277 t fired, . Pages in use: 51 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 240189 m, 2066 m/sec, 4075234 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 171000 m, 705 m/sec, 6903093 t fired, . Pages in use: 52 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 251909 m, 2344 m/sec, 4292234 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 176209 m, 1041 m/sec, 7105698 t fired, . Pages in use: 53 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 262343 m, 2086 m/sec, 4501544 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 181192 m, 996 m/sec, 7296356 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 277842 m, 3099 m/sec, 4758652 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 187633 m, 1288 m/sec, 7549902 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 296451 m, 3721 m/sec, 5041698 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 194887 m, 1450 m/sec, 7817658 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 311370 m, 2983 m/sec, 5291354 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 198943 m, 811 m/sec, 7973483 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 324403 m, 2606 m/sec, 5529320 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 202902 m, 791 m/sec, 8135675 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 336765 m, 2472 m/sec, 5745194 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 208077 m, 1035 m/sec, 8348524 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 347227 m, 2092 m/sec, 5924675 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 213323 m, 1049 m/sec, 8546270 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 362322 m, 3019 m/sec, 6172140 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 217511 m, 837 m/sec, 8716017 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 376873 m, 2910 m/sec, 6438870 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 222980 m, 1093 m/sec, 8941895 t fired, . Pages in use: 55 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 390165 m, 2658 m/sec, 6668565 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 227025 m, 809 m/sec, 9110439 t fired, . Pages in use: 55 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 404282 m, 2823 m/sec, 6946639 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 232127 m, 1020 m/sec, 9321328 t fired, . Pages in use: 55 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 415955 m, 2334 m/sec, 7171627 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 236663 m, 907 m/sec, 9509434 t fired, . Pages in use: 56 16 (type EXCL) for DLCround-PT-11a-CTLFireability-11 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 428650 m, 2539 m/sec, 7415370 t fired, . Pages in use: 57 16 (type EXCL) for 33 DLCround-PT-11a-CTLFireability-11 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 439839 m, 2237 m/sec, 7627257 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 1714 m, -46989 m/sec, 64965 t fired, . Pages in use: 59 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 448902 m, 1812 m/sec, 7817977 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 3313 m, 319 m/sec, 127377 t fired, . Pages in use: 59 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 459513 m, 2122 m/sec, 8002054 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 4951 m, 327 m/sec, 191246 t fired, . Pages in use: 59 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 469346 m, 1966 m/sec, 8175460 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 6455 m, 300 m/sec, 247822 t fired, . Pages in use: 59 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 476121 m, 1355 m/sec, 8308971 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 8128 m, 334 m/sec, 307622 t fired, . Pages in use: 59 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 487442 m, 2264 m/sec, 8520072 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 12079 m, 790 m/sec, 459098 t fired, . Pages in use: 60 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 497676 m, 2046 m/sec, 8727014 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 17107 m, 1005 m/sec, 664880 t fired, . Pages in use: 60 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 507393 m, 1943 m/sec, 8917617 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 21100 m, 798 m/sec, 829075 t fired, . Pages in use: 60 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 520857 m, 2692 m/sec, 9164899 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 23608 m, 501 m/sec, 935617 t fired, . Pages in use: 60 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 527631 m, 1354 m/sec, 9296268 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 24775 m, 233 m/sec, 983010 t fired, . Pages in use: 60 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 537654 m, 2004 m/sec, 9468753 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 27031 m, 451 m/sec, 1065703 t fired, . Pages in use: 60 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 546081 m, 1685 m/sec, 9626205 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 28630 m, 319 m/sec, 1130002 t fired, . Pages in use: 60 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 558819 m, 2547 m/sec, 9826994 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 30575 m, 389 m/sec, 1209389 t fired, . Pages in use: 60 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 574495 m, 3135 m/sec, 10086335 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 32378 m, 360 m/sec, 1280309 t fired, . Pages in use: 61 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 586478 m, 2396 m/sec, 10310985 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 35106 m, 545 m/sec, 1383807 t fired, . Pages in use: 61 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 598470 m, 2398 m/sec, 10534906 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 37521 m, 483 m/sec, 1486221 t fired, . Pages in use: 61 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 611062 m, 2518 m/sec, 10771493 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 39051 m, 306 m/sec, 1551679 t fired, . Pages in use: 61 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 626041 m, 2995 m/sec, 11029230 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 40787 m, 347 m/sec, 1627653 t fired, . Pages in use: 62 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-11a-CTLFireability-09 637302 m, 2252 m/sec, 11206865 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 42140 m, 270 m/sec, 1689833 t fired, . Pages in use: 62 16 (type EXCL) for DLCround-PT-11a-CTLFireability-09 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-11 45365 m, 645 m/sec, 1824741 t fired, . Pages in use: 62 16 (type EXCL) for 27 DLCround-PT-11a-CTLFireability-09 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 113 m, -127437 m/sec, 1631 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 62409 m, 3408 m/sec, 2514955 t fired, . Pages in use: 64 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 12897 m, 2556 m/sec, 190348 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 65539 m, 626 m/sec, 2651024 t fired, . Pages in use: 65 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 26588 m, 2738 m/sec, 411934 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 67520 m, 396 m/sec, 2741089 t fired, . Pages in use: 65 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 35411 m, 1764 m/sec, 559243 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 69100 m, 316 m/sec, 2810424 t fired, . Pages in use: 65 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 47848 m, 2487 m/sec, 754357 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 70524 m, 284 m/sec, 2872890 t fired, . Pages in use: 65 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 53615 m, 1153 m/sec, 867954 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 71581 m, 211 m/sec, 2918238 t fired, . Pages in use: 65 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 62689 m, 1814 m/sec, 1021783 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 73018 m, 287 m/sec, 2972216 t fired, . Pages in use: 65 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 71864 m, 1835 m/sec, 1168085 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 75348 m, 466 m/sec, 3066502 t fired, . Pages in use: 66 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 82981 m, 2223 m/sec, 1341558 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 76943 m, 319 m/sec, 3138909 t fired, . Pages in use: 66 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 94969 m, 2397 m/sec, 1520577 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 78091 m, 229 m/sec, 3188804 t fired, . Pages in use: 66 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 103805 m, 1767 m/sec, 1677794 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 79353 m, 252 m/sec, 3244738 t fired, . Pages in use: 66 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 114703 m, 2179 m/sec, 1857022 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 80718 m, 273 m/sec, 3299926 t fired, . Pages in use: 66 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 126430 m, 2345 m/sec, 2038508 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 81850 m, 226 m/sec, 3341605 t fired, . Pages in use: 66 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 137871 m, 2288 m/sec, 2225414 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 83284 m, 286 m/sec, 3395451 t fired, . Pages in use: 66 16 (type EXCL) for DLCround-PT-11a-CTLFireability-11 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 150702 m, 2566 m/sec, 2446474 t fired, . Pages in use: 66 16 (type EXCL) for 33 DLCround-PT-11a-CTLFireability-11 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 183815 m, 6622 m/sec, 3046013 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 274 m, -16602 m/sec, 9174 t fired, . Pages in use: 69 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 192791 m, 1795 m/sec, 3201563 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 1574 m, 260 m/sec, 59426 t fired, . Pages in use: 69 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 202047 m, 1851 m/sec, 3367831 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 2770 m, 239 m/sec, 107624 t fired, . Pages in use: 69 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 211168 m, 1824 m/sec, 3537840 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 4036 m, 253 m/sec, 154615 t fired, . Pages in use: 69 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 218348 m, 1436 m/sec, 3670334 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 5259 m, 244 m/sec, 203458 t fired, . Pages in use: 69 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 227835 m, 1897 m/sec, 3852356 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 6395 m, 227 m/sec, 245678 t fired, . Pages in use: 69 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 235613 m, 1555 m/sec, 3990561 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 7421 m, 205 m/sec, 282782 t fired, . Pages in use: 69 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 243419 m, 1561 m/sec, 4136147 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 8482 m, 212 m/sec, 321588 t fired, . Pages in use: 71 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 254039 m, 2124 m/sec, 4346005 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 9642 m, 232 m/sec, 366484 t fired, . Pages in use: 71 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 260867 m, 1365 m/sec, 4471186 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 10601 m, 191 m/sec, 401822 t fired, . Pages in use: 71 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 269622 m, 1751 m/sec, 4623985 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 14049 m, 689 m/sec, 538682 t fired, . Pages in use: 73 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 277039 m, 1483 m/sec, 4745156 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 15722 m, 334 m/sec, 608502 t fired, . Pages in use: 73 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 285383 m, 1668 m/sec, 4870101 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 16464 m, 148 m/sec, 638456 t fired, . Pages in use: 73 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 297575 m, 2438 m/sec, 5059883 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 17906 m, 288 m/sec, 696518 t fired, . Pages in use: 73 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 308856 m, 2256 m/sec, 5246573 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 19162 m, 251 m/sec, 749818 t fired, . Pages in use: 73 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 317637 m, 1756 m/sec, 5405136 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 20426 m, 252 m/sec, 801057 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 321458 m, 764 m/sec, 5472989 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 21647 m, 244 m/sec, 852156 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 328619 m, 1432 m/sec, 5609506 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 22517 m, 174 m/sec, 889814 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 340083 m, 2292 m/sec, 5791771 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 23841 m, 264 m/sec, 945216 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 346173 m, 1218 m/sec, 5905130 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 24988 m, 229 m/sec, 990233 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 352064 m, 1178 m/sec, 6023509 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 26058 m, 214 m/sec, 1028587 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 359385 m, 1464 m/sec, 6128941 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 27010 m, 190 m/sec, 1064773 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 367787 m, 1680 m/sec, 6275807 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 27867 m, 171 m/sec, 1099844 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 376018 m, 1646 m/sec, 6421224 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 29118 m, 250 m/sec, 1149677 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 383540 m, 1504 m/sec, 6566097 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 30813 m, 339 m/sec, 1218019 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 392179 m, 1727 m/sec, 6706611 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 31725 m, 182 m/sec, 1252333 t fired, . Pages in use: 74 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 398878 m, 1339 m/sec, 6842403 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 33186 m, 292 m/sec, 1309906 t fired, . Pages in use: 74 16 (type EXCL) for DLCround-PT-11a-CTLFireability-09 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-11 35183 m, 399 m/sec, 1387306 t fired, . Pages in use: 74 16 (type EXCL) for 27 DLCround-PT-11a-CTLFireability-09 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 81 m, -79759 m/sec, 1234 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 51585 m, 3280 m/sec, 2088808 t fired, . Pages in use: 76 16 (type EXCL) for DLCround-PT-11a-CTLFireability-11 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 9439 m, 1871 m/sec, 135046 t fired, . Pages in use: 79 16 (type EXCL) for 33 DLCround-PT-11a-CTLFireability-11 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 68732 m, 11858 m/sec, 1120047 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 18 m, -10313 m/sec, 110 t fired, . Pages in use: 81 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 77529 m, 1759 m/sec, 1254363 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 884 m, 173 m/sec, 31972 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 84103 m, 1314 m/sec, 1360586 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 1584 m, 140 m/sec, 59910 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 90003 m, 1180 m/sec, 1454281 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 2245 m, 132 m/sec, 85983 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 96886 m, 1376 m/sec, 1548500 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 2941 m, 139 m/sec, 114072 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 99802 m, 583 m/sec, 1611695 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 3897 m, 191 m/sec, 149484 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 106618 m, 1363 m/sec, 1728145 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 4599 m, 140 m/sec, 177653 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 113596 m, 1395 m/sec, 1837563 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 5222 m, 124 m/sec, 202032 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 123209 m, 1922 m/sec, 1989345 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 6132 m, 182 m/sec, 236121 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 130571 m, 1472 m/sec, 2097560 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 6897 m, 153 m/sec, 264885 t fired, . Pages in use: 82 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 139835 m, 1852 m/sec, 2257851 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 8021 m, 224 m/sec, 304037 t fired, . Pages in use: 83 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 148619 m, 1756 m/sec, 2408401 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 9065 m, 208 m/sec, 344854 t fired, . Pages in use: 83 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 156075 m, 1491 m/sec, 2531491 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 9895 m, 166 m/sec, 375656 t fired, . Pages in use: 84 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 164679 m, 1720 m/sec, 2696880 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 10849 m, 190 m/sec, 410498 t fired, . Pages in use: 84 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 171915 m, 1447 m/sec, 2821809 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 11680 m, 166 m/sec, 443168 t fired, . Pages in use: 84 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 178070 m, 1231 m/sec, 2936916 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 12395 m, 143 m/sec, 471656 t fired, . Pages in use: 84 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 186375 m, 1661 m/sec, 3084736 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 13286 m, 178 m/sec, 506986 t fired, . Pages in use: 84 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 192718 m, 1268 m/sec, 3200349 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 14040 m, 150 m/sec, 538218 t fired, . Pages in use: 84 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 199295 m, 1315 m/sec, 3313007 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 14743 m, 140 m/sec, 567467 t fired, . Pages in use: 85 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 206609 m, 1462 m/sec, 3451144 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 15515 m, 154 m/sec, 600173 t fired, . Pages in use: 85 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 213268 m, 1331 m/sec, 3574882 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 16375 m, 172 m/sec, 634886 t fired, . Pages in use: 85 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 219926 m, 1331 m/sec, 3699922 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 17278 m, 180 m/sec, 672001 t fired, . Pages in use: 86 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 225990 m, 1212 m/sec, 3820032 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 18117 m, 167 m/sec, 705642 t fired, . Pages in use: 86 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 231249 m, 1051 m/sec, 3915551 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 18899 m, 156 m/sec, 738245 t fired, . Pages in use: 86 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 239332 m, 1616 m/sec, 4059406 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 19930 m, 206 m/sec, 782356 t fired, . Pages in use: 87 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 246215 m, 1376 m/sec, 4187002 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 20742 m, 162 m/sec, 813401 t fired, . Pages in use: 87 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 250983 m, 953 m/sec, 4276330 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 21375 m, 126 m/sec, 840832 t fired, . Pages in use: 88 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 255019 m, 807 m/sec, 4365165 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 22175 m, 160 m/sec, 874370 t fired, . Pages in use: 88 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-11a-CTLFireability-09 262279 m, 1452 m/sec, 4500330 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 22931 m, 151 m/sec, 906585 t fired, . Pages in use: 88 16 (type EXCL) for DLCround-PT-11a-CTLFireability-09 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-11 24164 m, 246 m/sec, 958054 t fired, . Pages in use: 89 16 (type EXCL) for 27 DLCround-PT-11a-CTLFireability-09 (type EXCL) for DLCround-PT-11a-CTLFireability-11 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 -- Pages in use: 90 16 (type EXCL) for 33 DLCround-PT-11a-CTLFireability-11 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 166670 m, -19121 m/sec, 2732896 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 2 m, -4832 m/sec, 2 t fired, . Pages in use: 97 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 174760 m, 1618 m/sec, 2875970 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 2181 m, 435 m/sec, 83207 t fired, . Pages in use: 97 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 179957 m, 1039 m/sec, 2973764 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 2763 m, 116 m/sec, 107378 t fired, . Pages in use: 97 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 185054 m, 1019 m/sec, 3065505 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 3368 m, 121 m/sec, 129254 t fired, . Pages in use: 97 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 189073 m, 803 m/sec, 3132656 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 3873 m, 101 m/sec, 148654 t fired, . Pages in use: 97 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 193151 m, 815 m/sec, 3208302 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 4382 m, 101 m/sec, 169349 t fired, . Pages in use: 97 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 200729 m, 1515 m/sec, 3341459 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 5103 m, 144 m/sec, 197526 t fired, . Pages in use: 98 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 206054 m, 1065 m/sec, 3440545 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 5732 m, 125 m/sec, 221616 t fired, . Pages in use: 98 16 VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-09 212766 m, 1342 m/sec, 3566925 t fired, . 1/5 DLCround-PT-11a-CTLFireability-11 6375 m, 128 m/sec, 245117 t fired, . Pages in use: 99 16 (type EXCL) for DLCround-PT-11a-CTLFireability-09 (local timeout) VALUE PRODUCED BY CTL false CTL model checker false LTL model checker DISJ true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-11a-CTLFireability-11 7169 m, 158 m/sec, 274973 t fired, . Pages in use: 99 16 421 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-11a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCround-PT-11a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393200402"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-11a.tgz
mv DLCround-PT-11a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;