About the Execution of LoLA for DLCround-PT-09b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5782.712 | 1288020.00 | 1995651.00 | 3698.20 | FFTF?FTFFFFFFFT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r061-tall-162038393100378.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCround-PT-09b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038393100378
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.6M
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.4K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 81K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Mar 28 15:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 15:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 28 15:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 15:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.0K Mar 23 08:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 14K Mar 23 08:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Mar 22 15:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 11K Mar 22 15:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 4 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 1.3M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-09b-CTLFireability-00
FORMULA_NAME DLCround-PT-09b-CTLFireability-01
FORMULA_NAME DLCround-PT-09b-CTLFireability-02
FORMULA_NAME DLCround-PT-09b-CTLFireability-03
FORMULA_NAME DLCround-PT-09b-CTLFireability-04
FORMULA_NAME DLCround-PT-09b-CTLFireability-05
FORMULA_NAME DLCround-PT-09b-CTLFireability-06
FORMULA_NAME DLCround-PT-09b-CTLFireability-07
FORMULA_NAME DLCround-PT-09b-CTLFireability-08
FORMULA_NAME DLCround-PT-09b-CTLFireability-09
FORMULA_NAME DLCround-PT-09b-CTLFireability-10
FORMULA_NAME DLCround-PT-09b-CTLFireability-11
FORMULA_NAME DLCround-PT-09b-CTLFireability-12
FORMULA_NAME DLCround-PT-09b-CTLFireability-13
FORMULA_NAME DLCround-PT-09b-CTLFireability-14
FORMULA_NAME DLCround-PT-09b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620797979727
starting LoLA
BK_INPUT DLCround-PT-09b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCround-PT-09b-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-09b-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620799267747
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: LAUNCH task # 53 (type EQUN) for 18 DLCround-PT-09b-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SRCH) for 18 DLCround-PT-09b-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 1 (type EXCL) for DLCround-PT-09b-CTLFireability-00
lola: result : false
lola: markings : 184
lola: fired transitions : 253
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: try reading problem file /home/mcc/execution/CTLFireability-53.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 54 (type EXCL) for 18 DLCround-PT-09b-CTLFireability-06
lola: time limit : 192 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for DLCround-PT-09b-CTLFireability-06
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 55 (type SRCH) for DLCround-PT-09b-CTLFireability-06
lola: result : unknown
lola: time used : 11.000000
lola: memory pages used : 1
lola: CANCELED task # 52 (type FNDP) for DLCround-PT-09b-CTLFireability-06 (obsolete)
lola: CANCELED task # 53 (type EQUN) for DLCround-PT-09b-CTLFireability-06 (obsolete)
lola: LAUNCH task # 32 (type EXCL) for 31 DLCround-PT-09b-CTLFireability-09
lola: time limit : 206 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type FNDP) for DLCround-PT-09b-CTLFireability-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 11.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-05: SP ACTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-06: CONJ 0 0 0 0 5 0 0 1
DLCround-PT-09b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 0/206 0/32 DLCround-PT-09b-CTLFireability-09 --
Time elapsed: 710 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 58 (type FNDP) for 18 DLCround-PT-09b-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 18 DLCround-PT-09b-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 61 (type SRCH) for 18 DLCround-PT-09b-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type EQUN) for DLCround-PT-09b-CTLFireability-06
lola: result : true
lola: FINISHED task # 32 (type EXCL) for DLCround-PT-09b-CTLFireability-09
lola: result : false
lola: markings : 906
lola: fired transitions : 907
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 DLCround-PT-09b-CTLFireability-07
lola: time limit : 206 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type SRCH) for DLCround-PT-09b-CTLFireability-06
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 26 (type EXCL) for DLCround-PT-09b-CTLFireability-07
lola: result : false
lola: markings : 212
lola: fired transitions : 425
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 DLCround-PT-09b-CTLFireability-04
lola: time limit : 222 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/CTLFireability-59.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 58 (type FNDP) for DLCround-PT-09b-CTLFireability-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 2.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for DLCround-PT-09b-CTLFireability-06 (obsolete)
lola: FINISHED task # 59 (type EQUN) for DLCround-PT-09b-CTLFireability-06
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-06: CONJ true CONJ
DLCround-PT-09b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-09b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-09b-CTLFireability-05: SP ACTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 4/240 1/32 DLCround-PT-09b-CTLFireability-04 15539 m, 3107 m/sec, 29692 t fired, .
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DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-06: CONJ true CONJ
DLCround-PT-09b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-09b-CTLFireability-05: SP ACTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 9/240 1/32 DLCround-PT-09b-CTLFireability-04 29579 m, 2808 m/sec, 74668 t fired, .
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DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-06: CONJ true CONJ
DLCround-PT-09b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-09b-CTLFireability-05: SP ACTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 14/240 2/32 DLCround-PT-09b-CTLFireability-04 40956 m, 2275 m/sec, 117204 t fired, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-06: CONJ true CONJ
DLCround-PT-09b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-03: CTL 1 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-09b-CTLFireability-05: SP ACTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 21/240 2/32 DLCround-PT-09b-CTLFireability-04 59184 m, 3645 m/sec, 183049 t fired, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-06: CONJ true CONJ
DLCround-PT-09b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-09b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-09b-CTLFireability-05: SP ACTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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13 CTL EXCL 26/240 2/32 DLCround-PT-09b-CTLFireability-04 74180 m, 2999 m/sec, 231928 t fired, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-06: CONJ true CONJ
DLCround-PT-09b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-09: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-09b-CTLFireability-05: SP ACTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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13 CTL EXCL 31/240 2/32 DLCround-PT-09b-CTLFireability-04 89542 m, 3072 m/sec, 294864 t fired, .
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DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-06: CONJ true CONJ
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-09b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-09b-CTLFireability-05: SP ACTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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13 CTL EXCL 36/240 3/32 DLCround-PT-09b-CTLFireability-04 105586 m, 3208 m/sec, 360965 t fired, .
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DLCround-PT-09b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-09b-CTLFireability-10: F 0 1 0 0 1 0 0 0
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13 CTL EXCL 41/240 3/32 DLCround-PT-09b-CTLFireability-04 120350 m, 2952 m/sec, 429575 t fired, .
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13 CTL EXCL 15/2647 2/5 DLCround-PT-09b-CTLFireability-04 60725 m, 3748 m/sec, 188708 t fired, .
50 CTL EXCL 15/220 2/32 DLCround-PT-09b-CTLFireability-15 72525 m, 5548 m/sec, 204460 t fired, .
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13 CTL EXCL 20/2647 2/5 DLCround-PT-09b-CTLFireability-04 79240 m, 3703 m/sec, 251349 t fired, .
50 CTL EXCL 20/220 2/32 DLCround-PT-09b-CTLFireability-15 98888 m, 5272 m/sec, 275748 t fired, .
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13 CTL EXCL 25/2647 2/5 DLCround-PT-09b-CTLFireability-04 94466 m, 3045 m/sec, 313925 t fired, .
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13 CTL EXCL 30/2647 3/5 DLCround-PT-09b-CTLFireability-04 110619 m, 3230 m/sec, 382251 t fired, .
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13 CTL EXCL 35/2647 3/5 DLCround-PT-09b-CTLFireability-04 123678 m, 2611 m/sec, 447702 t fired, .
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13 CTL EXCL 40/2647 3/5 DLCround-PT-09b-CTLFireability-04 142650 m, 3794 m/sec, 512390 t fired, .
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13 CTL EXCL 45/2647 4/5 DLCround-PT-09b-CTLFireability-04 161430 m, 3756 m/sec, 580332 t fired, .
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13 CTL EXCL 50/2647 4/5 DLCround-PT-09b-CTLFireability-04 180130 m, 3740 m/sec, 644748 t fired, .
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13 CTL EXCL 55/2647 5/5 DLCround-PT-09b-CTLFireability-04 199316 m, 3837 m/sec, 711478 t fired, .
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13 CTL EXCL 60/2647 5/5 DLCround-PT-09b-CTLFireability-04 215320 m, 3200 m/sec, 779146 t fired, .
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13 CTL EXCL 65/2647 5/5 DLCround-PT-09b-CTLFireability-04 230996 m, 3135 m/sec, 846832 t fired, .
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13 CTL EXCL 70/2647 5/5 DLCround-PT-09b-CTLFireability-04 243804 m, 2561 m/sec, 913322 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 48/240 4/5 DLCround-PT-09b-CTLFireability-15 233391 m, 5143 m/sec, 648611 t fired, .
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50 CTL EXCL 58/240 5/5 DLCround-PT-09b-CTLFireability-15 280218 m, 4664 m/sec, 780666 t fired, .
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50 CTL EXCL 68/240 5/5 DLCround-PT-09b-CTLFireability-15 329288 m, 4752 m/sec, 916039 t fired, .
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lola: LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-09b-CTLFireability-12
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lola: FINISHED task # 41 (type EXCL) for DLCround-PT-09b-CTLFireability-12
lola: result : false
lola: markings : 372
lola: fired transitions : 377
lola: time used : 0.000000
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lola: LAUNCH task # 38 (type EXCL) for 37 DLCround-PT-09b-CTLFireability-11
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lola: markings : 1526
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lola: time limit : 386 sec
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lola: FINISHED task # 56 (type EXCL) for DLCround-PT-09b-CTLFireability-05
lola: result : false
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lola: time used : 0.000000
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lola: time limit : 773 sec
lola: memory limit: 32 pages
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DLCround-PT-09b-CTLFireability-09: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-10: F false state space / EG
DLCround-PT-09b-CTLFireability-11: CTL false CTL model checker
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lola: result : true
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lola: time limit : 1156 sec
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lola: FINISHED task # 47 (type EXCL) for DLCround-PT-09b-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
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lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-09b-CTLFireability-01
lola: time limit : 2313 sec
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lola: FINISHED task # 4 (type EXCL) for DLCround-PT-09b-CTLFireability-01
lola: result : false
lola: markings : 2
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-01: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-02: CTL true CTL model checker
DLCround-PT-09b-CTLFireability-03: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-04: CTL unknown AGGR
DLCround-PT-09b-CTLFireability-05: SP ACTL false LTL model checker
DLCround-PT-09b-CTLFireability-06: CONJ true CONJ
DLCround-PT-09b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-08: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-09: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-10: F false state space / EG
DLCround-PT-09b-CTLFireability-11: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-09b-CTLFireability-13: CTL false CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-09b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCround-PT-09b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393100378"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-09b.tgz
mv DLCround-PT-09b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;