MCC'2021- Execution of r061-tall-162038393100370

About the Execution of LoLA for DLCround-PT-09a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16245.876	2143573.00	4695744.00	7891.10	T?????T??TFFTTFF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.
Waiting for the VM to be
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==================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCround-PT-09a,
Time confinement is 3600
Memory confinement is
Number of cores is 4
Run identifier is r061-tall-16
==================================

--------------------
preparation of the directory
/home/mcc/execution
total 932K
-rw-r--r-- 1 mcc users 12K May
-rw-r--r-- 1 mcc users 113K
-rw-r--r-- 1 mcc users 9.7K May
-rw-r--r-- 1 mcc users 87K
-rw-r--r-- 1 mcc users 4.2K May
-rw-r--r-- 1 mcc users 6.4K May
-rw-r--r-- 1 mcc users 3.4K
-rw-r--r-- 1 mcc users 26K
-rw-r--r-- 1 mcc users 1.9K
-rw-r--r-- 1 mcc users 15K
-rw-r--r-- 1 mcc users 3.9K
-rw-r--r-- 1 mcc users 21K
-rw-r--r-- 1 mcc users 2.4K
-rw-r--r-- 1 mcc users 13K
-rw-r--r-- 1 mcc users 1.6K
-rw-r--r-- 1 mcc users 3.6K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 566K May

--------------------
content from stdout:

=== Data for post analysis

The expected result is a
BOOL_VECTOR

here is the order used to
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi
FORMULA_NAME DLCround-PT-09a-CTLFi

=== Now, execution of the

BK_START 1620796390991

starting LoLA
BK_INPUT DLCround-PT-09a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/
current directory: /home/mcc/execu
CTLFireability

FORMULA DLCround-PT-09a-CTLFireability-00

FORMULA DLCround-PT-09a-CTLFireability-13

FORMULA DLCround-PT-09a-CTLFireability-15

FORMULA DLCround-PT-09a-CTLFireability-12

FORMULA DLCround-PT-09a-CTLFireability-14

FORMULA DLCround-PT-09a-CTLFireability-11

FORMULA DLCround-PT-09a-CTLFireability-10

FORMULA DLCround-PT-09a-CTLFireability-09

FORMULA DLCround-PT-09a-CTLFireability-06

BK_STOP 1620798534564

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file
lola: reading net from
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file /home/mcc/
lola: Reading formula.
lola: Using XML format
lola: reading XML formula
lola: reading formula from
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
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lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
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lola: RELEASE
lola: RELEASE
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lola: RELEASE
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lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Rule S: 0 transitions
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
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lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
FINISHED FORMULA: CATEGORY

PENDING FORMULAS: CATEGORY
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TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 50 secs.
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lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: LAUNCH task # 42
lola: time limit : 186 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: FINISHED task # 42
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 1 (type
lola: time limit : 221 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: rewrite Frontend/Parser/fo
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lola: LAUNCH task # 44
lola: time limit : 236 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44
lola: result
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lola: LAUNCH task # 58
lola: time limit : 221 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/fo
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lola: LAUNCH task # 62
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 67
lola: time limit : 32000000
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lola: LAUNCH task # 69
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: FINISHED task # 69
lola: result
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TASK CATEGORY TYPE TIME/TLIMIT
58 EXEG EXCL 1/221
62 EF FNDP 0/1772
67 EF STEQ 0/1772

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lola: CANCELED task # 67
lola: LAUNCH task # 47
lola: time limit : 272 sec
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sara: try reading problem
sara: place or transition
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=================================== examination is CTLFireability seconds 16384 MBytes 2038393100370 =================================== to be used: 5 16:58 CTLCardinality.txt May 10 09:42 CTLCardinality.xml 5 16:58 CTLFireability.txt May 10 09:42 CTLFireability.xml 6 14:48 GenericPropertiesDefinition.xml 6 14:48 GenericPropertiesVerdict.xml Mar 28 15:58 LTLCardinality.txt Mar 28 15:58 LTLCardinality.xml Mar 28 15:58 LTLFireability.txt Mar 28 15:58 LTLFireability.xml Mar 23 08:16 ReachabilityCardinality.txt Mar 23 08:16 ReachabilityCardinality.xml Mar 22 15:47 ReachabilityFireability.txt Mar 22 15:47 ReachabilityFireability.xml Mar 22 09:10 UpperBounds.txt Mar 22 09:10 UpperBounds.xml 6 May 5 16:51 equiv_col 4 May 5 16:51 instance 6 May 5 16:51 iscolored 5 16:51 model.pnml generated by BenchKit (invocation template) vector of booleans build the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 tool begins bin tion TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT (--pnmlnet) /home/mcc/execution/model.pnml place/transition net execution/model.pnml (--xmlformula) /home/mcc/execution/CTLFireability.xml rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:317 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:253 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:253 rmula_rewrite.k:394 rmula_rewrite.k:478 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:314 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:253 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:451 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:253 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:391 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:299 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:547 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:325 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:439 rmula_rewrite.k:478 rmula_rewrite.k:553 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:544 rmula_rewrite.k:553 rmula_rewrite.k:544 rmula_rewrite.k:457 rmula_rewrite.k:439 rmula_rewrite.k:439 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:250 in 1.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. removed,0 places removed in 0.000000 secs. in 1.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 1.000000 secs. in 0.000000 secs. in 0.000000 secs. in 1.000000 secs. in 1.000000 secs. VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 3 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 16 in 1.000000 secs. rmula_rewrite.k:812 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:807 (type EXCL) for 39 DLCround-PT-09a-CTLFireability-13 rmula_rewrite.k:814 rmula_rewrite.k:808 rmula_rewrite.k:806 (type EXCL) for DLCround-PT-09a-CTLFireability-13 : false 4 4 0.000000 1 EXCL) for 0 DLCround-PT-09a-CTLFireability-00 (type EXCL) for DLCround-PT-09a-CTLFireability-00 : true 27 299 0.000000 1 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:806 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:811 rmula_rewrite.k:807 rmula_rewrite.k:814 rmula_rewrite.k:807 rmula_rewrite.k:812 rmula_rewrite.k:809 rmula_rewrite.k:813 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:812 rmula_rewrite.k:814 rmula_rewrite.k:812 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:808 (type EXCL) for 39 DLCround-PT-09a-CTLFireability-13 (type EXCL) for DLCround-PT-09a-CTLFireability-13 : true 0.000000 1 rmula_rewrite.k:715 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:813 rmula_rewrite.k:808 rmula_rewrite.k:811 rmula_rewrite.k:809 rmula_rewrite.k:814 rmula_rewrite.k:812 rmula_rewrite.k:815 rmula_rewrite.k:815 rmula_rewrite.k:806 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:811 rmula_rewrite.k:814 rmula_rewrite.k:808 rmula_rewrite.k:811 rmula_rewrite.k:809 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:815 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:809 rmula_rewrite.k:811 rmula_rewrite.k:811 rmula_rewrite.k:815 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:815 rmula_rewrite.k:815 (type EXCL) for 49 DLCround-PT-09a-CTLFireability-15 rmula_rewrite.k:721 rmula_rewrite.k:787 rmula_rewrite.k:721 rmula_rewrite.k:787 rmula_rewrite.k:721 rmula_rewrite.k:787 rmula_rewrite.k:721 rmula_rewrite.k:787 rmula_rewrite.k:721 rmula_rewrite.k:787 rmula_rewrite.k:721 rmula_rewrite.k:787 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:809 rmula_rewrite.k:809 rmula_rewrite.k:809 rmula_rewrite.k:813 rmula_rewrite.k:809 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:809 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:808 rmula_rewrite.k:808 rmula_rewrite.k:813 rmula_rewrite.k:813 (type FNDP) for 49 DLCround-PT-09a-CTLFireability-15 sec (type EQUN) for 49 DLCround-PT-09a-CTLFireability-15 sec (type SRCH) for 49 DLCround-PT-09a-CTLFireability-15 sec (type SRCH) for DLCround-PT-09a-CTLFireability-15 : unknown 0.000000 1 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 5 3 0 4 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-15 . 0/5 DLCround-PT-09a-CTLFireability-15 1 attempts, . 0/5 DLCround-PT-09a-CTLFireability-15 -- Pages in use: 2 16 (type EXCL) for DLCround-PT-09a-CTLFireability-15 : false 1.000000 1 (type FNDP) for DLCround-PT-09a-CTLFireability-15 : true 1 1.000000 0 rmula_rewrite.k:721 rmula_rewrite.k:787 (type EQUN) for DLCround-PT-09a-CTLFireability-15 (obsolete) (type EXCL) for 46 DLCround-PT-09a-CTLFireability-14 file /home/mcc/execution/CTLFireability-67.sara. ordering is non-deterministic VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-14 34684 m, 6936 m/sec, 710251 t fired, . Pages in use: 2 16 (type EQUN) for DLCround-PT-09a-CTLFireability-15 : true VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-14 72804 m, 7624 m/sec, 1481435 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-14 112561 m, 7951 m/sec, 2296337 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-14 152048 m, 7897 m/sec, 3093880 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-14 190955 m, 7781 m/sec, 3895918 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-14 230057 m, 7820 m/sec, 4692072 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-14 267990 m, 7586 m/sec, 5482332 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-14 308706 m, 8143 m/sec, 6302040 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-14 348373 m, 7933 m/sec, 7125216 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-14 386719 m, 7669 m/sec, 7904938 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-14 425659 m, 7788 m/sec, 8722006 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-14 463703 m, 7608 m/sec, 9488912 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-14 501893 m, 7638 m/sec, 10241576 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-14 540566 m, 7734 m/sec, 11021955 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-14 577543 m, 7395 m/sec, 11782012 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-14 616801 m, 7851 m/sec, 12593043 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-14 657036 m, 8047 m/sec, 13383814 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-14 695151 m, 7623 m/sec, 14152035 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-14 732608 m, 7491 m/sec, 14914585 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-14 767865 m, 7051 m/sec, 15632875 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-14 803885 m, 7204 m/sec, 16369257 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-14 841101 m, 7443 m/sec, 17129727 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-14 880428 m, 7865 m/sec, 17938599 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-14 921499 m, 8214 m/sec, 18761508 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-14 959672 m, 7634 m/sec, 19534622 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-14 997605 m, 7586 m/sec, 20303565 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-14 1034597 m, 7398 m/sec, 21060884 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-14 1070902 m, 7261 m/sec, 21828484 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-14 1108931 m, 7605 m/sec, 22611174 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-14 1157907 m, 9795 m/sec, 23604973 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-14 1196278 m, 7674 m/sec, 24394691 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-14 1234820 m, 7708 m/sec, 25177857 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-14 1271278 m, 7291 m/sec, 25930040 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-14 1308021 m, 7348 m/sec, 26683790 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-14 1344631 m, 7322 m/sec, 27425584 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-14 1381759 m, 7425 m/sec, 28183757 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-14 1420292 m, 7706 m/sec, 28943017 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-14 1457398 m, 7421 m/sec, 29697184 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-14 1494553 m, 7431 m/sec, 30441042 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-14 1533784 m, 7846 m/sec, 31206633 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-14 1571899 m, 7623 m/sec, 31968983 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-14 1611050 m, 7830 m/sec, 32720826 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-14 1650684 m, 7926 m/sec, 33548077 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-14 1687130 m, 7289 m/sec, 34286096 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-14 1726697 m, 7913 m/sec, 35060124 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-14 1763592 m, 7379 m/sec, 35814229 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-14 1801705 m, 7622 m/sec, 36596725 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-14 1839942 m, 7647 m/sec, 37372070 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-14 1877433 m, 7498 m/sec, 38141270 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-14 1916597 m, 7832 m/sec, 38940168 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-14 1954692 m, 7619 m/sec, 39692134 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-14 1989182 m, 6898 m/sec, 40417592 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-14 2027706 m, 7704 m/sec, 41202533 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-14 2065096 m, 7478 m/sec, 41974491 t fired, . Pages in use: 9 16 (type EXCL) for DLCround-PT-09a-CTLFireability-14 (local timeout) VALUE PRODUCED BY CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 9 16 (type EXCL) for 36 DLCround-PT-09a-CTLFireability-12 (type EXCL) for 46 DLCround-PT-09a-CTLFireability-14 (type EXCL) for DLCround-PT-09a-CTLFireability-12 : true 22 143 0.000000 1 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-09a-CTLFireability-14 35413 m, -405936 m/sec, 724932 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-09a-CTLFireability-14 75066 m, 7930 m/sec, 1523788 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-09a-CTLFireability-14 114829 m, 7952 m/sec, 2345002 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-09a-CTLFireability-14 153758 m, 7785 m/sec, 3129204 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-09a-CTLFireability-14 191832 m, 7614 m/sec, 3913149 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-09a-CTLFireability-14 230161 m, 7665 m/sec, 4693799 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-09a-CTLFireability-14 267971 m, 7562 m/sec, 5481936 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-09a-CTLFireability-14 308382 m, 8082 m/sec, 6294868 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-09a-CTLFireability-14 345832 m, 7490 m/sec, 7073700 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-09a-CTLFireability-14 383666 m, 7566 m/sec, 7844373 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ true CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-09a-CTLFireability-14 421489 m, 7564 m/sec, 8636738 t fired, . Pages in use: 13 16 (type EXCL) for DLCround-PT-09a-CTLFireability-14 : false 434207 8892758 56.000000 2 (type EXCL) for 33 DLCround-PT-09a-CTLFireability-11 (type EXCL) for DLCround-PT-09a-CTLFireability-11 : false 5 12 0.000000 1 (type EXCL) for 30 DLCround-PT-09a-CTLFireability-10 (type EXCL) for DLCround-PT-09a-CTLFireability-10 : false 1 0.000000 1 (type EXCL) for 27 DLCround-PT-09a-CTLFireability-09 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-09 25198 m, 5039 m/sec, 485088 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-09 61333 m, 7227 m/sec, 1169603 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-09 93343 m, 6402 m/sec, 1854470 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-09 127713 m, 6874 m/sec, 2532300 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-09 161308 m, 6719 m/sec, 3211226 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-09 190578 m, 5854 m/sec, 3844085 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-09 221736 m, 6231 m/sec, 4511977 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-09 257073 m, 7067 m/sec, 5139300 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-09 288869 m, 6359 m/sec, 5785803 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-09 319893 m, 6204 m/sec, 6424774 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-09 357846 m, 7590 m/sec, 7069811 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-09 387942 m, 6019 m/sec, 7690139 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-09 415772 m, 5566 m/sec, 8290341 t fired, . Pages in use: 13 16 (type EXCL) for DLCround-PT-09a-CTLFireability-09 : true 416462 8304602 65.000000 2 (type EXCL) for 21 DLCround-PT-09a-CTLFireability-07 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-07 33556 m, 6711 m/sec, 460374 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-07 67572 m, 6803 m/sec, 1122062 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-07 102205 m, 6926 m/sec, 1732986 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-07 143580 m, 8275 m/sec, 2355100 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-07 173297 m, 5943 m/sec, 2973565 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-07 204763 m, 6293 m/sec, 3563265 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-07 237880 m, 6623 m/sec, 4186442 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-07 269482 m, 6320 m/sec, 4781094 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-07 302192 m, 6542 m/sec, 5390398 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-07 334128 m, 6387 m/sec, 5984674 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-07 363128 m, 5800 m/sec, 6581063 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-07 393403 m, 6055 m/sec, 7158278 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-07 429003 m, 7120 m/sec, 7749900 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-07 456288 m, 5457 m/sec, 8347899 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-07 484510 m, 5644 m/sec, 8927113 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-07 518064 m, 6710 m/sec, 9535238 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-07 552134 m, 6814 m/sec, 10107531 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-07 598599 m, 9293 m/sec, 10641935 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-07 636599 m, 7600 m/sec, 11205406 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-07 679965 m, 8673 m/sec, 11763589 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-07 710067 m, 6020 m/sec, 12379583 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-07 743624 m, 6711 m/sec, 12987554 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-07 778437 m, 6962 m/sec, 13603825 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-07 805440 m, 5400 m/sec, 14175212 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-07 832547 m, 5421 m/sec, 14750172 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-07 864633 m, 6417 m/sec, 15333633 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-07 892085 m, 5490 m/sec, 15933814 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-07 922851 m, 6153 m/sec, 16510688 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-07 953488 m, 6127 m/sec, 17091581 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 980455 m, 5393 m/sec, 17664012 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 1004566 m, 4822 m/sec, 18295348 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 1031466 m, 5380 m/sec, 18870483 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 1056467 m, 5000 m/sec, 19439211 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 1084605 m, 5627 m/sec, 20013028 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 1113014 m, 5681 m/sec, 20586505 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 1139677 m, 5332 m/sec, 21143218 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 1169423 m, 5949 m/sec, 21720392 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-09a-CTLFireability-07 1197068 m, 5529 m/sec, 22285863 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-07 1224824 m, 5551 m/sec, 22842113 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-07 1251927 m, 5420 m/sec, 23487054 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-07 1275639 m, 4742 m/sec, 24079706 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-07 1305451 m, 5962 m/sec, 24645476 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-07 1335244 m, 5958 m/sec, 25190717 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-07 1361484 m, 5248 m/sec, 25755918 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-07 1387981 m, 5299 m/sec, 26334247 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-09a-CTLFireability-07 1414907 m, 5385 m/sec, 26902378 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1446207 m, 6260 m/sec, 27520566 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1482962 m, 7351 m/sec, 28108372 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1516188 m, 6645 m/sec, 28733348 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1544149 m, 5592 m/sec, 29332786 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1575605 m, 6291 m/sec, 29907194 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1602720 m, 5423 m/sec, 30517592 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1632183 m, 5892 m/sec, 31097693 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1661982 m, 5959 m/sec, 31633859 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-09a-CTLFireability-07 1685131 m, 4629 m/sec, 32207697 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-07 1710485 m, 5070 m/sec, 32760061 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-07 1739594 m, 5821 m/sec, 33312580 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-07 1764321 m, 4945 m/sec, 33882351 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-07 1793325 m, 5800 m/sec, 34419414 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-07 1820622 m, 5459 m/sec, 35045986 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-07 1855520 m, 6979 m/sec, 35682945 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-07 1887462 m, 6388 m/sec, 36329460 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-09a-CTLFireability-07 1915701 m, 5647 m/sec, 36956498 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-07 1946124 m, 6084 m/sec, 37574785 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-07 1983794 m, 7534 m/sec, 38210448 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-07 2027027 m, 8646 m/sec, 38805432 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-07 2062838 m, 7162 m/sec, 39442175 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-07 2103534 m, 8139 m/sec, 40046511 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-07 2132594 m, 5812 m/sec, 40643954 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-09a-CTLFireability-07 2162652 m, 6011 m/sec, 41235065 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCround-PT-09a-CTLFireability-07 2194902 m, 6450 m/sec, 41777564 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCround-PT-09a-CTLFireability-07 2216601 m, 4339 m/sec, 42299928 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCround-PT-09a-CTLFireability-07 2247060 m, 6091 m/sec, 42913392 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCround-PT-09a-CTLFireability-07 2275076 m, 5603 m/sec, 43493433 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCround-PT-09a-CTLFireability-07 2304771 m, 5939 m/sec, 44076935 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCround-PT-09a-CTLFireability-07 2337950 m, 6635 m/sec, 44642570 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCround-PT-09a-CTLFireability-07 2361591 m, 4728 m/sec, 45217929 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCround-PT-09a-CTLFireability-07 2383920 m, 4465 m/sec, 45779589 t fired, . Pages in use: 21 16 (type EXCL) for DLCround-PT-09a-CTLFireability-07 (local timeout) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 22 16 (type EXCL) for 18 DLCround-PT-09a-CTLFireability-06 (type EXCL) for 21 DLCround-PT-09a-CTLFireability-07 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 28552 m, 5710 m/sec, 690377 t fired, . 1/5 DLCround-PT-09a-CTLFireability-07 43622 m, -468059 m/sec, 647568 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 56821 m, 5653 m/sec, 1411193 t fired, . 1/5 DLCround-PT-09a-CTLFireability-07 77688 m, 6813 m/sec, 1300687 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 79794 m, 4594 m/sec, 2041757 t fired, . 1/5 DLCround-PT-09a-CTLFireability-07 114451 m, 7352 m/sec, 1957010 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 104629 m, 4967 m/sec, 2715712 t fired, . 1/5 DLCround-PT-09a-CTLFireability-07 157464 m, 8602 m/sec, 2625540 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 128010 m, 4676 m/sec, 3347938 t fired, . 1/5 DLCround-PT-09a-CTLFireability-07 188739 m, 6255 m/sec, 3273502 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 150315 m, 4461 m/sec, 3961903 t fired, . 1/5 DLCround-PT-09a-CTLFireability-07 222328 m, 6717 m/sec, 3869331 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 177059 m, 5348 m/sec, 4602322 t fired, . 2/5 DLCround-PT-09a-CTLFireability-07 254677 m, 6469 m/sec, 4486730 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 201437 m, 4875 m/sec, 5208573 t fired, . 2/5 DLCround-PT-09a-CTLFireability-07 287797 m, 6624 m/sec, 5113257 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-06 226392 m, 4991 m/sec, 5860519 t fired, . 2/5 DLCround-PT-09a-CTLFireability-07 319705 m, 6381 m/sec, 5739568 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 248738 m, 4469 m/sec, 6467953 t fired, . 2/5 DLCround-PT-09a-CTLFireability-07 350802 m, 6219 m/sec, 6338696 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 270592 m, 4370 m/sec, 7069151 t fired, . 2/5 DLCround-PT-09a-CTLFireability-07 378998 m, 5639 m/sec, 6934394 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 294916 m, 4864 m/sec, 7726225 t fired, . 2/5 DLCround-PT-09a-CTLFireability-07 412660 m, 6732 m/sec, 7510936 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 316288 m, 4274 m/sec, 8332993 t fired, . 2/5 DLCround-PT-09a-CTLFireability-07 444474 m, 6362 m/sec, 8090187 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 337787 m, 4299 m/sec, 8947610 t fired, . 2/5 DLCround-PT-09a-CTLFireability-07 474955 m, 6096 m/sec, 8703691 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 358679 m, 4178 m/sec, 9542544 t fired, . 3/5 DLCround-PT-09a-CTLFireability-07 503809 m, 5770 m/sec, 9311362 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 381556 m, 4575 m/sec, 10163929 t fired, . 3/5 DLCround-PT-09a-CTLFireability-07 540575 m, 7353 m/sec, 9909897 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 402875 m, 4263 m/sec, 10756458 t fired, . 3/5 DLCround-PT-09a-CTLFireability-07 583560 m, 8597 m/sec, 10441263 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 424356 m, 4296 m/sec, 11360941 t fired, . 3/5 DLCround-PT-09a-CTLFireability-07 621483 m, 7584 m/sec, 10987464 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 448938 m, 4916 m/sec, 12021004 t fired, . 3/5 DLCround-PT-09a-CTLFireability-07 660352 m, 7773 m/sec, 11549535 t fired, . Pages in use: 30 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-06 473229 m, 4858 m/sec, 12657899 t fired, . 3/5 DLCround-PT-09a-CTLFireability-07 700227 m, 7975 m/sec, 12150592 t fired, . Pages in use: 30 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 495329 m, 4420 m/sec, 13281250 t fired, . 4/5 DLCround-PT-09a-CTLFireability-07 726401 m, 5234 m/sec, 12725235 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 515920 m, 4118 m/sec, 13871072 t fired, . 4/5 DLCround-PT-09a-CTLFireability-07 764451 m, 7610 m/sec, 13329389 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 536879 m, 4191 m/sec, 14477134 t fired, . 4/5 DLCround-PT-09a-CTLFireability-07 791045 m, 5318 m/sec, 13915092 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 557871 m, 4198 m/sec, 15064205 t fired, . 4/5 DLCround-PT-09a-CTLFireability-07 816932 m, 5177 m/sec, 14454764 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 584102 m, 5246 m/sec, 15738444 t fired, . 4/5 DLCround-PT-09a-CTLFireability-07 849333 m, 6480 m/sec, 15012210 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 609110 m, 5001 m/sec, 16412535 t fired, . 4/5 DLCround-PT-09a-CTLFireability-07 876903 m, 5514 m/sec, 15613791 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 634674 m, 5112 m/sec, 17018772 t fired, . 4/5 DLCround-PT-09a-CTLFireability-07 909501 m, 6519 m/sec, 16182710 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 659088 m, 4882 m/sec, 17642917 t fired, . 4/5 DLCround-PT-09a-CTLFireability-07 933713 m, 4842 m/sec, 16732041 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 682142 m, 4610 m/sec, 18270104 t fired, . 5/5 DLCround-PT-09a-CTLFireability-07 964168 m, 6091 m/sec, 17300510 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-06 701804 m, 3932 m/sec, 18844232 t fired, . 5/5 DLCround-PT-09a-CTLFireability-07 989895 m, 5145 m/sec, 17903866 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-06 722813 m, 4201 m/sec, 19407084 t fired, . 5/5 DLCround-PT-09a-CTLFireability-07 1012762 m, 4573 m/sec, 18467399 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-06 744230 m, 4283 m/sec, 20010269 t fired, . 5/5 DLCround-PT-09a-CTLFireability-07 1039417 m, 5331 m/sec, 19028227 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-06 752499 m, 1653 m/sec, 20237924 t fired, . 5/5 DLCround-PT-09a-CTLFireability-07 1064013 m, 4919 m/sec, 19602221 t fired, . Pages in use: 35 16 (type EXCL) for DLCround-PT-09a-CTLFireability-06 : true 752499 20237924 166.000000 4 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-09a-CTLFireability-07 1090894 m, 5376 m/sec, 20155502 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-09a-CTLFireability-07 1122363 m, 6293 m/sec, 20721457 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-09a-CTLFireability-07 1146310 m, 4789 m/sec, 21306111 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-09a-CTLFireability-07 1177262 m, 6190 m/sec, 21887046 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-09a-CTLFireability-07 1203640 m, 5275 m/sec, 22452281 t fired, . Pages in use: 35 16 (type EXCL) for DLCround-PT-09a-CTLFireability-07 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 35 16 (type EXCL) for 15 DLCround-PT-09a-CTLFireability-05 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-05 39947 m, 7989 m/sec, 660051 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-05 74704 m, 6951 m/sec, 1319623 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-05 105078 m, 6074 m/sec, 1974744 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-05 136885 m, 6361 m/sec, 2626086 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-05 167843 m, 6191 m/sec, 3262650 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-05 198144 m, 6060 m/sec, 3902994 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-09a-CTLFireability-05 233572 m, 7085 m/sec, 4521697 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-05 266266 m, 6538 m/sec, 5147283 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-05 297147 m, 6176 m/sec, 5774609 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-05 326991 m, 5968 m/sec, 6415892 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-05 357968 m, 6195 m/sec, 7067248 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-05 387250 m, 5856 m/sec, 7709191 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-05 415331 m, 5616 m/sec, 8340112 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-05 443096 m, 5553 m/sec, 8973353 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-09a-CTLFireability-05 474325 m, 6245 m/sec, 9604782 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-05 503778 m, 5890 m/sec, 10250986 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-05 532488 m, 5742 m/sec, 10905127 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-05 567489 m, 7000 m/sec, 11585001 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-05 598555 m, 6213 m/sec, 12255941 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-05 625391 m, 5367 m/sec, 12867901 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-05 653741 m, 5670 m/sec, 13523664 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-05 681923 m, 5636 m/sec, 14143629 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-09a-CTLFireability-05 716403 m, 6896 m/sec, 14812613 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CONJ false state space /EXEG IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-09a-CTLFireability-05 746910 m, 6101 m/sec, 15444681 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker has been truncated ====== archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-09a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCround-PT-09a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393100370"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-09a.tgz
mv DLCround-PT-09a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;