MCC'2021- Execution of r061-tall-162038393000306

About the Execution of LoLA for DLCround-PT-05a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16238.575	2358812.00	4096919.00	10326.00	??T?T?TF?TTFFTTF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.
Waiting for the VM to be
..................................
............
..................................
..................................
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==================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCround-PT-05a,
Time confinement is 3600
Memory confinement is
Number of cores is 4
Run identifier is r061-tall-16
==================================

--------------------
preparation of the directory
/home/mcc/execution
total 668K
-rw-r--r-- 1 mcc users 15K May
-rw-r--r-- 1 mcc users 141K
-rw-r--r-- 1 mcc users 12K May
-rw-r--r-- 1 mcc users 104K
-rw-r--r-- 1 mcc users 4.2K May
-rw-r--r-- 1 mcc users 6.4K May
-rw-r--r-- 1 mcc users 3.2K
-rw-r--r-- 1 mcc users 24K
-rw-r--r-- 1 mcc users 1.9K
-rw-r--r-- 1 mcc users 17K
-rw-r--r-- 1 mcc users 3.1K
-rw-r--r-- 1 mcc users 15K
-rw-r--r-- 1 mcc users 2.9K
-rw-r--r-- 1 mcc users 19K
-rw-r--r-- 1 mcc users 1.6K
-rw-r--r-- 1 mcc users 3.6K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 259K May

--------------------
content from stdout:

=== Data for post analysis

The expected result is a
BOOL_VECTOR

here is the order used to
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi
FORMULA_NAME DLCround-PT-05a-CTLFi

=== Now, execution of the

BK_START 1620790929716

starting LoLA
BK_INPUT DLCround-PT-05a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/
current directory: /home/mcc/execu
CTLFireability

FORMULA DLCround-PT-05a-CTLFireability-06

FORMULA DLCround-PT-05a-CTLFireability-15

FORMULA DLCround-PT-05a-CTLFireability-14

FORMULA DLCround-PT-05a-CTLFireability-13

FORMULA DLCround-PT-05a-CTLFireability-12

FORMULA DLCround-PT-05a-CTLFireability-04

FORMULA DLCround-PT-05a-CTLFireability-10

FORMULA DLCround-PT-05a-CTLFireability-09

FORMULA DLCround-PT-05a-CTLFireability-07

FORMULA DLCround-PT-05a-CTLFireability-02

FORMULA DLCround-PT-05a-CTLFireability-11

BK_STOP 1620793288528

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file
lola: reading net from
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file /home/mcc/
lola: Reading formula.
lola: Using XML format
lola: reading XML formula
lola: reading formula from
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
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lola: rewrite Frontend/Parser/fo
lola: RELEASE
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lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
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lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Created skeleton
lola: Created skeleton
lola: Rule S: 0 transitions
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
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lola: rewrite Frontend/Parser/fo
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lola: LAUNCH task # 19
lola: time limit : 108 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19
lola: result
lola: markings :
lola: time used :
lola: memory pages used :
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: LAUNCH task # 76
lola: time limit : 111 sec
lola: memory limit: 32 pages
lola: FINISHED task # 76
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 77
lola: time limit : 115 sec
lola: memory limit: 32 pages
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: FINISHED task # 77
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 13
lola: time limit : 127 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
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lola: rewrite Frontend/Parser/fo
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
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lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
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lola: rewrite Frontend/Parser/fo
lola: Created skeleton
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FINISHED FORMULA: CATEGORY
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lola: rewrite Frontend/Parser/fo
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lola: Created skeleton
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lola: LAUNCH task # 79
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: FINISHED task # 79
lola: result
lola: time used :
lola: memory pages used :
lola: Created skeleton
lola: Created skeleton
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=================================== examination is CTLFireability seconds 16384 MBytes 2038393000306 =================================== to be used: 5 16:58 CTLCardinality.txt May 10 09:42 CTLCardinality.xml 5 16:58 CTLFireability.txt May 10 09:42 CTLFireability.xml 6 14:48 GenericPropertiesDefinition.xml 6 14:48 GenericPropertiesVerdict.xml Mar 28 15:58 LTLCardinality.txt Mar 28 15:58 LTLCardinality.xml Mar 28 15:58 LTLFireability.txt Mar 28 15:58 LTLFireability.xml Mar 23 07:58 ReachabilityCardinality.txt Mar 23 07:58 ReachabilityCardinality.xml Mar 22 15:24 ReachabilityFireability.txt Mar 22 15:24 ReachabilityFireability.xml Mar 22 09:10 UpperBounds.txt Mar 22 09:10 UpperBounds.xml 6 May 5 16:51 equiv_col 4 May 5 16:51 instance 6 May 5 16:51 iscolored 5 16:51 model.pnml generated by BenchKit (invocation template) vector of booleans build the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 tool begins bin tion TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT (--pnmlnet) /home/mcc/execution/model.pnml place/transition net execution/model.pnml (--xmlformula) /home/mcc/execution/CTLFireability.xml rmula_rewrite.k:253 rmula_rewrite.k:472 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:299 rmula_rewrite.k:448 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:253 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:388 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:253 rmula_rewrite.k:250 rmula_rewrite.k:250 rmula_rewrite.k:550 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:250 rmula_rewrite.k:250 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:472 rmula_rewrite.k:448 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:445 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:553 rmula_rewrite.k:553 rmula_rewrite.k:553 rmula_rewrite.k:553 rmula_rewrite.k:553 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:253 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:299 rmula_rewrite.k:460 rmula_rewrite.k:250 rmula_rewrite.k:250 rmula_rewrite.k:250 rmula_rewrite.k:250 rmula_rewrite.k:478 rmula_rewrite.k:253 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:439 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:250 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:253 in 0.000000 secs. in 0.000000 secs. removed,0 places removed in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 2.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. rmula_rewrite.k:806 rmula_rewrite.k:809 rmula_rewrite.k:809 rmula_rewrite.k:809 rmula_rewrite.k:812 rmula_rewrite.k:812 rmula_rewrite.k:811 rmula_rewrite.k:808 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:809 (type EXCL) for 18 DLCround-PT-05a-CTLFireability-06 (type EXCL) for DLCround-PT-05a-CTLFireability-06 : true 1 0.000000 1 rmula_rewrite.k:749 rmula_rewrite.k:787 rmula_rewrite.k:734 rmula_rewrite.k:787 (type EXCL) for 65 DLCround-PT-05a-CTLFireability-15 (type EXCL) for DLCround-PT-05a-CTLFireability-15 : true 2 2 0.000000 1 (type EXCL) for 65 DLCround-PT-05a-CTLFireability-15 in 0.000000 secs. rmula_rewrite.k:806 rmula_rewrite.k:809 rmula_rewrite.k:813 (type EXCL) for DLCround-PT-05a-CTLFireability-15 : true 2 2 0.000000 1 (type EXCL) for 12 DLCround-PT-05a-CTLFireability-04 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:806 in 0.000000 secs. rmula_rewrite.k:812 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:814 rmula_rewrite.k:811 rmula_rewrite.k:814 rmula_rewrite.k:814 rmula_rewrite.k:809 in 0.000000 secs. rmula_rewrite.k:811 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:808 rmula_rewrite.k:809 rmula_rewrite.k:807 rmula_rewrite.k:806 rmula_rewrite.k:811 rmula_rewrite.k:807 rmula_rewrite.k:808 rmula_rewrite.k:811 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:812 rmula_rewrite.k:811 rmula_rewrite.k:812 rmula_rewrite.k:812 rmula_rewrite.k:812 rmula_rewrite.k:814 in 0.000000 secs. rmula_rewrite.k:812 rmula_rewrite.k:811 rmula_rewrite.k:809 rmula_rewrite.k:679 rmula_rewrite.k:679 in 0.000000 secs. rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:808 rmula_rewrite.k:811 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:714 rmula_rewrite.k:811 rmula_rewrite.k:808 rmula_rewrite.k:806 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:809 rmula_rewrite.k:806 rmula_rewrite.k:806 rmula_rewrite.k:814 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 0 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 DISJ 0 5 0 0 4 0 0 0 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 DISJ 0 0 0 0 4 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-04 9513 m, 1902 m/sec, 215309 t fired, . Pages in use: 1 16 rmula_rewrite.k:808 rmula_rewrite.k:812 rmula_rewrite.k:808 rmula_rewrite.k:807 rmula_rewrite.k:807 in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:809 rmula_rewrite.k:808 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:810 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:808 rmula_rewrite.k:815 rmula_rewrite.k:811 rmula_rewrite.k:812 rmula_rewrite.k:815 rmula_rewrite.k:807 rmula_rewrite.k:806 rmula_rewrite.k:815 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:815 rmula_rewrite.k:811 rmula_rewrite.k:812 rmula_rewrite.k:815 rmula_rewrite.k:808 (type SKEL/SRCH) for 30 DLCround-PT-05a-CTLFireability-10 sec (type SKEL/SRCH) for DLCround-PT-05a-CTLFireability-10 : false 0.000000 1 in 1.000000 secs. in 0.000000 secs. VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-04 43201 m, 6737 m/sec, 1059570 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-04 76518 m, 6663 m/sec, 1909464 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-04 109296 m, 6555 m/sec, 2795455 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-04 141037 m, 6348 m/sec, 3642307 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-04 174755 m, 6743 m/sec, 4522046 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-04 205200 m, 6089 m/sec, 5353794 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-04 239019 m, 6763 m/sec, 6234512 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 269551 m, 6106 m/sec, 7051897 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 299258 m, 5941 m/sec, 7882210 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 328218 m, 5792 m/sec, 8619509 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 352427 m, 4841 m/sec, 9147100 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 376856 m, 4885 m/sec, 9674110 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 401026 m, 4834 m/sec, 10229889 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 423044 m, 4403 m/sec, 10734876 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 450750 m, 5541 m/sec, 11257283 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-04 474483 m, 4746 m/sec, 11759872 t fired, . Pages in use: 2 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 497709 m, 4645 m/sec, 12264710 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 521930 m, 4844 m/sec, 12806499 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 548712 m, 5356 m/sec, 13332182 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 571806 m, 4618 m/sec, 13798100 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 597814 m, 5201 m/sec, 14329657 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 620881 m, 4613 m/sec, 14859653 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 643618 m, 4547 m/sec, 15417280 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 665674 m, 4411 m/sec, 15956320 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 686956 m, 4256 m/sec, 16435601 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-04 708409 m, 4290 m/sec, 16931147 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 733293 m, 4976 m/sec, 17594177 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 755110 m, 4363 m/sec, 18143963 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 783853 m, 5748 m/sec, 18923715 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 810083 m, 5246 m/sec, 19625955 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 836936 m, 5370 m/sec, 20356479 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 870398 m, 6692 m/sec, 21204961 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 903226 m, 6565 m/sec, 22062412 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 934261 m, 6207 m/sec, 22895492 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-05a-CTLFireability-04 959309 m, 5009 m/sec, 23581305 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-05a-CTLFireability-04 985214 m, 5181 m/sec, 24076755 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-05a-CTLFireability-04 1007080 m, 4373 m/sec, 24550211 t fired, . Pages in use: 5 16 (type EXCL) for DLCround-PT-05a-CTLFireability-04 (local timeout) VALUE PRODUCED BY CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 1 0 0 5 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 5 16 (type EXCL) for 65 DLCround-PT-05a-CTLFireability-15 (type EXCL) for 12 DLCround-PT-05a-CTLFireability-04 (type EXCL) for DLCround-PT-05a-CTLFireability-15 : false 2 2 1.000000 1 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 34607 m, -194494 m/sec, 838420 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 70595 m, 7197 m/sec, 1750857 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 101116 m, 6104 m/sec, 2573495 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 133362 m, 6449 m/sec, 3440495 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 167746 m, 6876 m/sec, 4331424 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 199524 m, 6355 m/sec, 5193256 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 233045 m, 6704 m/sec, 6063206 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 264752 m, 6341 m/sec, 6919004 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 294845 m, 6018 m/sec, 7758437 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 324965 m, 6024 m/sec, 8546241 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 350566 m, 5120 m/sec, 9108611 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 375231 m, 4933 m/sec, 9637121 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 399496 m, 4853 m/sec, 10191953 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 421278 m, 4356 m/sec, 10698922 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 448572 m, 5458 m/sec, 11215419 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 471842 m, 4654 m/sec, 11710259 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 495291 m, 4689 m/sec, 12209688 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 519268 m, 4795 m/sec, 12747953 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 545874 m, 5321 m/sec, 13274478 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 569530 m, 4731 m/sec, 13750406 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 594246 m, 4943 m/sec, 14256803 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 617170 m, 4584 m/sec, 14763524 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 640571 m, 4680 m/sec, 15351701 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 661720 m, 4229 m/sec, 15867281 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 682638 m, 4183 m/sec, 16340400 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 704288 m, 4330 m/sec, 16833323 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 727196 m, 4581 m/sec, 17420493 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 750027 m, 4566 m/sec, 18010472 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 775652 m, 5125 m/sec, 18714075 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 803921 m, 5653 m/sec, 19480313 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 828228 m, 4861 m/sec, 20115478 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 860071 m, 6368 m/sec, 20969378 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 895222 m, 7030 m/sec, 21842346 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 926104 m, 6176 m/sec, 22684325 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 952576 m, 5294 m/sec, 23405044 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-05a-CTLFireability-04 977632 m, 5011 m/sec, 23933722 t fired, . Pages in use: 10 16 VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-05a-CTLFireability-04 1000989 m, 4671 m/sec, 24413124 t fired, . Pages in use: 10 16 (type EXCL) for DLCround-PT-05a-CTLFireability-04 (local timeout) VALUE PRODUCED BY CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 10 16 (type EXCL) for 62 DLCround-PT-05a-CTLFireability-14 (type EXCL) for 12 DLCround-PT-05a-CTLFireability-04 (type EXCL) for DLCround-PT-05a-CTLFireability-14 : true 2 7 0.000000 1 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 36492 m, -192899 m/sec, 888710 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 71473 m, 6996 m/sec, 1774572 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 104308 m, 6567 m/sec, 2664709 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 138179 m, 6774 m/sec, 3567933 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 171028 m, 6569 m/sec, 4420701 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 201138 m, 6022 m/sec, 5239036 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 232939 m, 6360 m/sec, 6060284 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 263206 m, 6053 m/sec, 6879440 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 292494 m, 5857 m/sec, 7695839 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 322833 m, 6067 m/sec, 8498564 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 347276 m, 4888 m/sec, 9034643 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 371198 m, 4784 m/sec, 9552992 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 395280 m, 4816 m/sec, 10092857 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 416763 m, 4296 m/sec, 10594918 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 442344 m, 5116 m/sec, 11098719 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 465535 m, 4638 m/sec, 11583186 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 489559 m, 4804 m/sec, 12087074 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 512578 m, 4603 m/sec, 12602737 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 536236 m, 4731 m/sec, 13086156 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 559948 m, 4742 m/sec, 13560748 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 582857 m, 4581 m/sec, 14027331 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 604859 m, 4400 m/sec, 14472963 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 626423 m, 4312 m/sec, 15004052 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 647687 m, 4252 m/sec, 15521206 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 668117 m, 4086 m/sec, 16012038 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 688481 m, 4072 m/sec, 16472701 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 709340 m, 4171 m/sec, 16949868 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 734415 m, 5015 m/sec, 17626605 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 755621 m, 4241 m/sec, 18156460 t fired, . Pages in use: 17 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 783951 m, 5666 m/sec, 18926461 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 811145 m, 5438 m/sec, 19653148 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 837766 m, 5324 m/sec, 20380576 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 872029 m, 6852 m/sec, 21244423 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 904509 m, 6496 m/sec, 22096502 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 935608 m, 6219 m/sec, 22938802 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 961182 m, 5114 m/sec, 23626538 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-05a-CTLFireability-04 988765 m, 5516 m/sec, 24141937 t fired, . Pages in use: 19 16 (type EXCL) for DLCround-PT-05a-CTLFireability-04 (local timeout) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 19 16 (type EXCL) for 59 DLCround-PT-05a-CTLFireability-13 (type EXCL) for 12 DLCround-PT-05a-CTLFireability-04 (type EXCL) for DLCround-PT-05a-CTLFireability-13 : true 6364 173672 1.000000 1 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 31756 m, -191401 m/sec, 762293 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 65977 m, 6844 m/sec, 1625576 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 90294 m, 4863 m/sec, 2277080 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 120653 m, 6071 m/sec, 3104784 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 150204 m, 5910 m/sec, 3882675 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 182176 m, 6394 m/sec, 4725122 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 210267 m, 5618 m/sec, 5492853 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 241355 m, 6217 m/sec, 6297436 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 270042 m, 5737 m/sec, 7063807 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 296117 m, 5215 m/sec, 7794210 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 325265 m, 5829 m/sec, 8552794 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 345658 m, 4078 m/sec, 8997066 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 368951 m, 4658 m/sec, 9507620 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 390745 m, 4358 m/sec, 9984488 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 411628 m, 4176 m/sec, 10475928 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 433033 m, 4281 m/sec, 10925675 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 455956 m, 4584 m/sec, 11367248 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 477835 m, 4375 m/sec, 11822098 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 499024 m, 4237 m/sec, 12296993 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 521712 m, 4537 m/sec, 12801582 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 546968 m, 5051 m/sec, 13296682 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 571903 m, 4987 m/sec, 13800084 t fired, . Pages in use: 27 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 596541 m, 4927 m/sec, 14303244 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 620144 m, 4720 m/sec, 14840015 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 640769 m, 4125 m/sec, 15356201 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 659972 m, 3840 m/sec, 15826757 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 680526 m, 4110 m/sec, 16291184 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 700424 m, 3979 m/sec, 16742205 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 721920 m, 4299 m/sec, 17280336 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 742624 m, 4140 m/sec, 17826421 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 764773 m, 4429 m/sec, 18409806 t fired, . Pages in use: 29 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 791216 m, 5288 m/sec, 19119986 t fired, . Pages in use: 30 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 812788 m, 4314 m/sec, 19695288 t fired, . Pages in use: 30 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 834775 m, 4397 m/sec, 20293807 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 865332 m, 6111 m/sec, 21089587 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 893496 m, 5632 m/sec, 21795214 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-05a-CTLFireability-04 922852 m, 5871 m/sec, 22596795 t fired, . Pages in use: 31 16 (type EXCL) for DLCround-PT-05a-CTLFireability-04 (local timeout) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 31 16 (type EXCL) for 56 DLCround-PT-05a-CTLFireability-12 (type EXCL) for 12 DLCround-PT-05a-CTLFireability-04 (type EXCL) for DLCround-PT-05a-CTLFireability-12 : false 1 2 1.000000 1 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 37044 m, -177161 m/sec, 902608 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 61477 m, 4886 m/sec, 1509887 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 81782 m, 4061 m/sec, 2045168 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 99483 m, 3540 m/sec, 2525586 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 116260 m, 3355 m/sec, 2990209 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 130896 m, 2927 m/sec, 3377642 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 147535 m, 3327 m/sec, 3809893 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 168548 m, 4202 m/sec, 4353645 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 185237 m, 3337 m/sec, 4807896 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 200182 m, 2989 m/sec, 5211174 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 219035 m, 3770 m/sec, 5722650 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 236861 m, 3565 m/sec, 6175223 t fired, . Pages in use: 35 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 251562 m, 2940 m/sec, 6578269 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 266758 m, 3039 m/sec, 6972149 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 290476 m, 4743 m/sec, 7643527 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 317143 m, 5333 m/sec, 8360541 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 331228 m, 2817 m/sec, 8689428 t fired, . Pages in use: 37 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 344840 m, 2722 m/sec, 8979751 t fired, . Pages in use: 37 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 355283 m, 2088 m/sec, 9205204 t fired, . Pages in use: 37 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 365030 m, 1949 m/sec, 9427555 t fired, . Pages in use: 37 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 378338 m, 2661 m/sec, 9703954 t fired, . Pages in use: 37 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 390712 m, 2474 m/sec, 9983898 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 404593 m, 2776 m/sec, 10311638 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 419183 m, 2918 m/sec, 10651514 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 432855 m, 2734 m/sec, 10922722 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 447398 m, 2908 m/sec, 11193483 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 462307 m, 2981 m/sec, 11511775 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 473918 m, 2322 m/sec, 11748813 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 489081 m, 3032 m/sec, 12076449 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 500530 m, 2289 m/sec, 12330303 t fired, . Pages in use: 40 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 515333 m, 2960 m/sec, 12658299 t fired, . Pages in use: 40 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 534027 m, 3738 m/sec, 13044098 t fired, . Pages in use: 40 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 549033 m, 3001 m/sec, 13338605 t fired, . Pages in use: 40 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 565703 m, 3334 m/sec, 13672128 t fired, . Pages in use: 41 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 580669 m, 2993 m/sec, 13986568 t fired, . Pages in use: 41 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 598723 m, 3610 m/sec, 14347502 t fired, . Pages in use: 41 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 613963 m, 3048 m/sec, 14682372 t fired, . Pages in use: 41 16 (type EXCL) for DLCround-PT-05a-CTLFireability-04 (local timeout) VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 5 0 0 6 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 41 16 (type EXCL) for 30 DLCround-PT-05a-CTLFireability-10 (type EXCL) for 12 DLCround-PT-05a-CTLFireability-04 (type EXCL) for DLCround-PT-05a-CTLFireability-10 : false 2.000000 1 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 8406 m, -121111 m/sec, 190349 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 31956 m, 4710 m/sec, 767466 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 47521 m, 3113 m/sec, 1177036 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 67982 m, 4092 m/sec, 1680322 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 85828 m, 3569 m/sec, 2153724 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 104223 m, 3679 m/sec, 2662323 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 120302 m, 3215 m/sec, 3096494 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 136120 m, 3163 m/sec, 3512345 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 153497 m, 3475 m/sec, 3968687 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 174794 m, 4259 m/sec, 4523184 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 189181 m, 2877 m/sec, 4911232 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 203130 m, 2789 m/sec, 5293981 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-05a-CTLFireability-04 223363 m, 4046 m/sec, 5826155 t fired, . Pages in use: 45 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 242757 m, 3878 m/sec, 6335605 t fired, . Pages in use: 46 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 259937 m, 3436 m/sec, 6791595 t fired, . Pages in use: 46 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 273584 m, 2729 m/sec, 7163126 t fired, . Pages in use: 46 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 291859 m, 3655 m/sec, 7679280 t fired, . Pages in use: 46 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 310749 m, 3778 m/sec, 8190575 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 330289 m, 3908 m/sec, 8668123 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 345859 m, 3114 m/sec, 9001761 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 358906 m, 2609 m/sec, 9286591 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 372258 m, 2670 m/sec, 9573394 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 386349 m, 2818 m/sec, 9881446 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 399151 m, 2560 m/sec, 10182634 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 416956 m, 3561 m/sec, 10599081 t fired, . Pages in use: 48 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 437471 m, 4103 m/sec, 11004274 t fired, . Pages in use: 49 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 451703 m, 2846 m/sec, 11277237 t fired, . Pages in use: 49 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-05a-CTLFireability-04 465578 m, 2775 m/sec, 11584053 t fired, . Pages in use: 49 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 488443 m, 4573 m/sec, 12061625 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 7 0 0 1 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-05a-CTLFireability-04 506521 m, 3615 m/sec, 12470663 t fired, . Pages in use: 50 16 (type EXCL) for DLCround-PT-05a-CTLFireability-04 : true 526988 12908943 153.000000 3 (type EXCL) for 30 DLCround-PT-05a-CTLFireability-10 (type EXCL) for DLCround-PT-05a-CTLFireability-10 : true 1 2 0.000000 1 (type EXCL) for 27 DLCround-PT-05a-CTLFireability-09 (type EXCL) for DLCround-PT-05a-CTLFireability-09 : true 1 1 0.000000 1 (type EXCL) for 21 DLCround-PT-05a-CTLFireability-07 (type EXCL) for DLCround-PT-05a-CTLFireability-07 : false 2 1 0.000000 1 (type EXCL) for 9 DLCround-PT-05a-CTLFireability-03 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 2322 m, 464 m/sec, 79834 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 33710 m, 6277 m/sec, 1115527 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 64213 m, 6100 m/sec, 2099366 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 94507 m, 6058 m/sec, 3090396 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 122876 m, 5673 m/sec, 3988419 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 151503 m, 5725 m/sec, 4896383 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 180574 m, 5814 m/sec, 5794775 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 210386 m, 5962 m/sec, 6758352 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-05a-CTLFireability-03 240421 m, 6007 m/sec, 7723254 t fired, . Pages in use: 50 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-03 270160 m, 5947 m/sec, 8652567 t fired, . Pages in use: 51 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-03 300629 m, 6093 m/sec, 9606937 t fired, . Pages in use: 51 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-03 330809 m, 6036 m/sec, 10542804 t fired, . Pages in use: 51 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-03 362596 m, 6357 m/sec, 11563599 t fired, . Pages in use: 51 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-03 393565 m, 6193 m/sec, 12534108 t fired, . Pages in use: 52 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-03 421773 m, 5641 m/sec, 13431693 t fired, . Pages in use: 52 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-03 450516 m, 5748 m/sec, 14341324 t fired, . Pages in use: 52 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-05a-CTLFireability-03 475968 m, 5090 m/sec, 15141938 t fired, . Pages in use: 52 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-03 503172 m, 5440 m/sec, 16058790 t fired, . Pages in use: 53 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-03 530496 m, 5464 m/sec, 16959876 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-03 558023 m, 5505 m/sec, 17811379 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-03 584892 m, 5373 m/sec, 18659212 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-03 612370 m, 5495 m/sec, 19523316 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-03 640003 m, 5526 m/sec, 20451733 t fired, . Pages in use: 54 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-03 668116 m, 5622 m/sec, 21321964 t fired, . Pages in use: 55 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-05a-CTLFireability-03 696265 m, 5629 m/sec, 22201433 t fired, . Pages in use: 55 16 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker DISJ true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL true CTL model checker DISJ false DISJ has been truncated ====== archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-05a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCround-PT-05a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393000306"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-05a.tgz
mv DLCround-PT-05a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;