fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r061-tall-162038393000290
Last Updated
Jun 28, 2021

About the Execution of LoLA for DLCround-PT-04a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16245.831 3580480.00 7689833.00 8631.60 ????????????FFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r061-tall-162038393000290.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCround-PT-04a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4

Run identifier is r061-tall-162038393000290
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 568K
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 107K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 97K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 28 15:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 28 15:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Mar 23 07:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 23 07:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 22 15:23 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 22 15:23 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 4 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 200K May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-04a-CTLFireability-00
FORMULA_NAME DLCround-PT-04a-CTLFireability-01
FORMULA_NAME DLCround-PT-04a-CTLFireability-02
FORMULA_NAME DLCround-PT-04a-CTLFireability-03
FORMULA_NAME DLCround-PT-04a-CTLFireability-04
FORMULA_NAME DLCround-PT-04a-CTLFireability-05
FORMULA_NAME DLCround-PT-04a-CTLFireability-06
FORMULA_NAME DLCround-PT-04a-CTLFireability-07
FORMULA_NAME DLCround-PT-04a-CTLFireability-08
FORMULA_NAME DLCround-PT-04a-CTLFireability-09
FORMULA_NAME DLCround-PT-04a-CTLFireability-10
FORMULA_NAME DLCround-PT-04a-CTLFireability-11
FORMULA_NAME DLCround-PT-04a-CTLFireability-12
FORMULA_NAME DLCround-PT-04a-CTLFireability-13
FORMULA_NAME DLCround-PT-04a-CTLFireability-14
FORMULA_NAME DLCround-PT-04a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1620769889357

starting LoLA
BK_INPUT DLCround-PT-04a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCround-PT-04a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-04a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-04a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-04a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620773469837

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 54 (type EXCL) for 51 DLCround-PT-04a-CTLFireability-13
lola: time limit : 137 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 54 (type EXCL) for DLCround-PT-04a-CTLFireability-13
lola: result : false
lola: markings : 87
lola: fired transitions : 1492
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-04a-CTLFireability-02
lola: time limit : 155 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 70 (type FNDP) for 34 DLCround-PT-04a-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type EQUN) for 34 DLCround-PT-04a-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SRCH) for 34 DLCround-PT-04a-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 73 (type SRCH) for DLCround-PT-04a-CTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 70 (type FNDP) for DLCround-PT-04a-CTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 71 (type EQUN) for DLCround-PT-04a-CTLFireability-10 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
sara: try reading problem file /home/mcc/execution/CTLFireability-71.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 71 (type EQUN) for DLCround-PT-04a-CTLFireability-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 3/198 1/32 DLCround-PT-04a-CTLFireability-02 15649 m, 3129 m/sec, 324440 t fired, .

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DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 8/198 1/32 DLCround-PT-04a-CTLFireability-02 46035 m, 6077 m/sec, 999057 t fired, .

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DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 13/198 1/32 DLCround-PT-04a-CTLFireability-02 74186 m, 5630 m/sec, 1661426 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 18/198 1/32 DLCround-PT-04a-CTLFireability-02 102970 m, 5756 m/sec, 2335587 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 23/198 1/32 DLCround-PT-04a-CTLFireability-02 133382 m, 6082 m/sec, 3019949 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 28/198 1/32 DLCround-PT-04a-CTLFireability-02 158862 m, 5096 m/sec, 3710062 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 33/198 1/32 DLCround-PT-04a-CTLFireability-02 188002 m, 5828 m/sec, 4418869 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 38/198 1/32 DLCround-PT-04a-CTLFireability-02 217155 m, 5830 m/sec, 5151613 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 43/198 2/32 DLCround-PT-04a-CTLFireability-02 245654 m, 5699 m/sec, 5810173 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 48/198 2/32 DLCround-PT-04a-CTLFireability-02 272681 m, 5405 m/sec, 6482544 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 53/198 2/32 DLCround-PT-04a-CTLFireability-02 301142 m, 5692 m/sec, 7193532 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 58/198 2/32 DLCround-PT-04a-CTLFireability-02 325500 m, 4871 m/sec, 7826940 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 63/198 2/32 DLCround-PT-04a-CTLFireability-02 349317 m, 4763 m/sec, 8490176 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 68/198 2/32 DLCround-PT-04a-CTLFireability-02 375524 m, 5241 m/sec, 9151410 t fired, .

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DLCround-PT-04a-CTLFireability-13: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-04a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 73/198 2/32 DLCround-PT-04a-CTLFireability-02 402267 m, 5348 m/sec, 9867115 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 78/198 2/32 DLCround-PT-04a-CTLFireability-02 427611 m, 5068 m/sec, 10558063 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
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DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 83/198 2/32 DLCround-PT-04a-CTLFireability-02 451844 m, 4846 m/sec, 11247973 t fired, .

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DLCround-PT-04a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-10: DISJ 0 1 0 0 5 0 0 1
DLCround-PT-04a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-04a-CTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-04a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 88/198 2/32 DLCround-PT-04a-CTLFireability-02 479455 m, 5522 m/sec, 11931021 t fired, .

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7 CTL EXCL 93/198 3/32 DLCround-PT-04a-CTLFireability-02 506016 m, 5312 m/sec, 12584598 t fired, .

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7 CTL EXCL 98/198 3/32 DLCround-PT-04a-CTLFireability-02 534643 m, 5725 m/sec, 13191176 t fired, .

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7 CTL EXCL 103/198 3/32 DLCround-PT-04a-CTLFireability-02 558574 m, 4786 m/sec, 13885542 t fired, .

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7 CTL EXCL 108/198 3/32 DLCround-PT-04a-CTLFireability-02 581558 m, 4596 m/sec, 14527345 t fired, .

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7 CTL EXCL 113/198 3/32 DLCround-PT-04a-CTLFireability-02 604958 m, 4680 m/sec, 15255034 t fired, .

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7 CTL EXCL 118/198 3/32 DLCround-PT-04a-CTLFireability-02 630099 m, 5028 m/sec, 15901058 t fired, .

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7 CTL EXCL 123/198 3/32 DLCround-PT-04a-CTLFireability-02 656134 m, 5207 m/sec, 16595600 t fired, .

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7 CTL EXCL 128/198 3/32 DLCround-PT-04a-CTLFireability-02 681010 m, 4975 m/sec, 17294164 t fired, .

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7 CTL EXCL 133/198 3/32 DLCround-PT-04a-CTLFireability-02 707205 m, 5239 m/sec, 17964144 t fired, .

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7 CTL EXCL 138/198 4/32 DLCround-PT-04a-CTLFireability-02 731476 m, 4854 m/sec, 18603531 t fired, .

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7 CTL EXCL 143/198 4/32 DLCround-PT-04a-CTLFireability-02 756686 m, 5042 m/sec, 19245951 t fired, .

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7 CTL EXCL 148/198 4/32 DLCround-PT-04a-CTLFireability-02 781341 m, 4931 m/sec, 19919393 t fired, .

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7 CTL EXCL 153/198 4/32 DLCround-PT-04a-CTLFireability-02 803352 m, 4402 m/sec, 20555097 t fired, .

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7 CTL EXCL 158/198 4/32 DLCround-PT-04a-CTLFireability-02 829657 m, 5261 m/sec, 21207443 t fired, .

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7 CTL EXCL 163/198 4/32 DLCround-PT-04a-CTLFireability-02 856382 m, 5345 m/sec, 21916499 t fired, .

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7 CTL EXCL 168/198 4/32 DLCround-PT-04a-CTLFireability-02 878236 m, 4370 m/sec, 22602490 t fired, .

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7 CTL EXCL 173/198 4/32 DLCround-PT-04a-CTLFireability-02 903034 m, 4959 m/sec, 23256550 t fired, .

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7 CTL EXCL 178/198 4/32 DLCround-PT-04a-CTLFireability-02 926811 m, 4755 m/sec, 23908649 t fired, .

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7 CTL EXCL 188/198 5/32 DLCround-PT-04a-CTLFireability-02 974592 m, 4348 m/sec, 25217438 t fired, .

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7 CTL EXCL 193/198 5/32 DLCround-PT-04a-CTLFireability-02 996592 m, 4400 m/sec, 25877457 t fired, .

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7 CTL EXCL 198/198 5/32 DLCround-PT-04a-CTLFireability-02 1021001 m, 4881 m/sec, 26566714 t fired, .

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7 CTL EXCL 5/198 1/5 DLCround-PT-04a-CTLFireability-02 32116 m, -197777 m/sec, 671524 t fired, .

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7 CTL EXCL 20/198 1/5 DLCround-PT-04a-CTLFireability-02 122925 m, 6295 m/sec, 2780022 t fired, .

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7 CTL EXCL 25/198 1/5 DLCround-PT-04a-CTLFireability-02 148654 m, 5145 m/sec, 3456169 t fired, .

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7 CTL EXCL 30/198 1/5 DLCround-PT-04a-CTLFireability-02 177674 m, 5804 m/sec, 4167153 t fired, .

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7 CTL EXCL 35/198 1/5 DLCround-PT-04a-CTLFireability-02 205028 m, 5470 m/sec, 4802735 t fired, .

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7 CTL EXCL 40/198 1/5 DLCround-PT-04a-CTLFireability-02 232110 m, 5416 m/sec, 5498412 t fired, .

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7 CTL EXCL 45/198 2/5 DLCround-PT-04a-CTLFireability-02 260515 m, 5681 m/sec, 6162470 t fired, .

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7 CTL EXCL 50/198 2/5 DLCround-PT-04a-CTLFireability-02 289132 m, 5723 m/sec, 6862515 t fired, .

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7 CTL EXCL 55/198 2/5 DLCround-PT-04a-CTLFireability-02 315406 m, 5254 m/sec, 7568936 t fired, .

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7 CTL EXCL 60/198 2/5 DLCround-PT-04a-CTLFireability-02 340597 m, 5038 m/sec, 8246147 t fired, .

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7 CTL EXCL 65/198 2/5 DLCround-PT-04a-CTLFireability-02 366226 m, 5125 m/sec, 8904256 t fired, .

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7 CTL EXCL 70/198 2/5 DLCround-PT-04a-CTLFireability-02 391020 m, 4958 m/sec, 9565249 t fired, .

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7 CTL EXCL 90/198 3/5 DLCround-PT-04a-CTLFireability-02 498098 m, 5424 m/sec, 12389386 t fired, .

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7 CTL EXCL 95/198 3/5 DLCround-PT-04a-CTLFireability-02 527991 m, 5978 m/sec, 13033779 t fired, .

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7 CTL EXCL 100/198 3/5 DLCround-PT-04a-CTLFireability-02 552869 m, 4975 m/sec, 13711468 t fired, .

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7 CTL EXCL 105/198 3/5 DLCround-PT-04a-CTLFireability-02 575827 m, 4591 m/sec, 14360329 t fired, .

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7 CTL EXCL 110/198 3/5 DLCround-PT-04a-CTLFireability-02 599630 m, 4760 m/sec, 15071057 t fired, .

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7 CTL EXCL 115/198 3/5 DLCround-PT-04a-CTLFireability-02 624735 m, 5021 m/sec, 15753981 t fired, .

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7 CTL EXCL 120/198 3/5 DLCround-PT-04a-CTLFireability-02 652153 m, 5483 m/sec, 16470171 t fired, .

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7 CTL EXCL 126/198 3/5 DLCround-PT-04a-CTLFireability-02 677000 m, 4969 m/sec, 17177753 t fired, .

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7 CTL EXCL 131/198 3/5 DLCround-PT-04a-CTLFireability-02 703533 m, 5306 m/sec, 17867496 t fired, .

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7 CTL EXCL 136/198 4/5 DLCround-PT-04a-CTLFireability-02 728389 m, 4971 m/sec, 18526443 t fired, .

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7 CTL EXCL 191/198 5/5 DLCround-PT-04a-CTLFireability-02 1002644 m, 4615 m/sec, 26035639 t fired, .

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7 CTL EXCL 196/198 5/5 DLCround-PT-04a-CTLFireability-02 1026108 m, 4692 m/sec, 26716836 t fired, .

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7 CTL EXCL 5/198 1/5 DLCround-PT-04a-CTLFireability-02 33209 m, -198579 m/sec, 694027 t fired, .

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7 CTL EXCL 10/198 1/5 DLCround-PT-04a-CTLFireability-02 64495 m, 6257 m/sec, 1423799 t fired, .

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7 CTL EXCL 35/198 1/5 DLCround-PT-04a-CTLFireability-02 205892 m, 5760 m/sec, 4827285 t fired, .

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7 CTL EXCL 40/198 1/5 DLCround-PT-04a-CTLFireability-02 232205 m, 5262 m/sec, 5502538 t fired, .

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7 CTL EXCL 45/198 2/5 DLCround-PT-04a-CTLFireability-02 260010 m, 5561 m/sec, 6148951 t fired, .

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7 CTL EXCL 110/198 3/5 DLCround-PT-04a-CTLFireability-02 599640 m, 4729 m/sec, 15071224 t fired, .

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7 CTL EXCL 115/198 3/5 DLCround-PT-04a-CTLFireability-02 625035 m, 5079 m/sec, 15765121 t fired, .

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7 CTL EXCL 195/198 5/5 DLCround-PT-04a-CTLFireability-02 1020188 m, 4829 m/sec, 26539672 t fired, .

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7 CTL EXCL 5/198 1/5 DLCround-PT-04a-CTLFireability-02 31736 m, -197690 m/sec, 660233 t fired, .

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7 CTL EXCL 15/198 1/5 DLCround-PT-04a-CTLFireability-02 90966 m, 5791 m/sec, 2059477 t fired, .

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7 CTL EXCL 20/198 1/5 DLCround-PT-04a-CTLFireability-02 120012 m, 5809 m/sec, 2734132 t fired, .

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7 CTL EXCL 45/198 2/5 DLCround-PT-04a-CTLFireability-02 261386 m, 5853 m/sec, 6190080 t fired, .

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7 CTL EXCL 50/198 2/5 DLCround-PT-04a-CTLFireability-02 290288 m, 5780 m/sec, 6883936 t fired, .

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7 CTL EXCL 55/198 2/5 DLCround-PT-04a-CTLFireability-02 317487 m, 5439 m/sec, 7616594 t fired, .

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7 CTL EXCL 60/198 2/5 DLCround-PT-04a-CTLFireability-02 342699 m, 5042 m/sec, 8294623 t fired, .

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7 CTL EXCL 65/198 2/5 DLCround-PT-04a-CTLFireability-02 370099 m, 5480 m/sec, 9028864 t fired, .

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7 CTL EXCL 70/198 2/5 DLCround-PT-04a-CTLFireability-02 396615 m, 5303 m/sec, 9731745 t fired, .

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7 CTL EXCL 75/198 2/5 DLCround-PT-04a-CTLFireability-02 421684 m, 5013 m/sec, 10406909 t fired, .

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7 CTL EXCL 80/198 2/5 DLCround-PT-04a-CTLFireability-02 446268 m, 4916 m/sec, 11079430 t fired, .

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7 CTL EXCL 85/198 2/5 DLCround-PT-04a-CTLFireability-02 473554 m, 5457 m/sec, 11768984 t fired, .

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7 CTL EXCL 90/198 3/5 DLCround-PT-04a-CTLFireability-02 500277 m, 5344 m/sec, 12447703 t fired, .

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7 CTL EXCL 95/198 3/5 DLCround-PT-04a-CTLFireability-02 530274 m, 5999 m/sec, 13089534 t fired, .

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7 CTL EXCL 100/198 3/5 DLCround-PT-04a-CTLFireability-02 555236 m, 4992 m/sec, 13773836 t fired, .

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7 CTL EXCL 115/198 3/5 DLCround-PT-04a-CTLFireability-02 626311 m, 4873 m/sec, 15796745 t fired, .

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7 CTL EXCL 120/198 3/5 DLCround-PT-04a-CTLFireability-02 653070 m, 5351 m/sec, 16502174 t fired, .

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7 CTL EXCL 125/198 3/5 DLCround-PT-04a-CTLFireability-02 678161 m, 5018 m/sec, 17214198 t fired, .

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7 CTL EXCL 130/198 3/5 DLCround-PT-04a-CTLFireability-02 704386 m, 5245 m/sec, 17899297 t fired, .

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7 CTL EXCL 155/198 4/5 DLCround-PT-04a-CTLFireability-02 830838 m, 5366 m/sec, 21247723 t fired, .

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7 CTL EXCL 160/198 4/5 DLCround-PT-04a-CTLFireability-02 856931 m, 5218 m/sec, 21934231 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 186/198 5/5 DLCround-PT-04a-CTLFireability-02 978419 m, 4670 m/sec, 25351734 t fired, .

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7 CTL EXCL 191/198 5/5 DLCround-PT-04a-CTLFireability-02 1002456 m, 4807 m/sec, 26029433 t fired, .

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7 CTL EXCL 196/198 5/5 DLCround-PT-04a-CTLFireability-02 1026898 m, 4888 m/sec, 26740289 t fired, .

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7 CTL EXCL 5/198 1/5 DLCround-PT-04a-CTLFireability-02 31745 m, -199030 m/sec, 660670 t fired, .

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7 CTL EXCL 10/198 1/5 DLCround-PT-04a-CTLFireability-02 61872 m, 6025 m/sec, 1353045 t fired, .

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7 CTL EXCL 15/198 1/5 DLCround-PT-04a-CTLFireability-02 89674 m, 5560 m/sec, 2036755 t fired, .

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7 CTL EXCL 20/198 1/5 DLCround-PT-04a-CTLFireability-02 118902 m, 5845 m/sec, 2716215 t fired, .

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7 CTL EXCL 25/198 1/5 DLCround-PT-04a-CTLFireability-02 147253 m, 5670 m/sec, 3413227 t fired, .

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7 CTL EXCL 30/198 1/5 DLCround-PT-04a-CTLFireability-02 176314 m, 5812 m/sec, 4120689 t fired, .

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7 CTL EXCL 35/198 1/5 DLCround-PT-04a-CTLFireability-02 205489 m, 5835 m/sec, 4815912 t fired, .

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7 CTL EXCL 40/198 1/5 DLCround-PT-04a-CTLFireability-02 232499 m, 5402 m/sec, 5508192 t fired, .

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7 CTL EXCL 45/198 2/5 DLCround-PT-04a-CTLFireability-02 261090 m, 5718 m/sec, 6181172 t fired, .

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7 CTL EXCL 55/198 2/5 DLCround-PT-04a-CTLFireability-02 313771 m, 4825 m/sec, 7537893 t fired, .

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7 CTL EXCL 60/198 2/5 DLCround-PT-04a-CTLFireability-02 340157 m, 5277 m/sec, 8232568 t fired, .

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7 CTL EXCL 65/198 2/5 DLCround-PT-04a-CTLFireability-02 364700 m, 4908 m/sec, 8876202 t fired, .

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7 CTL EXCL 70/198 2/5 DLCround-PT-04a-CTLFireability-02 390100 m, 5080 m/sec, 9547244 t fired, .

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7 CTL EXCL 75/198 2/5 DLCround-PT-04a-CTLFireability-02 417258 m, 5431 m/sec, 10265767 t fired, .

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7 CTL EXCL 80/198 2/5 DLCround-PT-04a-CTLFireability-02 442074 m, 4963 m/sec, 10940472 t fired, .

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7 CTL EXCL 85/198 2/5 DLCround-PT-04a-CTLFireability-02 468233 m, 5231 m/sec, 11662212 t fired, .

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7 CTL EXCL 90/198 3/5 DLCround-PT-04a-CTLFireability-02 497578 m, 5869 m/sec, 12372240 t fired, .

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7 CTL EXCL 95/198 3/5 DLCround-PT-04a-CTLFireability-02 527485 m, 5981 m/sec, 13024399 t fired, .

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7 CTL EXCL 100/198 3/5 DLCround-PT-04a-CTLFireability-02 553488 m, 5200 m/sec, 13729767 t fired, .

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7 CTL EXCL 105/198 3/5 DLCround-PT-04a-CTLFireability-02 577407 m, 4783 m/sec, 14404067 t fired, .

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7 CTL EXCL 110/198 3/5 DLCround-PT-04a-CTLFireability-02 600905 m, 4699 m/sec, 15113172 t fired, .

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7 CTL EXCL 125/198 3/5 DLCround-PT-04a-CTLFireability-02 678261 m, 5082 m/sec, 17215254 t fired, .

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7 CTL EXCL 130/198 3/5 DLCround-PT-04a-CTLFireability-02 704908 m, 5329 m/sec, 17913731 t fired, .

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7 CTL EXCL 135/198 4/5 DLCround-PT-04a-CTLFireability-02 730890 m, 5196 m/sec, 18588659 t fired, .

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7 CTL EXCL 140/198 4/5 DLCround-PT-04a-CTLFireability-02 757387 m, 5299 m/sec, 19266536 t fired, .

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7 CTL EXCL 150/198 4/5 DLCround-PT-04a-CTLFireability-02 805759 m, 4740 m/sec, 20624265 t fired, .

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7 CTL EXCL 155/198 4/5 DLCround-PT-04a-CTLFireability-02 832907 m, 5429 m/sec, 21302636 t fired, .

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7 CTL EXCL 160/198 4/5 DLCround-PT-04a-CTLFireability-02 858487 m, 5116 m/sec, 21983787 t fired, .

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7 CTL EXCL 165/198 4/5 DLCround-PT-04a-CTLFireability-02 883403 m, 4983 m/sec, 22712322 t fired, .

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7 CTL EXCL 170/198 4/5 DLCround-PT-04a-CTLFireability-02 907530 m, 4825 m/sec, 23381830 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 196/198 5/5 DLCround-PT-04a-CTLFireability-02 1029772 m, 4881 m/sec, 26834510 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/2575 1/5 DLCround-PT-04a-CTLFireability-02 21720 m, -201610 m/sec, 443388 t fired, .
32 CTL EXCL 5/198 1/32 DLCround-PT-04a-CTLFireability-09 33842 m, 6768 m/sec, 606489 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/2575 1/5 DLCround-PT-04a-CTLFireability-02 39659 m, 3587 m/sec, 852944 t fired, .
32 CTL EXCL 10/183 1/32 DLCround-PT-04a-CTLFireability-09 68745 m, 6980 m/sec, 1251712 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/2575 1/5 DLCround-PT-04a-CTLFireability-02 58451 m, 3758 m/sec, 1290567 t fired, .
32 CTL EXCL 15/183 1/32 DLCround-PT-04a-CTLFireability-09 101265 m, 6504 m/sec, 1819360 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/2575 1/5 DLCround-PT-04a-CTLFireability-02 72276 m, 2765 m/sec, 1604203 t fired, .
32 CTL EXCL 20/183 1/32 DLCround-PT-04a-CTLFireability-09 137444 m, 7235 m/sec, 2415452 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/2575 1/5 DLCround-PT-04a-CTLFireability-02 92749 m, 4094 m/sec, 2078196 t fired, .
32 CTL EXCL 25/183 1/32 DLCround-PT-04a-CTLFireability-09 157296 m, 3970 m/sec, 2757617 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/2575 1/5 DLCround-PT-04a-CTLFireability-02 110064 m, 3463 m/sec, 2512984 t fired, .
32 CTL EXCL 30/183 1/32 DLCround-PT-04a-CTLFireability-09 175775 m, 3695 m/sec, 3089467 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/2575 1/5 DLCround-PT-04a-CTLFireability-02 128890 m, 3765 m/sec, 2908052 t fired, .
32 CTL EXCL 35/183 1/32 DLCround-PT-04a-CTLFireability-09 194990 m, 3843 m/sec, 3414852 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/2575 1/5 DLCround-PT-04a-CTLFireability-02 145218 m, 3265 m/sec, 3355994 t fired, .
32 CTL EXCL 40/183 1/32 DLCround-PT-04a-CTLFireability-09 214467 m, 3895 m/sec, 3744852 t fired, .

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7 CTL EXCL 45/2575 1/5 DLCround-PT-04a-CTLFireability-02 163586 m, 3673 m/sec, 3820172 t fired, .
32 CTL EXCL 45/183 2/32 DLCround-PT-04a-CTLFireability-09 240881 m, 5282 m/sec, 4184059 t fired, .

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7 CTL EXCL 50/2575 1/5 DLCround-PT-04a-CTLFireability-02 181052 m, 3493 m/sec, 4240060 t fired, .
32 CTL EXCL 50/183 2/32 DLCround-PT-04a-CTLFireability-09 260826 m, 3989 m/sec, 4511034 t fired, .

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7 CTL EXCL 55/2575 1/5 DLCround-PT-04a-CTLFireability-02 198325 m, 3454 m/sec, 4674522 t fired, .
32 CTL EXCL 55/183 2/32 DLCround-PT-04a-CTLFireability-09 284554 m, 4745 m/sec, 4910433 t fired, .

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7 CTL EXCL 60/2575 1/5 DLCround-PT-04a-CTLFireability-02 216577 m, 3650 m/sec, 5128723 t fired, .
32 CTL EXCL 60/183 2/32 DLCround-PT-04a-CTLFireability-09 306404 m, 4370 m/sec, 5294822 t fired, .

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7 CTL EXCL 65/2575 1/5 DLCround-PT-04a-CTLFireability-02 234712 m, 3627 m/sec, 5552176 t fired, .
32 CTL EXCL 65/183 2/32 DLCround-PT-04a-CTLFireability-09 327168 m, 4152 m/sec, 5653476 t fired, .

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7 CTL EXCL 70/2575 2/5 DLCround-PT-04a-CTLFireability-02 250653 m, 3188 m/sec, 5913635 t fired, .
32 CTL EXCL 70/183 2/32 DLCround-PT-04a-CTLFireability-09 346219 m, 3810 m/sec, 5979890 t fired, .

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7 CTL EXCL 75/2575 2/5 DLCround-PT-04a-CTLFireability-02 269607 m, 3790 m/sec, 6406057 t fired, .
32 CTL EXCL 75/183 2/32 DLCround-PT-04a-CTLFireability-09 365038 m, 3763 m/sec, 6308276 t fired, .

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7 CTL EXCL 80/2575 2/5 DLCround-PT-04a-CTLFireability-02 285806 m, 3239 m/sec, 6812677 t fired, .
32 CTL EXCL 80/183 2/32 DLCround-PT-04a-CTLFireability-09 384765 m, 3945 m/sec, 6659814 t fired, .

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7 CTL EXCL 85/2575 2/5 DLCround-PT-04a-CTLFireability-02 302603 m, 3359 m/sec, 7238578 t fired, .
32 CTL EXCL 85/183 2/32 DLCround-PT-04a-CTLFireability-09 408632 m, 4773 m/sec, 7088950 t fired, .

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7 CTL EXCL 90/2575 2/5 DLCround-PT-04a-CTLFireability-02 320814 m, 3642 m/sec, 7681876 t fired, .
32 CTL EXCL 90/183 2/32 DLCround-PT-04a-CTLFireability-09 429795 m, 4232 m/sec, 7467394 t fired, .

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7 CTL EXCL 95/2575 2/5 DLCround-PT-04a-CTLFireability-02 336254 m, 3088 m/sec, 8130843 t fired, .
32 CTL EXCL 95/183 2/32 DLCround-PT-04a-CTLFireability-09 445985 m, 3238 m/sec, 7763423 t fired, .

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32 CTL EXCL 100/183 2/32 DLCround-PT-04a-CTLFireability-09 467243 m, 4251 m/sec, 8133551 t fired, .

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7 CTL EXCL 105/2575 2/5 DLCround-PT-04a-CTLFireability-02 369714 m, 3573 m/sec, 9017294 t fired, .
32 CTL EXCL 105/183 3/32 DLCround-PT-04a-CTLFireability-09 492720 m, 5095 m/sec, 8584184 t fired, .

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7 CTL EXCL 110/2575 2/5 DLCround-PT-04a-CTLFireability-02 383186 m, 2694 m/sec, 9365407 t fired, .
32 CTL EXCL 110/183 3/32 DLCround-PT-04a-CTLFireability-09 514126 m, 4281 m/sec, 8972621 t fired, .

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7 CTL EXCL 115/2575 2/5 DLCround-PT-04a-CTLFireability-02 401824 m, 3727 m/sec, 9855329 t fired, .
32 CTL EXCL 115/183 3/32 DLCround-PT-04a-CTLFireability-09 534030 m, 3980 m/sec, 9343913 t fired, .

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7 CTL EXCL 125/2575 2/5 DLCround-PT-04a-CTLFireability-02 437374 m, 3605 m/sec, 10814106 t fired, .
32 CTL EXCL 125/183 3/32 DLCround-PT-04a-CTLFireability-09 579126 m, 4603 m/sec, 10191351 t fired, .

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7 CTL EXCL 130/2575 2/5 DLCround-PT-04a-CTLFireability-02 454864 m, 3498 m/sec, 11330831 t fired, .
32 CTL EXCL 130/183 3/32 DLCround-PT-04a-CTLFireability-09 598747 m, 3924 m/sec, 10561450 t fired, .

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7 CTL EXCL 135/2575 2/5 DLCround-PT-04a-CTLFireability-02 473722 m, 3771 m/sec, 11773589 t fired, .
32 CTL EXCL 135/183 3/32 DLCround-PT-04a-CTLFireability-09 614679 m, 3186 m/sec, 10824923 t fired, .

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7 CTL EXCL 140/2575 3/5 DLCround-PT-04a-CTLFireability-02 493013 m, 3858 m/sec, 12250743 t fired, .
32 CTL EXCL 140/183 3/32 DLCround-PT-04a-CTLFireability-09 640268 m, 5117 m/sec, 11287172 t fired, .

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7 CTL EXCL 145/2575 3/5 DLCround-PT-04a-CTLFireability-02 507642 m, 2925 m/sec, 12639461 t fired, .
32 CTL EXCL 145/183 3/32 DLCround-PT-04a-CTLFireability-09 670642 m, 6074 m/sec, 11821082 t fired, .

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7 CTL EXCL 150/2575 3/5 DLCround-PT-04a-CTLFireability-02 527502 m, 3972 m/sec, 13024639 t fired, .
32 CTL EXCL 150/183 3/32 DLCround-PT-04a-CTLFireability-09 689846 m, 3840 m/sec, 12165979 t fired, .

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7 CTL EXCL 155/2575 3/5 DLCround-PT-04a-CTLFireability-02 544041 m, 3307 m/sec, 13438185 t fired, .
32 CTL EXCL 155/183 3/32 DLCround-PT-04a-CTLFireability-09 711465 m, 4323 m/sec, 12559271 t fired, .

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7 CTL EXCL 160/2575 3/5 DLCround-PT-04a-CTLFireability-02 555468 m, 2285 m/sec, 13781404 t fired, .
32 CTL EXCL 160/183 4/32 DLCround-PT-04a-CTLFireability-09 730295 m, 3766 m/sec, 12894383 t fired, .

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7 CTL EXCL 165/2575 3/5 DLCround-PT-04a-CTLFireability-02 568249 m, 2556 m/sec, 14135913 t fired, .
32 CTL EXCL 165/183 4/32 DLCround-PT-04a-CTLFireability-09 746875 m, 3316 m/sec, 13212321 t fired, .

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7 CTL EXCL 170/2575 3/5 DLCround-PT-04a-CTLFireability-02 585444 m, 3439 m/sec, 14639590 t fired, .
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7 CTL EXCL 175/2575 3/5 DLCround-PT-04a-CTLFireability-02 602127 m, 3336 m/sec, 15154653 t fired, .
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7 CTL EXCL 180/2575 3/5 DLCround-PT-04a-CTLFireability-02 617984 m, 3171 m/sec, 15564639 t fired, .
32 CTL EXCL 180/183 4/32 DLCround-PT-04a-CTLFireability-09 815280 m, 4153 m/sec, 14422168 t fired, .

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7 CTL EXCL 190/198 3/5 DLCround-PT-04a-CTLFireability-02 656535 m, 3415 m/sec, 16609504 t fired, .
32 CTL EXCL 4/2390 1/5 DLCround-PT-04a-CTLFireability-09 14398 m, -160176 m/sec, 264956 t fired, .

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7 CTL EXCL 195/198 3/5 DLCround-PT-04a-CTLFireability-02 670997 m, 2892 m/sec, 17021819 t fired, .
32 CTL EXCL 9/170 1/5 DLCround-PT-04a-CTLFireability-09 33724 m, 3865 m/sec, 604756 t fired, .

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32 CTL EXCL 14/170 1/5 DLCround-PT-04a-CTLFireability-09 43526 m, 1960 m/sec, 784095 t fired, .

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7 CTL EXCL 4/2375 1/5 DLCround-PT-04a-CTLFireability-02 11367 m, -131926 m/sec, 223351 t fired, .
32 CTL EXCL 19/183 1/5 DLCround-PT-04a-CTLFireability-09 51961 m, 1687 m/sec, 937291 t fired, .

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7 CTL EXCL 9/2375 1/5 DLCround-PT-04a-CTLFireability-02 26866 m, 3099 m/sec, 558255 t fired, .
32 CTL EXCL 24/170 1/5 DLCround-PT-04a-CTLFireability-09 68922 m, 3392 m/sec, 1254883 t fired, .

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7 CTL EXCL 14/2375 1/5 DLCround-PT-04a-CTLFireability-02 43055 m, 3237 m/sec, 930670 t fired, .
32 CTL EXCL 29/170 1/5 DLCround-PT-04a-CTLFireability-09 82275 m, 2670 m/sec, 1485677 t fired, .

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7 CTL EXCL 19/2375 1/5 DLCround-PT-04a-CTLFireability-02 57218 m, 2832 m/sec, 1255998 t fired, .
32 CTL EXCL 34/170 1/5 DLCround-PT-04a-CTLFireability-09 96266 m, 2798 m/sec, 1744490 t fired, .

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7 CTL EXCL 24/2375 1/5 DLCround-PT-04a-CTLFireability-02 72276 m, 3011 m/sec, 1604203 t fired, .
32 CTL EXCL 39/170 1/5 DLCround-PT-04a-CTLFireability-09 109096 m, 2566 m/sec, 1955210 t fired, .

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7 CTL EXCL 29/2375 1/5 DLCround-PT-04a-CTLFireability-02 85035 m, 2551 m/sec, 1917735 t fired, .
32 CTL EXCL 44/170 1/5 DLCround-PT-04a-CTLFireability-09 120874 m, 2355 m/sec, 2149922 t fired, .

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32 CTL EXCL 49/170 1/5 DLCround-PT-04a-CTLFireability-09 126828 m, 1190 m/sec, 2255324 t fired, .

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32 CTL EXCL 54/170 1/5 DLCround-PT-04a-CTLFireability-09 147502 m, 4134 m/sec, 2587712 t fired, .

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32 CTL EXCL 59/170 1/5 DLCround-PT-04a-CTLFireability-09 157468 m, 1993 m/sec, 2760785 t fired, .

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32 CTL EXCL 64/170 1/5 DLCround-PT-04a-CTLFireability-09 170072 m, 2520 m/sec, 2979594 t fired, .

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7 CTL EXCL 54/2375 1/5 DLCround-PT-04a-CTLFireability-02 142283 m, 2058 m/sec, 3279318 t fired, .
32 CTL EXCL 69/170 1/5 DLCround-PT-04a-CTLFireability-09 176551 m, 1295 m/sec, 3104393 t fired, .

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7 CTL EXCL 59/2375 1/5 DLCround-PT-04a-CTLFireability-02 150502 m, 1643 m/sec, 3488148 t fired, .
32 CTL EXCL 74/170 1/5 DLCround-PT-04a-CTLFireability-09 183109 m, 1311 m/sec, 3219742 t fired, .

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7 CTL EXCL 64/2375 1/5 DLCround-PT-04a-CTLFireability-02 159088 m, 1717 m/sec, 3715837 t fired, .
32 CTL EXCL 79/170 1/5 DLCround-PT-04a-CTLFireability-09 189876 m, 1353 m/sec, 3331872 t fired, .

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7 CTL EXCL 69/2375 1/5 DLCround-PT-04a-CTLFireability-02 169159 m, 2014 m/sec, 3942927 t fired, .
32 CTL EXCL 84/170 1/5 DLCround-PT-04a-CTLFireability-09 196508 m, 1326 m/sec, 3444720 t fired, .

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7 CTL EXCL 74/2375 1/5 DLCround-PT-04a-CTLFireability-02 179600 m, 2088 m/sec, 4205874 t fired, .
32 CTL EXCL 89/170 1/5 DLCround-PT-04a-CTLFireability-09 204404 m, 1579 m/sec, 3586380 t fired, .

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7 CTL EXCL 79/2375 1/5 DLCround-PT-04a-CTLFireability-02 192379 m, 2555 m/sec, 4520460 t fired, .
32 CTL EXCL 94/170 1/5 DLCround-PT-04a-CTLFireability-09 214788 m, 2076 m/sec, 3751575 t fired, .

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7 CTL EXCL 84/2375 1/5 DLCround-PT-04a-CTLFireability-02 205984 m, 2721 m/sec, 4830974 t fired, .
32 CTL EXCL 99/170 1/5 DLCround-PT-04a-CTLFireability-09 233056 m, 3653 m/sec, 4057444 t fired, .

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7 CTL EXCL 89/2375 1/5 DLCround-PT-04a-CTLFireability-02 218086 m, 2420 m/sec, 5176034 t fired, .
32 CTL EXCL 104/170 2/5 DLCround-PT-04a-CTLFireability-09 253074 m, 4003 m/sec, 4391656 t fired, .

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32 CTL EXCL 109/170 2/5 DLCround-PT-04a-CTLFireability-09 264081 m, 2201 m/sec, 4571570 t fired, .

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32 CTL EXCL 115/170 2/5 DLCround-PT-04a-CTLFireability-09 272929 m, 1769 m/sec, 4721177 t fired, .

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32 CTL EXCL 120/170 2/5 DLCround-PT-04a-CTLFireability-09 283103 m, 2034 m/sec, 4889524 t fired, .

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7 CTL EXCL 120/2375 2/5 DLCround-PT-04a-CTLFireability-02 290680 m, 2622 m/sec, 6894544 t fired, .
32 CTL EXCL 135/170 2/5 DLCround-PT-04a-CTLFireability-09 313587 m, 1387 m/sec, 5410650 t fired, .

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7 CTL EXCL 125/2375 2/5 DLCround-PT-04a-CTLFireability-02 301168 m, 2097 m/sec, 7194392 t fired, .
32 CTL EXCL 140/170 2/5 DLCround-PT-04a-CTLFireability-09 318949 m, 1072 m/sec, 5505647 t fired, .

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7 CTL EXCL 130/2375 2/5 DLCround-PT-04a-CTLFireability-02 312366 m, 2239 m/sec, 7501936 t fired, .
32 CTL EXCL 145/170 2/5 DLCround-PT-04a-CTLFireability-09 324796 m, 1169 m/sec, 5607356 t fired, .

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7 CTL EXCL 135/2375 2/5 DLCround-PT-04a-CTLFireability-02 322448 m, 2016 m/sec, 7746760 t fired, .
32 CTL EXCL 150/170 2/5 DLCround-PT-04a-CTLFireability-09 333920 m, 1824 m/sec, 5769543 t fired, .

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7 CTL EXCL 140/2375 2/5 DLCround-PT-04a-CTLFireability-02 332862 m, 2082 m/sec, 8035762 t fired, .
32 CTL EXCL 155/170 2/5 DLCround-PT-04a-CTLFireability-09 344934 m, 2202 m/sec, 5958776 t fired, .

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7 CTL EXCL 145/2375 2/5 DLCround-PT-04a-CTLFireability-02 343130 m, 2053 m/sec, 8312219 t fired, .
32 CTL EXCL 160/170 2/5 DLCround-PT-04a-CTLFireability-09 353082 m, 1629 m/sec, 6095774 t fired, .

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7 CTL EXCL 150/2375 2/5 DLCround-PT-04a-CTLFireability-02 352703 m, 1914 m/sec, 8582740 t fired, .
32 CTL EXCL 165/170 2/5 DLCround-PT-04a-CTLFireability-09 358816 m, 1146 m/sec, 6196922 t fired, .

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7 CTL EXCL 155/2375 2/5 DLCround-PT-04a-CTLFireability-02 364994 m, 2458 m/sec, 8883256 t fired, .
32 CTL EXCL 170/170 2/5 DLCround-PT-04a-CTLFireability-09 371090 m, 2454 m/sec, 6414630 t fired, .

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7 CTL EXCL 160/2375 2/5 DLCround-PT-04a-CTLFireability-02 376042 m, 2209 m/sec, 9162439 t fired, .

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7 CTL EXCL 165/182 2/5 DLCround-PT-04a-CTLFireability-02 384294 m, 1650 m/sec, 9427550 t fired, .
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32 CTL EXCL 21/157 1/5 DLCround-PT-04a-CTLFireability-09 34338 m, 1193 m/sec, 613511 t fired, .

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7 CTL EXCL 0/2189 1/5 DLCround-PT-04a-CTLFireability-02 308 m, -82540 m/sec, 4279 t fired, .
32 CTL EXCL 27/170 1/5 DLCround-PT-04a-CTLFireability-09 41335 m, 1399 m/sec, 742196 t fired, .

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7 CTL EXCL 5/2189 1/5 DLCround-PT-04a-CTLFireability-02 11131 m, 2164 m/sec, 221161 t fired, .
32 CTL EXCL 32/157 1/5 DLCround-PT-04a-CTLFireability-09 45591 m, 851 m/sec, 822380 t fired, .

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7 CTL EXCL 10/2189 1/5 DLCround-PT-04a-CTLFireability-02 21016 m, 1977 m/sec, 427934 t fired, .
32 CTL EXCL 37/157 1/5 DLCround-PT-04a-CTLFireability-09 51652 m, 1212 m/sec, 931614 t fired, .

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32 CTL EXCL 42/157 1/5 DLCround-PT-04a-CTLFireability-09 54798 m, 629 m/sec, 990663 t fired, .

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32 CTL EXCL 47/157 1/5 DLCround-PT-04a-CTLFireability-09 61532 m, 1346 m/sec, 1115440 t fired, .

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7 CTL EXCL 25/2189 1/5 DLCround-PT-04a-CTLFireability-02 52087 m, 2008 m/sec, 1129347 t fired, .
32 CTL EXCL 52/157 1/5 DLCround-PT-04a-CTLFireability-09 64877 m, 669 m/sec, 1178166 t fired, .

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7 CTL EXCL 30/2189 1/5 DLCround-PT-04a-CTLFireability-02 61386 m, 1859 m/sec, 1338889 t fired, .
32 CTL EXCL 57/157 1/5 DLCround-PT-04a-CTLFireability-09 69082 m, 841 m/sec, 1257817 t fired, .

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32 CTL EXCL 62/157 1/5 DLCround-PT-04a-CTLFireability-09 73693 m, 922 m/sec, 1337687 t fired, .

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32 CTL EXCL 67/157 1/5 DLCround-PT-04a-CTLFireability-09 77287 m, 718 m/sec, 1401428 t fired, .

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32 CTL EXCL 82/157 1/5 DLCround-PT-04a-CTLFireability-09 90973 m, 754 m/sec, 1650845 t fired, .

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7 CTL EXCL 60/2189 1/5 DLCround-PT-04a-CTLFireability-02 108317 m, 1947 m/sec, 2473033 t fired, .
32 CTL EXCL 87/157 1/5 DLCround-PT-04a-CTLFireability-09 102901 m, 2385 m/sec, 1843768 t fired, .

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7 CTL EXCL 65/2189 1/5 DLCround-PT-04a-CTLFireability-02 117760 m, 1888 m/sec, 2689631 t fired, .
32 CTL EXCL 92/157 1/5 DLCround-PT-04a-CTLFireability-09 107256 m, 871 m/sec, 1921234 t fired, .

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7 CTL EXCL 70/2189 1/5 DLCround-PT-04a-CTLFireability-02 127875 m, 2023 m/sec, 2884202 t fired, .
32 CTL EXCL 97/157 1/5 DLCround-PT-04a-CTLFireability-09 113610 m, 1270 m/sec, 2023767 t fired, .

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7 CTL EXCL 75/2189 1/5 DLCround-PT-04a-CTLFireability-02 136317 m, 1688 m/sec, 3097421 t fired, .
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7 CTL EXCL 80/2189 1/5 DLCround-PT-04a-CTLFireability-02 143687 m, 1474 m/sec, 3321502 t fired, .
32 CTL EXCL 107/157 1/5 DLCround-PT-04a-CTLFireability-09 122633 m, 960 m/sec, 2178896 t fired, .

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7 CTL EXCL 85/2189 1/5 DLCround-PT-04a-CTLFireability-02 151845 m, 1631 m/sec, 3517957 t fired, .
32 CTL EXCL 112/157 1/5 DLCround-PT-04a-CTLFireability-09 126946 m, 862 m/sec, 2257372 t fired, .

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7 CTL EXCL 90/2189 1/5 DLCround-PT-04a-CTLFireability-02 158337 m, 1298 m/sec, 3693373 t fired, .
32 CTL EXCL 117/157 1/5 DLCround-PT-04a-CTLFireability-09 133095 m, 1229 m/sec, 2347185 t fired, .

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7 CTL EXCL 95/2189 1/5 DLCround-PT-04a-CTLFireability-02 166459 m, 1624 m/sec, 3880440 t fired, .
32 CTL EXCL 122/157 1/5 DLCround-PT-04a-CTLFireability-09 139952 m, 1371 m/sec, 2458187 t fired, .

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32 CTL EXCL 127/157 1/5 DLCround-PT-04a-CTLFireability-09 148919 m, 1793 m/sec, 2609763 t fired, .

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7 CTL EXCL 130/2189 1/5 DLCround-PT-04a-CTLFireability-02 222886 m, 1356 m/sec, 5309704 t fired, .
32 CTL EXCL 157/157 1/5 DLCround-PT-04a-CTLFireability-09 176599 m, 815 m/sec, 3105250 t fired, .

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7 CTL EXCL 135/2189 1/5 DLCround-PT-04a-CTLFireability-02 233145 m, 2051 m/sec, 5529742 t fired, .

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7 CTL EXCL 147/167 2/5 DLCround-PT-04a-CTLFireability-02 240426 m, 1456 m/sec, 5707894 t fired, .
32 CTL EXCL 0/2048 1/5 DLCround-PT-04a-CTLFireability-09 367 m, -35246 m/sec, 6440 t fired, .

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32 CTL EXCL 5/145 1/5 DLCround-PT-04a-CTLFireability-09 5417 m, 1010 m/sec, 99210 t fired, .

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32 CTL EXCL 10/145 1/5 DLCround-PT-04a-CTLFireability-09 9840 m, 884 m/sec, 180774 t fired, .

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7 CTL EXCL 162/167 2/5 DLCround-PT-04a-CTLFireability-02 264135 m, 1534 m/sec, 6259011 t fired, .
32 CTL EXCL 15/145 1/5 DLCround-PT-04a-CTLFireability-09 14381 m, 908 m/sec, 264680 t fired, .

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7 CTL EXCL 167/167 2/5 DLCround-PT-04a-CTLFireability-02 271460 m, 1465 m/sec, 6450570 t fired, .
32 CTL EXCL 20/145 1/5 DLCround-PT-04a-CTLFireability-09 18361 m, 796 m/sec, 338762 t fired, .

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32 CTL EXCL 25/145 1/5 DLCround-PT-04a-CTLFireability-09 22745 m, 876 m/sec, 418799 t fired, .

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7 CTL EXCL 0/2011 1/5 DLCround-PT-04a-CTLFireability-02 241 m, -54243 m/sec, 2087 t fired, .
32 CTL EXCL 57/156 1/5 DLCround-PT-04a-CTLFireability-09 59915 m, 7434 m/sec, 1086261 t fired, .

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7 CTL EXCL 5/2011 1/5 DLCround-PT-04a-CTLFireability-02 7235 m, 1398 m/sec, 152698 t fired, .
32 CTL EXCL 62/145 1/5 DLCround-PT-04a-CTLFireability-09 64268 m, 870 m/sec, 1166410 t fired, .

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32 CTL EXCL 67/145 1/5 DLCround-PT-04a-CTLFireability-09 68030 m, 752 m/sec, 1238752 t fired, .

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7 CTL EXCL 20/2011 1/5 DLCround-PT-04a-CTLFireability-02 33532 m, 1745 m/sec, 704048 t fired, .
32 CTL EXCL 77/145 1/5 DLCround-PT-04a-CTLFireability-09 75715 m, 662 m/sec, 1376593 t fired, .

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7 CTL EXCL 25/2011 1/5 DLCround-PT-04a-CTLFireability-02 39747 m, 1243 m/sec, 855256 t fired, .
32 CTL EXCL 82/145 1/5 DLCround-PT-04a-CTLFireability-09 79974 m, 851 m/sec, 1441584 t fired, .

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7 CTL EXCL 30/2011 1/5 DLCround-PT-04a-CTLFireability-02 45542 m, 1159 m/sec, 985313 t fired, .
32 CTL EXCL 87/145 1/5 DLCround-PT-04a-CTLFireability-09 83566 m, 718 m/sec, 1509505 t fired, .

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7 CTL EXCL 35/2011 1/5 DLCround-PT-04a-CTLFireability-02 52402 m, 1372 m/sec, 1141892 t fired, .
32 CTL EXCL 92/145 1/5 DLCround-PT-04a-CTLFireability-09 86341 m, 555 m/sec, 1560844 t fired, .

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7 CTL EXCL 40/2011 1/5 DLCround-PT-04a-CTLFireability-02 60462 m, 1612 m/sec, 1317104 t fired, .
32 CTL EXCL 97/145 1/5 DLCround-PT-04a-CTLFireability-09 90217 m, 775 m/sec, 1635690 t fired, .

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7 CTL EXCL 45/2011 1/5 DLCround-PT-04a-CTLFireability-02 67886 m, 1484 m/sec, 1499638 t fired, .
32 CTL EXCL 102/145 1/5 DLCround-PT-04a-CTLFireability-09 93792 m, 715 m/sec, 1698625 t fired, .

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7 CTL EXCL 50/2011 1/5 DLCround-PT-04a-CTLFireability-02 73939 m, 1210 m/sec, 1656702 t fired, .
32 CTL EXCL 107/145 1/5 DLCround-PT-04a-CTLFireability-09 97508 m, 743 m/sec, 1762943 t fired, .

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7 CTL EXCL 55/2011 1/5 DLCround-PT-04a-CTLFireability-02 80627 m, 1337 m/sec, 1799412 t fired, .
32 CTL EXCL 112/145 1/5 DLCround-PT-04a-CTLFireability-09 102336 m, 965 m/sec, 1835092 t fired, .

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7 CTL EXCL 60/2011 1/5 DLCround-PT-04a-CTLFireability-02 86133 m, 1101 m/sec, 1951785 t fired, .
32 CTL EXCL 117/145 1/5 DLCround-PT-04a-CTLFireability-09 106559 m, 844 m/sec, 1908042 t fired, .

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32 CTL EXCL 122/145 1/5 DLCround-PT-04a-CTLFireability-09 110491 m, 786 m/sec, 1978552 t fired, .

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32 CTL EXCL 127/145 1/5 DLCround-PT-04a-CTLFireability-09 114522 m, 806 m/sec, 2041608 t fired, .

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32 CTL EXCL 132/145 1/5 DLCround-PT-04a-CTLFireability-09 118422 m, 780 m/sec, 2112681 t fired, .

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32 CTL EXCL 137/145 1/5 DLCround-PT-04a-CTLFireability-09 123104 m, 936 m/sec, 2187988 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 85/2011 1/5 DLCround-PT-04a-CTLFireability-02 124534 m, 1688 m/sec, 2794437 t fired, .
32 CTL EXCL 142/145 1/5 DLCround-PT-04a-CTLFireability-09 126725 m, 724 m/sec, 2253332 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 90/2011 1/5 DLCround-PT-04a-CTLFireability-02 131659 m, 1425 m/sec, 2980811 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 151/152 1/5 DLCround-PT-04a-CTLFireability-02 230493 m, 19766 m/sec, 5455497 t fired, .
32 CTL EXCL 0/1889 1/5 DLCround-PT-04a-CTLFireability-09 299 m, -25285 m/sec, 5279 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/130 1/5 DLCround-PT-04a-CTLFireability-09 3603 m, 660 m/sec, 65864 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 0/1823 1/5 DLCround-PT-04a-CTLFireability-02 281 m, -46042 m/sec, 3230 t fired, .
32 CTL EXCL 46/140 1/5 DLCround-PT-04a-CTLFireability-09 42990 m, 7877 m/sec, 774412 t fired, .

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7 CTL EXCL 5/1823 1/5 DLCround-PT-04a-CTLFireability-02 6085 m, 1160 m/sec, 120088 t fired, .
32 CTL EXCL 51/130 1/5 DLCround-PT-04a-CTLFireability-09 46638 m, 729 m/sec, 841444 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/1823 1/5 DLCround-PT-04a-CTLFireability-02 13110 m, 1405 m/sec, 260062 t fired, .
32 CTL EXCL 56/130 1/5 DLCround-PT-04a-CTLFireability-09 50324 m, 737 m/sec, 907359 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/1823 1/5 DLCround-PT-04a-CTLFireability-02 18354 m, 1048 m/sec, 378853 t fired, .
32 CTL EXCL 61/130 1/5 DLCround-PT-04a-CTLFireability-09 53637 m, 662 m/sec, 968730 t fired, .

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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-04a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCround-PT-04a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393000290"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-04a.tgz
mv DLCround-PT-04a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;