fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r061-tall-162038393000274
Last Updated
Jun 28, 2021

About the Execution of LoLA for DLCround-PT-03a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16241.256 3197885.00 10120464.00 10206.50 ?TF???TT?TF?FFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r061-tall-162038393000274.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCround-PT-03a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4

Run identifier is r061-tall-162038393000274
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 152K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.6K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 78K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Mar 23 07:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K Mar 23 07:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Mar 22 15:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 22 15:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 4 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 148K May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-03a-CTLFireability-00
FORMULA_NAME DLCround-PT-03a-CTLFireability-01
FORMULA_NAME DLCround-PT-03a-CTLFireability-02
FORMULA_NAME DLCround-PT-03a-CTLFireability-03
FORMULA_NAME DLCround-PT-03a-CTLFireability-04
FORMULA_NAME DLCround-PT-03a-CTLFireability-05
FORMULA_NAME DLCround-PT-03a-CTLFireability-06
FORMULA_NAME DLCround-PT-03a-CTLFireability-07
FORMULA_NAME DLCround-PT-03a-CTLFireability-08
FORMULA_NAME DLCround-PT-03a-CTLFireability-09
FORMULA_NAME DLCround-PT-03a-CTLFireability-10
FORMULA_NAME DLCround-PT-03a-CTLFireability-11
FORMULA_NAME DLCround-PT-03a-CTLFireability-12
FORMULA_NAME DLCround-PT-03a-CTLFireability-13
FORMULA_NAME DLCround-PT-03a-CTLFireability-14
FORMULA_NAME DLCround-PT-03a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1620767593147

starting LoLA
BK_INPUT DLCround-PT-03a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCround-PT-03a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620770791032

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-03a-CTLFireability-01
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 48 (type FNDP) for 42 DLCround-PT-03a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 42 DLCround-PT-03a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 42 DLCround-PT-03a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 51 (type SRCH) for DLCround-PT-03a-CTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 48 (type FNDP) for DLCround-PT-03a-CTLFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: try reading problem file /home/mcc/execution/CTLFireability-49.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 49 (type EQUN) for DLCround-PT-03a-CTLFireability-14 (obsolete)
lola: FINISHED task # 49 (type EQUN) for DLCround-PT-03a-CTLFireability-14
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03a-CTLFireability-14: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: AGEF 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 AGEF EXCL 3/239 1/32 DLCround-PT-03a-CTLFireability-01 26517 m, 5303 m/sec, 417722 t fired, .

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DLCround-PT-03a-CTLFireability-01: AGEF 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-03a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 AGEF EXCL 8/239 1/32 DLCround-PT-03a-CTLFireability-01 72368 m, 9170 m/sec, 1133705 t fired, .

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DLCround-PT-03a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: AGEF 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 AGEF EXCL 13/239 1/32 DLCround-PT-03a-CTLFireability-01 129030 m, 11332 m/sec, 2040468 t fired, .

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DLCround-PT-03a-CTLFireability-01: AGEF 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-03a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 AGEF EXCL 18/239 1/32 DLCround-PT-03a-CTLFireability-01 174205 m, 9035 m/sec, 2774530 t fired, .

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DLCround-PT-03a-CTLFireability-01: AGEF 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-03a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 AGEF EXCL 23/239 1/32 DLCround-PT-03a-CTLFireability-01 216446 m, 8448 m/sec, 3498232 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: AGEF 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-03a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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4 AGEF EXCL 28/239 1/32 DLCround-PT-03a-CTLFireability-01 259779 m, 8666 m/sec, 4236155 t fired, .

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4 AGEF EXCL 33/239 2/32 DLCround-PT-03a-CTLFireability-01 302033 m, 8450 m/sec, 4964360 t fired, .

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4 AGEF EXCL 38/239 2/32 DLCround-PT-03a-CTLFireability-01 341601 m, 7913 m/sec, 5655001 t fired, .

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4 AGEF EXCL 43/239 2/32 DLCround-PT-03a-CTLFireability-01 381863 m, 8052 m/sec, 6350536 t fired, .

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4 AGEF EXCL 48/239 2/32 DLCround-PT-03a-CTLFireability-01 431710 m, 9969 m/sec, 7157294 t fired, .

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4 AGEF EXCL 53/239 2/32 DLCround-PT-03a-CTLFireability-01 473783 m, 8414 m/sec, 7859234 t fired, .

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4 AGEF EXCL 58/239 2/32 DLCround-PT-03a-CTLFireability-01 521488 m, 9541 m/sec, 8621829 t fired, .

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4 AGEF EXCL 63/239 3/32 DLCround-PT-03a-CTLFireability-01 562091 m, 8120 m/sec, 9335788 t fired, .

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4 AGEF EXCL 68/239 3/32 DLCround-PT-03a-CTLFireability-01 602281 m, 8038 m/sec, 10018134 t fired, .

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4 AGEF EXCL 73/239 3/32 DLCround-PT-03a-CTLFireability-01 645932 m, 8730 m/sec, 10745865 t fired, .

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4 AGEF EXCL 78/239 3/32 DLCround-PT-03a-CTLFireability-01 684981 m, 7809 m/sec, 11421168 t fired, .

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4 AGEF EXCL 83/239 3/32 DLCround-PT-03a-CTLFireability-01 725266 m, 8057 m/sec, 12123191 t fired, .

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4 AGEF EXCL 93/239 4/32 DLCround-PT-03a-CTLFireability-01 804925 m, 8338 m/sec, 13486734 t fired, .

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4 AGEF EXCL 98/239 4/32 DLCround-PT-03a-CTLFireability-01 846226 m, 8260 m/sec, 14178642 t fired, .

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4 AGEF EXCL 103/239 4/32 DLCround-PT-03a-CTLFireability-01 885473 m, 7849 m/sec, 14865680 t fired, .

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4 AGEF EXCL 108/239 4/32 DLCround-PT-03a-CTLFireability-01 923630 m, 7631 m/sec, 15529568 t fired, .

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4 AGEF EXCL 113/239 4/32 DLCround-PT-03a-CTLFireability-01 960194 m, 7312 m/sec, 16172718 t fired, .

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4 AGEF EXCL 118/239 4/32 DLCround-PT-03a-CTLFireability-01 998982 m, 7757 m/sec, 16845591 t fired, .

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4 AGEF EXCL 123/239 4/32 DLCround-PT-03a-CTLFireability-01 1038666 m, 7936 m/sec, 17537299 t fired, .

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4 AGEF EXCL 128/239 5/32 DLCround-PT-03a-CTLFireability-01 1080031 m, 8273 m/sec, 18256557 t fired, .

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4 AGEF EXCL 133/239 5/32 DLCround-PT-03a-CTLFireability-01 1116266 m, 7247 m/sec, 18911460 t fired, .

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4 AGEF EXCL 138/239 5/32 DLCround-PT-03a-CTLFireability-01 1150892 m, 6925 m/sec, 19540020 t fired, .

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4 AGEF EXCL 143/239 5/32 DLCround-PT-03a-CTLFireability-01 1188218 m, 7465 m/sec, 20196621 t fired, .

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4 AGEF EXCL 148/239 5/32 DLCround-PT-03a-CTLFireability-01 1226754 m, 7707 m/sec, 20852754 t fired, .

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4 AGEF EXCL 168/239 6/32 DLCround-PT-03a-CTLFireability-01 1375350 m, 7119 m/sec, 23516253 t fired, .

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4 AGEF EXCL 173/239 6/32 DLCround-PT-03a-CTLFireability-01 1413652 m, 7660 m/sec, 24207763 t fired, .

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4 AGEF EXCL 178/239 6/32 DLCround-PT-03a-CTLFireability-01 1449819 m, 7233 m/sec, 24853150 t fired, .

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4 AGEF EXCL 183/239 6/32 DLCround-PT-03a-CTLFireability-01 1485652 m, 7166 m/sec, 25494357 t fired, .

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4 AGEF EXCL 188/239 6/32 DLCround-PT-03a-CTLFireability-01 1526643 m, 8198 m/sec, 26233164 t fired, .

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4 AGEF EXCL 193/239 6/32 DLCround-PT-03a-CTLFireability-01 1562185 m, 7108 m/sec, 26878038 t fired, .

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4 AGEF EXCL 198/239 7/32 DLCround-PT-03a-CTLFireability-01 1597632 m, 7089 m/sec, 27535128 t fired, .

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4 AGEF EXCL 203/239 7/32 DLCround-PT-03a-CTLFireability-01 1636873 m, 7848 m/sec, 28250208 t fired, .

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4 AGEF EXCL 208/239 7/32 DLCround-PT-03a-CTLFireability-01 1671554 m, 6936 m/sec, 28881688 t fired, .

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4 AGEF EXCL 238/239 8/32 DLCround-PT-03a-CTLFireability-01 1886721 m, 7237 m/sec, 32785321 t fired, .

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4 AGEF EXCL 5/239 1/5 DLCround-PT-03a-CTLFireability-01 56704 m, -366003 m/sec, 878234 t fired, .

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4 AGEF EXCL 10/239 1/5 DLCround-PT-03a-CTLFireability-01 105105 m, 9680 m/sec, 1659676 t fired, .

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4 AGEF EXCL 15/239 1/5 DLCround-PT-03a-CTLFireability-01 153949 m, 9768 m/sec, 2436517 t fired, .

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4 AGEF EXCL 20/239 1/5 DLCround-PT-03a-CTLFireability-01 198015 m, 8813 m/sec, 3178405 t fired, .

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4 AGEF EXCL 36/239 2/5 DLCround-PT-03a-CTLFireability-01 324271 m, 8115 m/sec, 5343589 t fired, .

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4 AGEF EXCL 66/239 3/5 DLCround-PT-03a-CTLFireability-01 581244 m, 7722 m/sec, 9665214 t fired, .

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4 AGEF EXCL 136/239 5/5 DLCround-PT-03a-CTLFireability-01 1136520 m, 7118 m/sec, 19279246 t fired, .

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4 AGEF EXCL 141/239 5/5 DLCround-PT-03a-CTLFireability-01 1172930 m, 7282 m/sec, 19931297 t fired, .

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25 CTL EXCL 110/353 4/32 DLCround-PT-03a-CTLFireability-08 891337 m, 7057 m/sec, 13472282 t fired, .

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25 CTL EXCL 115/353 4/32 DLCround-PT-03a-CTLFireability-08 921521 m, 6036 m/sec, 14080685 t fired, .

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25 CTL EXCL 120/353 4/32 DLCround-PT-03a-CTLFireability-08 954146 m, 6525 m/sec, 14657115 t fired, .

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25 CTL EXCL 125/353 5/32 DLCround-PT-03a-CTLFireability-08 985360 m, 6242 m/sec, 15261162 t fired, .

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25 CTL EXCL 130/353 5/32 DLCround-PT-03a-CTLFireability-08 1016516 m, 6231 m/sec, 15823966 t fired, .

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25 CTL EXCL 145/353 5/32 DLCround-PT-03a-CTLFireability-08 1119385 m, 6596 m/sec, 17550206 t fired, .

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25 CTL EXCL 150/353 5/32 DLCround-PT-03a-CTLFireability-08 1150993 m, 6321 m/sec, 18138471 t fired, .

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25 CTL EXCL 155/353 5/32 DLCround-PT-03a-CTLFireability-08 1182982 m, 6397 m/sec, 18706999 t fired, .

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25 CTL EXCL 180/353 6/32 DLCround-PT-03a-CTLFireability-08 1391133 m, 7892 m/sec, 21592963 t fired, .

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25 CTL EXCL 185/353 6/32 DLCround-PT-03a-CTLFireability-08 1426118 m, 6997 m/sec, 22195403 t fired, .

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25 CTL EXCL 190/353 7/32 DLCround-PT-03a-CTLFireability-08 1461237 m, 7023 m/sec, 22784696 t fired, .

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25 CTL EXCL 200/353 7/32 DLCround-PT-03a-CTLFireability-08 1523233 m, 5905 m/sec, 23948401 t fired, .

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25 CTL EXCL 205/353 7/32 DLCround-PT-03a-CTLFireability-08 1551448 m, 5643 m/sec, 24568993 t fired, .

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25 CTL EXCL 215/353 7/32 DLCround-PT-03a-CTLFireability-08 1619029 m, 6407 m/sec, 25664148 t fired, .

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25 CTL EXCL 325/353 10/32 DLCround-PT-03a-CTLFireability-08 2361284 m, 5539 m/sec, 38167115 t fired, .

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25 CTL EXCL 115/353 4/5 DLCround-PT-03a-CTLFireability-08 949656 m, 6500 m/sec, 14604833 t fired, .

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16 CTL EXCL 111/382 4/32 DLCround-PT-03a-CTLFireability-05 916495 m, 7192 m/sec, 13866813 t fired, .

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16 CTL EXCL 120/382 5/32 DLCround-PT-03a-CTLFireability-05 988314 m, 6936 m/sec, 15110193 t fired, .

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13 CTL EXCL 15/381 1/32 DLCround-PT-03a-CTLFireability-04 141503 m, 10893 m/sec, 1499704 t fired, .
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13 CTL EXCL 80/381 3/32 DLCround-PT-03a-CTLFireability-04 625755 m, 7901 m/sec, 7942454 t fired, .
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13 CTL EXCL 85/381 3/32 DLCround-PT-03a-CTLFireability-04 662607 m, 7370 m/sec, 8350577 t fired, .
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13 CTL EXCL 145/381 5/32 DLCround-PT-03a-CTLFireability-04 1077457 m, 10787 m/sec, 14384385 t fired, .
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13 CTL EXCL 150/381 5/32 DLCround-PT-03a-CTLFireability-04 1113737 m, 7256 m/sec, 14921145 t fired, .
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13 CTL EXCL 155/381 5/32 DLCround-PT-03a-CTLFireability-04 1146042 m, 6461 m/sec, 15377449 t fired, .
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13 CTL EXCL 216/381 7/32 DLCround-PT-03a-CTLFireability-04 1565816 m, 7205 m/sec, 21702292 t fired, .

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DLCround-PT-03a-CTLFireability-14: EF true findpath
DLCround-PT-03a-CTLFireability-15: CTL false CTL model checker

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DLCround-PT-03a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 111/380 2/32 DLCround-PT-03a-CTLFireability-00 404555 m, 1803 m/sec, 6772416 t fired, .
13 CTL EXCL 111/317 3/5 DLCround-PT-03a-CTLFireability-04 673058 m, 3948 m/sec, 8516176 t fired, .

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DLCround-PT-03a-CTLFireability-10: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: EF true findpath
DLCround-PT-03a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 116/380 2/32 DLCround-PT-03a-CTLFireability-00 421026 m, 3294 m/sec, 7038714 t fired, .
13 CTL EXCL 116/317 3/5 DLCround-PT-03a-CTLFireability-04 700527 m, 5493 m/sec, 8953386 t fired, .

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DLCround-PT-03a-CTLFireability-10: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: EF true findpath
DLCround-PT-03a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-03a-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 121/380 2/32 DLCround-PT-03a-CTLFireability-00 436126 m, 3020 m/sec, 7301051 t fired, .
13 CTL EXCL 121/317 4/5 DLCround-PT-03a-CTLFireability-04 732410 m, 6376 m/sec, 9479123 t fired, .

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DLCround-PT-03a-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-13: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-03a-CTLFireability-01: AGEF 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 126/380 2/32 DLCround-PT-03a-CTLFireability-00 451226 m, 3020 m/sec, 7560058 t fired, .
13 CTL EXCL 126/317 4/5 DLCround-PT-03a-CTLFireability-04 764355 m, 6389 m/sec, 9835189 t fired, .

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DLCround-PT-03a-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03a-CTLFireability-14: EF true findpath
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DLCround-PT-03a-CTLFireability-02: EFAG 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 131/380 2/32 DLCround-PT-03a-CTLFireability-00 463237 m, 2402 m/sec, 7773375 t fired, .
13 CTL EXCL 131/317 4/5 DLCround-PT-03a-CTLFireability-04 785812 m, 4291 m/sec, 10235151 t fired, .


========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-03a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCround-PT-03a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393000274"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-03a.tgz
mv DLCround-PT-03a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;