About the Execution of LoLA for DLCflexbar-PT-7a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16235.987 | 409618.00 | 496775.00 | 1116.00 | FF?FF??FFF?FT??? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r061-tall-162038392900245.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCflexbar-PT-7a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038392900245
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.6M
-rw-r--r-- 1 mcc users 17K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 157K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 85K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Mar 23 04:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K Mar 23 04:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Mar 22 14:34 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 22 14:34 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 6.2M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-7a-00
FORMULA_NAME DLCflexbar-PT-7a-01
FORMULA_NAME DLCflexbar-PT-7a-02
FORMULA_NAME DLCflexbar-PT-7a-03
FORMULA_NAME DLCflexbar-PT-7a-04
FORMULA_NAME DLCflexbar-PT-7a-05
FORMULA_NAME DLCflexbar-PT-7a-06
FORMULA_NAME DLCflexbar-PT-7a-07
FORMULA_NAME DLCflexbar-PT-7a-08
FORMULA_NAME DLCflexbar-PT-7a-09
FORMULA_NAME DLCflexbar-PT-7a-10
FORMULA_NAME DLCflexbar-PT-7a-11
FORMULA_NAME DLCflexbar-PT-7a-12
FORMULA_NAME DLCflexbar-PT-7a-13
FORMULA_NAME DLCflexbar-PT-7a-14
FORMULA_NAME DLCflexbar-PT-7a-15
=== Now, execution of the tool begins
BK_START 1620440138466
starting LoLA
BK_INPUT DLCflexbar-PT-7a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability
FORMULA DLCflexbar-PT-7a-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-7a-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620440548084
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 30 (type CNST) for 27 DLCflexbar-PT-7a-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 30 (type CNST) for DLCflexbar-PT-7a-09
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-09: CONJ false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-04: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-08: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-11: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-12: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-13: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-7a-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 20 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 52 (type SKEL/SRCH) for 43 DLCflexbar-PT-7a-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: NOTDEADLOCKFREE
lola: FINISHED task # 52 (type SKEL/SRCH) for DLCflexbar-PT-7a-13
lola: result : false
lola: markings : 328758
lola: fired transitions : 1049183
lola: time used : 5.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-09: CONJ false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-04: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-08: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-11: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-12: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 25 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-09: CONJ false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-04: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-08: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-11: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-12: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-09: CONJ false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-04: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-08: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-11: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-12: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type EXCL) for 24 DLCflexbar-PT-7a-08
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 54 (type FNDP) for 24 DLCflexbar-PT-7a-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type EQUN) for 24 DLCflexbar-PT-7a-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type SRCH) for 24 DLCflexbar-PT-7a-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 54 (type FNDP) for DLCflexbar-PT-7a-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 55 (type EQUN) for DLCflexbar-PT-7a-08 (obsolete)
lola: CANCELED task # 56 (type EXCL) for DLCflexbar-PT-7a-08 (obsolete)
lola: CANCELED task # 57 (type SRCH) for DLCflexbar-PT-7a-08 (obsolete)
lola: FINISHED task # 56 (type EXCL) for DLCflexbar-PT-7a-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/LTLFireability-55.sara.
lola: FINISHED task # 57 (type SRCH) for DLCflexbar-PT-7a-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 55 (type EQUN) for DLCflexbar-PT-7a-08
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-04: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-10: LTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-05: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-7a-15: LTL 0 1 0 0 1 0 0 0
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47 LTL EXCL 41/503 2/32 DLCflexbar-PT-7a-14 197956 m, 4762 m/sec, 13948234 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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47 LTL EXCL 46/503 2/32 DLCflexbar-PT-7a-14 221498 m, 4708 m/sec, 15644289 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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47 LTL EXCL 51/503 2/32 DLCflexbar-PT-7a-14 245038 m, 4708 m/sec, 17342874 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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47 LTL EXCL 56/503 2/32 DLCflexbar-PT-7a-14 268663 m, 4725 m/sec, 19040004 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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47 LTL EXCL 61/503 2/32 DLCflexbar-PT-7a-14 292717 m, 4810 m/sec, 20736859 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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47 LTL EXCL 66/503 3/32 DLCflexbar-PT-7a-14 316610 m, 4778 m/sec, 22436767 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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47 LTL EXCL 71/503 3/32 DLCflexbar-PT-7a-14 340465 m, 4771 m/sec, 24134793 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-7a-15: LTL 0 1 0 0 1 0 0 0
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47 LTL EXCL 76/503 3/32 DLCflexbar-PT-7a-14 364152 m, 4737 m/sec, 25832645 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-7a-05: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-7a-15: LTL 0 1 0 0 1 0 0 0
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47 LTL EXCL 81/503 3/32 DLCflexbar-PT-7a-14 387739 m, 4717 m/sec, 27526213 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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47 LTL EXCL 86/503 3/32 DLCflexbar-PT-7a-14 411092 m, 4670 m/sec, 29221915 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-7a-15: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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47 LTL EXCL 201/503 7/32 DLCflexbar-PT-7a-14 941559 m, 4655 m/sec, 68423880 t fired, .
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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47 LTL EXCL 206/503 7/32 DLCflexbar-PT-7a-14 964695 m, 4627 m/sec, 70147921 t fired, .
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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47 LTL EXCL 231/503 8/32 DLCflexbar-PT-7a-14 1079601 m, 4636 m/sec, 78766011 t fired, .
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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DLCflexbar-PT-7a-04: LTL false LTL model checker
DLCflexbar-PT-7a-07: LTL false LTL model checker
DLCflexbar-PT-7a-08: AG false findpath
DLCflexbar-PT-7a-09: CONJ false preprocessing
DLCflexbar-PT-7a-11: LTL false LTL model checker
DLCflexbar-PT-7a-12: F true state space / EG
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/home/mcc/BenchKit/BenchKit_head.sh: line 62: 411 Killed lola --conf=$BIN_DIR/configfiles/ltlfireabilityconf --formula=$DIR/LTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-7a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-7a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038392900245"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-7a.tgz
mv DLCflexbar-PT-7a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;