Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2021-input.r023-tajo-162038139500318.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BridgeAndVehicles-PT-V80P50N50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r023-tajo-162038139500318
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 38M
-rw-r--r-- 1 mcc users 106K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 459K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8M May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 19M May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 13K Mar 28 15:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 47K Mar 28 15:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 471K Mar 28 15:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 1.4M Mar 28 15:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Mar 23 03:00 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 37K Mar 23 03:00 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 667K Mar 22 12:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 1.9M Mar 22 12:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.4K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.0K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 10 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 9.5M May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1620866139322

starting LoLA
BK_INPUT BridgeAndVehicles-PT-V80P50N50
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620866284902

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0

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BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 59 (type EXCL) for 15 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 15 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 15 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SRCH) for 15 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 55 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 315
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 56 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 58 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 59 (type EXCL) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-56.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type EXCL) for 18 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06
lola: time limit : 296 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 62 (type FNDP) for 18 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type EQUN) for 18 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type SRCH) for 18 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-63.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 4/590 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 4683 t fired, 14 attempts, .
63 EF STEQ 4/708 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 sara is running.
65 EF SRCH 4/708 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 3637 m, 727 m/sec, 6769 t fired, .
66 EF EXCL 4/296 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 983 m, 196 m/sec, 1062 t fired, .

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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 9/213 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 13950 t fired, 41 attempts, .
63 EF STEQ 9/213 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 sara is running.
65 EF SRCH 9/213 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 12965 m, 1865 m/sec, 24880 t fired, .
66 EF EXCL 9/296 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 2372 m, 277 m/sec, 2797 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 14/213 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 32910 t fired, 96 attempts, .
63 EF STEQ 14/213 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 sara is running.
65 EF SRCH 14/213 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 31576 m, 3722 m/sec, 53777 t fired, .
66 EF EXCL 14/296 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 4932 m, 512 m/sec, 6027 t fired, .

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sara: place or transition ordering is non-deterministic

FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 19/208 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 48258 t fired, 140 attempts, .
63 EF STEQ 19/208 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 sara is running.
65 EF SRCH 19/208 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 41734 m, 2031 m/sec, 82316 t fired, .
66 EF EXCL 19/296 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 7321 m, 477 m/sec, 9209 t fired, .

Time elapsed: 61 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 50 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 24/200 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 66606 t fired, 192 attempts, .
63 EF STEQ 24/200 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 sara is running.
65 EF SRCH 24/200 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 51313 m, 1915 m/sec, 109741 t fired, .
66 EF EXCL 24/296 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 9932 m, 522 m/sec, 12720 t fired, .

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lola: FINISHED task # 63 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06
lola: result : false
lola: CANCELED task # 62 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 65 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 66 (type EXCL) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 86 (type EXCL) for 30 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10
lola: time limit : 321 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 69 (type FNDP) for 39 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type EQUN) for 39 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type SRCH) for 39 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 62 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06
lola: result : unknown
lola: fired transitions : 67261
lola: tried executions : 194
lola: time used : 24.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-70.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 2 3 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 EF FNDP 5/235 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 17358 t fired, 46 attempts, .
70 EF STEQ 5/235 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 sara is running.
72 EF SRCH 5/252 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 9250 m, 1850 m/sec, 24129 t fired, .
86 EF EXCL 5/321 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 4216 m, 843 m/sec, 5539 t fired, .

Time elapsed: 71 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 2 3 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 EF FNDP 10/230 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 36478 t fired, 102 attempts, .
70 EF STEQ 10/230 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 sara is running.
72 EF SRCH 10/247 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 27230 m, 3596 m/sec, 68220 t fired, .
86 EF EXCL 10/321 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 9036 m, 964 m/sec, 12200 t fired, .

Time elapsed: 76 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG 0 2 3 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 EF FNDP 15/225 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 55048 t fired, 156 attempts, .
70 EF STEQ 15/225 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 sara is running.
72 EF SRCH 15/242 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 40522 m, 2658 m/sec, 100667 t fired, .
86 EF EXCL 15/321 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 14608 m, 1114 m/sec, 20363 t fired, .

Time elapsed: 81 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16

lola: FINISHED task # 70 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13
lola: result : true
lola: CANCELED task # 69 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 72 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 121 (type FNDP) for 33 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 122 (type EQUN) for 33 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 124 (type SRCH) for 33 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13
lola: result : unknown
lola: fired transitions : 70737
lola: tried executions : 203
lola: time used : 19.000000
lola: memory pages used : 0
lola: FINISHED task # 124 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11
lola: result : true
lola: markings : 199
lola: fired transitions : 198
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 121 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 122 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 127 (type FNDP) for 45 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type EQUN) for 45 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 130 (type SRCH) for 45 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 121 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11
lola: result : unknown
lola: fired transitions : 163
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 2 3 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EF EXCL 20/392 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 20170 m, 1112 m/sec, 28412 t fired, .
127 EF FNDP 0/292 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 333 t fired, 2 attempts, .
128 EF STEQ 0/292 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 sara is running.
130 EF SRCH 0/292 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 481 m, 96 m/sec, 531 t fired, .

Time elapsed: 86 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-128.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-122.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 2 3 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EF EXCL 25/392 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 25539 m, 1073 m/sec, 36333 t fired, .
127 EF FNDP 5/292 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 12265 t fired, 49 attempts, .
128 EF STEQ 5/292 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 sara is running.
130 EF SRCH 5/292 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 7210 m, 1345 m/sec, 13660 t fired, .

Time elapsed: 91 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 2 3 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EF EXCL 30/392 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 30858 m, 1063 m/sec, 44067 t fired, .
127 EF FNDP 10/287 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 22349 t fired, 87 attempts, .
128 EF STEQ 10/287 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 sara is running.
130 EF SRCH 10/287 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 14822 m, 1522 m/sec, 28052 t fired, .

Time elapsed: 96 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 2 3 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EF EXCL 35/392 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 35736 m, 975 m/sec, 51226 t fired, .
127 EF FNDP 15/282 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 31946 t fired, 122 attempts, .
128 EF STEQ 15/282 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 sara is running.
130 EF SRCH 15/282 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 21378 m, 1311 m/sec, 40553 t fired, .

Time elapsed: 101 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic

FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF 0 2 3 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
86 EF EXCL 40/392 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 41579 m, 1168 m/sec, 59834 t fired, .
127 EF FNDP 20/277 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 41835 t fired, 156 attempts, .
128 EF STEQ 20/277 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 sara is running.
130 EF SRCH 20/277 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 28606 m, 1445 m/sec, 54318 t fired, .

Time elapsed: 106 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 128 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15
lola: result : true
lola: CANCELED task # 127 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 130 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 102 (type FNDP) for 36 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type EQUN) for 36 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type SRCH) for 36 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 127 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 42666
lola: tried executions : 159
lola: time used : 21.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-103.sara.
lola: FINISHED task # 102 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 1754
lola: tried executions : 4
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 103 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 105 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 134 (type FNDP) for 0 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 135 (type EQUN) for 0 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 137 (type SRCH) for 0 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 103 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 137 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00
lola: result : true
lola: markings : 282
lola: fired transitions : 281
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 134 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 135 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 95 (type FNDP) for 27 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type EQUN) for 27 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 98 (type SRCH) for 27 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 134 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00
lola: result : unknown
lola: fired transitions : 279
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 135 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00
lola: result : unknown
lola: FINISHED task # 95 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09
lola: result : true
lola: fired transitions : 387
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 96 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 98 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 115 (type FNDP) for 24 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type EQUN) for 24 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type SRCH) for 24 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 118 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08
lola: result : true
lola: markings : 67
lola: fired transitions : 66
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 115 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 116 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 76 (type FNDP) for 21 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type EQUN) for 21 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SRCH) for 21 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 115 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 23
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-96.sara.
lola: FINISHED task # 76 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 77 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 79 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 89 (type FNDP) for 12 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type EQUN) for 12 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 92 (type SRCH) for 12 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787

lola: FINISHED task # 92 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04
lola: result : true
lola: markings : 82
lola: fired transitions : 81
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 89 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 90 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 109 (type FNDP) for 42 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 110 (type EQUN) for 42 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 112 (type SRCH) for 42 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-116.sara.
lola: FINISHED task # 89 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04
lola: result : true
lola: fired transitions : 80
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-77.sara.
lola: FINISHED task # 109 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 27
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 110 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 112 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 82 (type FNDP) for 30 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type EQUN) for 30 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SRCH) for 30 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-90.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-110.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-83.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 1/1745 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 1134 t fired, 8 attempts, .
83 EF STEQ 1/3490 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 sara is running.
85 EF SRCH 1/3490 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 1232 m, 246 m/sec, 1438 t fired, .
86 EF EXCL 45/3534 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 44601 m, 604 m/sec, 64287 t fired, .

Time elapsed: 111 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 122 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 6/1740 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 7875 t fired, 49 attempts, .
83 EF STEQ 6/3485 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 sara is running.
85 EF SRCH 6/3485 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 7436 m, 1240 m/sec, 10695 t fired, .
86 EF EXCL 50/3534 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 47448 m, 569 m/sec, 68473 t fired, .

Time elapsed: 116 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 11/1739 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 15655 t fired, 96 attempts, .
83 EF STEQ 11/3484 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 sara is running.
85 EF SRCH 11/3484 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 13672 m, 1247 m/sec, 20026 t fired, .
86 EF EXCL 55/3534 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 50800 m, 670 m/sec, 73412 t fired, .

Time elapsed: 121 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 16/1734 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 23580 t fired, 142 attempts, .
83 EF STEQ 16/3479 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 sara is running.
85 EF SRCH 16/3479 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 20372 m, 1340 m/sec, 29726 t fired, .
86 EF EXCL 60/3534 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 53967 m, 633 m/sec, 78085 t fired, .

Time elapsed: 126 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 21/1729 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 31380 t fired, 188 attempts, .
83 EF STEQ 21/3474 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 sara is running.
85 EF SRCH 21/3474 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 26634 m, 1252 m/sec, 39095 t fired, .
86 EF EXCL 65/3534 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 57172 m, 641 m/sec, 82802 t fired, .

Time elapsed: 131 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 26/1724 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 39265 t fired, 233 attempts, .
83 EF STEQ 26/3469 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 sara is running.
85 EF SRCH 26/3469 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 33092 m, 1291 m/sec, 48437 t fired, .
86 EF EXCL 70/3534 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 60445 m, 654 m/sec, 87622 t fired, .

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# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic

sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic


FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 EF FNDP 31/1719 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 46554 t fired, 276 attempts, .
83 EF STEQ 31/3464 0/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 sara is running.
85 EF SRCH 31/3464 1/5 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 39570 m, 1295 m/sec, 58128 t fired, .
86 EF EXCL 75/3534 1/32 BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 63805 m, 672 m/sec, 92555 t fired, .

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# running tasks: 4 of 4 Visible: 16

lola: FINISHED task # 116 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08
lola: result : true
lola: FINISHED task # 110 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14
lola: result : true
lola: FINISHED task # 83 (type EQUN) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10
lola: result : false
lola: CANCELED task # 82 (type FNDP) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 85 (type SRCH) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 86 (type EXCL) for BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-00: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-01: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-03: INITIAL false preprocessing
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-04: AG false tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-06: AG true state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-07: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-08: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-09: EF true findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-10: EF false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-11: EF true tandem / insertion
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-13: AG false state equation
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-PT-V80P50N50-ReachabilityCardinality-15: EF true state equation


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V80P50N50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V80P50N50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r023-tajo-162038139500318"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V80P50N50.tgz
mv BridgeAndVehicles-PT-V80P50N50 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;