About the Execution of LoLA for BridgeAndVehicles-PT-V50P50N50
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3579.479 | 42828.00 | 142195.00 | 12.60 | FTFFTFFFFFFTFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2021-input.r023-tajo-162038139500270.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BridgeAndVehicles-PT-V50P50N50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r023-tajo-162038139500270
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 29M
-rw-r--r-- 1 mcc users 119K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 538K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4M May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 17M May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 9.1K Mar 28 15:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 40K Mar 28 15:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 182K Mar 28 15:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 519K Mar 28 15:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Mar 23 02:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 42K Mar 23 02:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 146K Mar 22 11:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 424K Mar 22 11:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.4K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.4K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 10 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 6.0M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1620862462855
starting LoLA
BK_INPUT BridgeAndVehicles-PT-V50P50N50
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620862505683
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 6 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 7 (type CNST) for 6 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 7 (type CNST) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02
lola: result : false
lola: LAUNCH INITIAL
lola: LAUNCH task # 22 (type CNST) for 21 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 22 (type CNST) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07
lola: result : false
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 11 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 13 (type CNST) for 12 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 13 (type CNST) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 9 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 9 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 9 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type SRCH) for 9 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF 0 1 4 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 3/1793 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03 877 t fired, 3 attempts, .
49 EF STEQ 3/3587 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03 sara is running.
51 EF SRCH 3/3587 1/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03 1198 m, 239 m/sec, 2214 t fired, .
52 EF EXCL 3/275 1/32 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03 66 m, 13 m/sec, 65 t fired, .
Time elapsed: 16 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 49 (type EQUN) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 48 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 51 (type SRCH) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 52 (type EXCL) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 132 (type EXCL) for 18 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 61 (type FNDP) for 33 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 33 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 33 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 48 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 11252
lola: tried executions : 179
lola: time used : 7.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 132 (type EXCL) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06
lola: result : true
lola: markings : 62
lola: fired transitions : 61
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 115 (type EXCL) for 0 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 51
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 62 (type EQUN) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 64 (type SRCH) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 86 (type FNDP) for 15 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type EQUN) for 15 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 89 (type SRCH) for 15 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 115 (type EXCL) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00
lola: result : true
lola: markings : 62
lola: fired transitions : 61
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 125 (type EXCL) for 27 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09
lola: time limit : 397 sec
lola: memory limit: 32 pages
lola: FINISHED task # 125 (type EXCL) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09
lola: result : true
lola: markings : 26
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 118 (type EXCL) for 36 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12
lola: time limit : 447 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-62.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-87.sara.
lola: FINISHED task # 118 (type EXCL) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12
lola: result : true
lola: markings : 48
lola: fired transitions : 47
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 104 (type EXCL) for 24 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08
lola: time limit : 511 sec
lola: memory limit: 32 pages
lola: FINISHED task # 104 (type EXCL) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08
lola: result : true
lola: markings : 158
lola: fired transitions : 157
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 84 (type EXCL) for 30 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10
lola: time limit : 596 sec
lola: memory limit: 32 pages
lola: FINISHED task # 84 (type EXCL) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10
lola: result : true
lola: markings : 49
lola: fired transitions : 48
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 71 (type EXCL) for 39 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13
lola: time limit : 715 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF true findpath
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF 0 2 3 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 EF EXCL 0/715 1/32 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 51 m, 10 m/sec, 50 t fired, .
86 EF FNDP 1/510 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05 1610 t fired, 6 attempts, .
87 EF STEQ 1/510 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05 sara is running.
89 EF SRCH 1/595 1/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05 5955 m, 1191 m/sec, 9705 t fired, .
Time elapsed: 21 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 87 (type EQUN) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05
lola: result : false
lola: CANCELED task # 86 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 89 (type SRCH) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 55 (type FNDP) for 45 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 45 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SRCH) for 45 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 86 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 24932
lola: tried executions : 101
lola: time used : 5.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-56.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF true findpath
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG 0 2 3 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 1/595 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 720 t fired, 3 attempts, .
56 EF STEQ 1/715 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 sara is running.
58 EF SRCH 1/715 1/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 1365 m, 273 m/sec, 2325 t fired, .
71 EF EXCL 5/894 1/32 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 6598 m, 1309 m/sec, 9962 t fired, .
Time elapsed: 26 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF true findpath
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG 0 2 3 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 6/594 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 19437 t fired, 61 attempts, .
56 EF STEQ 6/714 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 sara is running.
58 EF SRCH 6/714 1/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 24733 m, 4673 m/sec, 68969 t fired, .
71 EF EXCL 10/894 1/32 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 13634 m, 1407 m/sec, 21399 t fired, .
Time elapsed: 31 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 56 (type EQUN) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15
lola: result : false
lola: CANCELED task # 55 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 58 (type SRCH) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 93 (type FNDP) for 42 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type EQUN) for 42 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 96 (type SRCH) for 42 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 55 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 19687
lola: tried executions : 63
lola: time used : 6.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-94.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF true findpath
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG true state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG 0 2 3 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 EF EXCL 15/1193 1/32 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 20582 m, 1389 m/sec, 32115 t fired, .
93 EF FNDP 5/892 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14 13451 t fired, 34 attempts, .
94 EF STEQ 5/892 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14 sara is running.
96 EF SRCH 5/892 1/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14 15068 m, 3013 m/sec, 29529 t fired, .
Time elapsed: 36 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 94 (type EQUN) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14
lola: result : true
lola: CANCELED task # 93 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 96 (type SRCH) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 73 (type FNDP) for 3 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type EQUN) for 3 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type SRCH) for 3 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 93 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 15771
lola: tried executions : 42
lola: time used : 6.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 76 (type SRCH) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01
lola: result : true
lola: markings : 347
lola: fired transitions : 346
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 73 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 74 (type EQUN) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 67 (type FNDP) for 39 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type EQUN) for 39 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type SRCH) for 39 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 73 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 303
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-74.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-68.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF true tandem / insertion
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF true findpath
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG true state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF 0 1 4 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF FNDP 4/1781 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 16910 t fired, 246 attempts, .
68 EF STEQ 4/3563 0/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 sara is running.
70 EF SRCH 4/3563 1/5 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 19527 m, 3905 m/sec, 28728 t fired, .
71 EF EXCL 20/3579 1/32 BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 25931 m, 1069 m/sec, 40142 t fired, .
Time elapsed: 41 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 68 (type EQUN) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13
lola: result : false
lola: CANCELED task # 67 (type FNDP) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 70 (type SRCH) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 71 (type EXCL) for BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-00: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-01: EF true tandem / insertion
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-02: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-03: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-04: INITIAL true preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-05: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-06: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-07: INITIAL false preprocessing
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-08: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-09: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-10: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-11: EF true findpath
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-12: AG false tandem / relaxed
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-13: EF false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-14: AG false state equation
BridgeAndVehicles-PT-V50P50N50-ReachabilityCardinality-15: AG true state equation
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V50P50N50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-PT-V50P50N50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r023-tajo-162038139500270"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V50P50N50.tgz
mv BridgeAndVehicles-PT-V50P50N50 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;