About the Execution of LoLA for BridgeAndVehicles-COL-V80P50N50
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 7368.231 | 52226.00 | 161167.00 | 25.30 | FFFFFTTFFFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2021-input.r023-tajo-162038139300158.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BridgeAndVehicles-COL-V80P50N50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r023-tajo-162038139300158
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 384K
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 92K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Mar 28 15:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 15:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 28 15:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 15:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Mar 23 03:00 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 23 02:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Mar 22 12:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 22 12:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 10 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 47K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
FORMULA_NAME BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1620856713462
starting LoLA
BK_INPUT BridgeAndVehicles-COL-V80P50N50
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620856765688
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 65 (type SKEL/FNDP) for 12 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: TR BINDINGS
lola: LAUNCH task # 66 (type SKEL/EQUN) for 12 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SKEL/SRCH) for 12 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 69 (type SKEL/SRCH) for 12 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 65 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: result : true
lola: fired transitions : 80
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 68 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: result : true
lola: markings : 82
lola: fired transitions : 81
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 11 (type SKEL/CNST) for 9 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: CANCELED task # 66 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 69 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 50 (type SKEL/FNDP) for 0 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SKEL/EQUN) for 0 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 53 (type SKEL/SRCH) for 0 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 11 (type SKEL/CNST) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 75 (type SKEL/FNDP) for 6 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: TR BINDINGS DONE
lola: Places: 228, Transitions: 8588
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 53 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: result : true
lola: markings : 194
lola: fired transitions : 193
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 75 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: result : true
lola: fired transitions : 36
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 50 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 51 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 104 (type SKEL/FNDP) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type SKEL/EQUN) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 107 (type SKEL/SRCH) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type SKEL/SRCH) for 18 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 192
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 51 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-66.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-105.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: @ trans enregistrement_A
lola: @ trans decision
lola: @ trans altern_cpt
lola: @ trans autorisation_A
lola: @ trans liberation_A
lola: FINISHED task # 66 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: result : true
lola: @ trans enregistrement_B
lola: @ trans timeout_A
lola: @ trans timeout_B
lola: @ trans liberation_B
lola: FINISHED task # 105 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: result : false
lola: CANCELED task # 104 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 107 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 108 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 139 (type SKEL/FNDP) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 145 (type SKEL/EQUN) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 155 (type SKEL/SRCH) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: @ trans basculement
lola: LAUNCH task # 156 (type SKEL/SRCH) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 104 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06
lola: result : unknown
lola: fired transitions : 131119
lola: tried executions : 306
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 155 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : true
lola: markings : 187
lola: fired transitions : 186
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 139 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 145 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 156 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 85 (type SKEL/FNDP) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 119 (type SKEL/EQUN) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 149 (type SKEL/SRCH) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 150 (type SKEL/SRCH) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: @ trans autorisation_B
lola: FINISHED task # 139 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 185
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 149 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: result : true
lola: markings : 81
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 85 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 119 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 150 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 98 (type SKEL/FNDP) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-145.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 99 (type SKEL/EQUN) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 101 (type SKEL/SRCH) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-119.sara.memory limit: 5 pages
lola: LAUNCH task # 102 (type SKEL/SRCH) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 68
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 145 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : true
lola: FINISHED task # 102 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: result : true
lola: markings : 81
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 101 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: result : true
lola: markings : 81
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 98 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 99 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 121 (type SKEL/FNDP) for 33 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 124 (type SKEL/EQUN) for 33 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 126 (type SKEL/SRCH) for 33 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 127 (type SKEL/SRCH) for 33 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: FINISHED task # 99 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 119 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: result : true
lola: FINISHED task # 121 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 99
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 124 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 126 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 127 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 143 (type SKEL/FNDP) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 151 (type SKEL/EQUN) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 157 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 159 (type SKEL/SRCH) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 126 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: result : true
lola: markings : 101
lola: fired transitions : 100
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 157 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: markings : 31
lola: fired transitions : 30
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 143 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 151 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 159 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-124.sara.
lola: LAUNCH task # 112 (type SKEL/FNDP) for 45 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type SKEL/EQUN) for 45 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 115 (type SKEL/SRCH) for 45 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 116 (type SKEL/SRCH) for 45 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-151.sara.
lola: FINISHED task # 143 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 29
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 124 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: result : true
lola: FINISHED task # 115 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 112 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 113 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 116 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 142 (type SKEL/FNDP) for 39 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 147 (type SKEL/EQUN) for 39 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 158 (type SKEL/SRCH) for 39 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 160 (type SKEL/SRCH) for 39 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 112 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 17909
lola: tried executions : 17910
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 160 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: result : true
lola: markings : 79
lola: fired transitions : 78
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 142 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 147 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 158 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 90 (type SKEL/FNDP) for 27 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type SKEL/EQUN) for 27 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 93 (type SKEL/SRCH) for 27 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-113.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 94 (type SKEL/SRCH) for 27 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 151 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: FINISHED task # 142 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 77
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-147.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 147 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-91.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 94 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: result : false
lola: markings : 19843
lola: fired transitions : 32804
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 90 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 91 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 93 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 122 (type SKEL/FNDP) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 123 (type SKEL/FNDP) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type SKEL/EQUN) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 130 (type SKEL/SRCH) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 90 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: result : unknown
lola: fired transitions : 10906
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 113 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15
lola: result : false
lola: FINISHED task # 130 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: result : true
lola: markings : 83
lola: fired transitions : 82
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 123 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 128 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-128.sara.
lola: LAUNCH task # 57 (type SKEL/FNDP) for 3 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SKEL/EQUN) for 3 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SKEL/SRCH) for 3 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 57 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 58 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 133 (type SKEL/EQUN) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 140 (type SKEL/SRCH) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 141 (type SKEL/SRCH) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 91 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09
lola: result : false
lola: FINISHED task # 123 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 81
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 140 (type SKEL/SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: result : true
lola: markings : 83
lola: fired transitions : 82
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-58.sara.
lola: CANCELED task # 122 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 133 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 141 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: FINISHED task # 122 (type SKEL/FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 81
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 128 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-133.sara.
lola: FINISHED task # 58 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01
lola: result : false
lola: FINISHED task # 133 (type SKEL/EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Rule S: 0 transitions removed,0 places removed
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06 stopped (result already fixed).
lola: planning for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09 stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 5 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 10 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 169 (type EXCL) for 6 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 165 (type FNDP) for 6 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 166 (type EQUN) for 6 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 168 (type SRCH) for 6 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-166.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG 0 1 4 0 1 0 0 4
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
165 EF FNDP 2/1786 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 --
166 EF STEQ 2/3572 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 sara is running.
168 EF SRCH 2/3572 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 35 m, 7 m/sec, 34 t fired, .
169 EF EXCL 2/324 1/32 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 6 m, 1 m/sec, 5 t fired, .
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lola: FINISHED task # 168 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: result : true
lola: markings : 35
lola: fired transitions : 34
lola: time used : 2.000000
lola: memory pages used : 1
lola: CANCELED task # 165 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 166 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 169 (type EXCL) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02 (obsolete)
lola: FINISHED task # 166 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: result : unknown
lola: FINISHED task # 165 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02
lola: result : true
lola: fired transitions : 33
lola: tried executions : 1
lola: time used : 3.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 0 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 176 (type EXCL) for 12 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: time limit : 394 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 172 (type FNDP) for 12 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 173 (type EQUN) for 12 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 175 (type SRCH) for 12 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-173.sara.
lola: FINISHED task # 172 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: result : true
lola: fired transitions : 80
lola: tried executions : 1
lola: time used : 2.000000
lola: memory pages used : 0
lola: CANCELED task # 173 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 175 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 176 (type EXCL) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 183 (type EXCL) for 21 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: time limit : 394 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 193 (type FNDP) for 0 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 194 (type EQUN) for 0 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 196 (type SRCH) for 0 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 173 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-194.sara.
lola: FINISHED task # 183 (type EXCL) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07
lola: result : true
lola: markings : 81
lola: fired transitions : 80
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 190 (type EXCL) for 33 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: time limit : 443 sec
lola: memory limit: 32 pages
lola: FINISHED task # 193 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 280
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 194 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 196 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 199 (type FNDP) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 200 (type EQUN) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 202 (type SRCH) for 15 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 194 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-200.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 190 (type EXCL) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11
lola: result : true
lola: markings : 151
lola: fired transitions : 150
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 210 (type EXCL) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 591 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG false tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG false tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF 0 2 3 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG 0 4 1 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG 0 5 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG 0 0 0 0 3 0 0 2
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG 0 5 0 0 4 0 0 1
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
199 EF FNDP 1/590 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 --
200 EF STEQ 1/709 0/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 sara is running.
202 EF SRCH 1/709 1/5 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 --
210 EF EXCL 0/591 1/32 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 --
Time elapsed: 50 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 199 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 315
lola: tried executions : 1
lola: time used : 2.000000
lola: memory pages used : 0
lola: CANCELED task # 200 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 202 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 213 (type FNDP) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 214 (type EQUN) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 216 (type SRCH) for 36 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 200 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 213 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 29
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 214 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 216 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 220 (type FNDP) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 221 (type EQUN) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 223 (type SRCH) for 42 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 220 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 221 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 223 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 227 (type FNDP) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 228 (type EQUN) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 230 (type SRCH) for 30 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-214.sara.
lola: FINISHED task # 230 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: result : true
lola: markings : 84
lola: fired transitions : 83
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 227 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 228 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 234 (type FNDP) for 39 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 235 (type EQUN) for 39 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 237 (type SRCH) for 39 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 227 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 47
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 234 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 77
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 235 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 237 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 206 (type FNDP) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 207 (type EQUN) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 209 (type SRCH) for 24 BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-221.sara.
lola: FINISHED task # 206 (type FNDP) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 82
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 207 (type EQUN) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 209 (type SRCH) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 210 (type EXCL) for BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-00: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-01: EF false skeleton: tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-02: AG false tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-03: INITIAL false skeleton: preprocessing
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-04: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-05: EF true findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-06: AG true skeleton: state equation
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-07: AG false tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-08: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-09: EF false skeleton: tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-10: AG false tandem / insertion
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-11: AG false tandem / relaxed
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-12: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-13: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-14: AG false findpath
BridgeAndVehicles-COL-V80P50N50-ReachabilityCardinality-15: EF false skeleton: tandem / insertion
Time elapsed: 52 secs. Pages in use: 4
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V80P50N50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BridgeAndVehicles-COL-V80P50N50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r023-tajo-162038139300158"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V80P50N50.tgz
mv BridgeAndVehicles-COL-V80P50N50 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;