About the Execution of LoLA for BART-COL-005
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6891.228 | 350529.00 | 352418.00 | 887.10 | FFTTF?FFTFTFFFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r004-tall-162037986200540.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is BART-COL-005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r004-tall-162037986200540
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 127K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 15:45 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 15:45 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Mar 28 15:45 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 15:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.1K Mar 23 02:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K Mar 23 02:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 22 10:37 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K Mar 22 10:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 09:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 4 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 186K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BART-COL-005-CTLFireability-00
FORMULA_NAME BART-COL-005-CTLFireability-01
FORMULA_NAME BART-COL-005-CTLFireability-02
FORMULA_NAME BART-COL-005-CTLFireability-03
FORMULA_NAME BART-COL-005-CTLFireability-04
FORMULA_NAME BART-COL-005-CTLFireability-05
FORMULA_NAME BART-COL-005-CTLFireability-06
FORMULA_NAME BART-COL-005-CTLFireability-07
FORMULA_NAME BART-COL-005-CTLFireability-08
FORMULA_NAME BART-COL-005-CTLFireability-09
FORMULA_NAME BART-COL-005-CTLFireability-10
FORMULA_NAME BART-COL-005-CTLFireability-11
FORMULA_NAME BART-COL-005-CTLFireability-12
FORMULA_NAME BART-COL-005-CTLFireability-13
FORMULA_NAME BART-COL-005-CTLFireability-14
FORMULA_NAME BART-COL-005-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620731909041
starting LoLA
BK_INPUT BART-COL-005
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA BART-COL-005-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA BART-COL-005-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620732259570
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:207
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: LAUNCH INITIAL
lola: LAUNCH task # 2 (type SKEL/CNST) for 0 BART-COL-005-CTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 8 (type SKEL/CNST) for 6 BART-COL-005-CTLFireability-02
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 35 (type SKEL/CNST) for 33 BART-COL-005-CTLFireability-11
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 2 (type SKEL/CNST) for BART-COL-005-CTLFireability-00
lola: result : false
lola: FINISHED task # 35 (type SKEL/CNST) for BART-COL-005-CTLFireability-11
lola: result : false
lola: LAUNCH INITIAL
lola: LAUNCH task # 5 (type SKEL/CNST) for 3 BART-COL-005-CTLFireability-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 8 (type SKEL/CNST) for BART-COL-005-CTLFireability-02
lola: result : true
lola: LAUNCH INITIAL
lola: LAUNCH task # 20 (type SKEL/CNST) for 18 BART-COL-005-CTLFireability-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 29 (type SKEL/CNST) for 27 BART-COL-005-CTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 38 (type SKEL/CNST) for 36 BART-COL-005-CTLFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 41 (type SKEL/CNST) for 39 BART-COL-005-CTLFireability-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 5 (type SKEL/CNST) for BART-COL-005-CTLFireability-01
lola: result : false
lola: FINISHED task # 29 (type SKEL/CNST) for BART-COL-005-CTLFireability-09
lola: result : false
lola: FINISHED task # 41 (type SKEL/CNST) for BART-COL-005-CTLFireability-13
lola: result : false
lola: FINISHED task # 38 (type SKEL/CNST) for BART-COL-005-CTLFireability-12
lola: result : false
lola: FINISHED task # 20 (type SKEL/CNST) for BART-COL-005-CTLFireability-06
lola: result : false
lola: TR BINDINGS
lola: TR BINDINGS DONE
lola: Places: 11603, Transitions: 1615
lola: @ trans TooEarly
lola: @ trans MissStation
lola: @ trans TrainStop
lola: @ trans TrainStable
lola: @ trans TrainDecc
lola: @ trans TrainAcc
lola: @ trans AtStation
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-COL-005-CTLFireability-00: INITIAL false skeleton: preprocessing
BART-COL-005-CTLFireability-01: INITIAL false skeleton: preprocessing
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BART-COL-005-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BART-COL-005-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BART-COL-005-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BART-COL-005-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-15: LTL/CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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BART-COL-005-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-10: EG 0 0 0 0 1 0 0 0
BART-COL-005-CTLFireability-14: INITIAL 0 0 0 0 1 0 0 0
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lola: FINISHED task # 22 (type CNST) for BART-COL-005-CTLFireability-07
lola: result : false
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lola: LAUNCH INITIAL
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for BART-COL-005-CTLFireability-08
lola: result : true
lola: markings : 40
lola: fired transitions : 82
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 43 (type CNST) for BART-COL-005-CTLFireability-14
lola: result : true
lola: LAUNCH task # 31 (type EXCL) for 30 BART-COL-005-CTLFireability-10
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lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for BART-COL-005-CTLFireability-10
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: LAUNCH task # 13 (type EXCL) for 12 BART-COL-005-CTLFireability-04
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lola: FINISHED task # 13 (type EXCL) for BART-COL-005-CTLFireability-04
lola: result : false
lola: markings : 180
lola: fired transitions : 179
lola: time used : 0.000000
lola: memory pages used : 1
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lola: LAUNCH task # 46 (type EXCL) for 45 BART-COL-005-CTLFireability-15
lola: time limit : 1101 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for BART-COL-005-CTLFireability-15
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 0/1652 1/32 BART-COL-005-CTLFireability-05 26215 m, 5243 m/sec, 32629 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: CANCELED task # 16 (type EXCL) for BART-COL-005-CTLFireability-05 (memory limit exceeded)
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lola: LAUNCH task # 10 (type EXCL) for 9 BART-COL-005-CTLFireability-03
lola: time limit : 3250 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for BART-COL-005-CTLFireability-03
lola: result : true
lola: markings : 41
lola: fired transitions : 82
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-COL-005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is BART-COL-005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r004-tall-162037986200540"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/BART-COL-005.tgz
mv BART-COL-005 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;