About the Execution of LoLA for AirplaneLD-COL-0500
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
1944.048 | 285352.00 | 286976.00 | 680.40 | FTFFFTTTFT?FTFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r004-tall-162037985700212.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is AirplaneLD-COL-0500, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r004-tall-162037985700212
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 536K
-rw-r--r-- 1 mcc users 25K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 174K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.2K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 76K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 15:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 15:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 28 15:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 15:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Mar 23 01:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 23 01:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 22 09:41 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K Mar 22 09:41 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 09:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 5 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 109K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-00
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-01
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-02
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-03
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-04
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-05
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-06
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-07
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-08
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-09
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-10
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-11
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-12
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-13
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-14
FORMULA_NAME AirplaneLD-COL-0500-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620724134902
starting LoLA
BK_INPUT AirplaneLD-COL-0500
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA AirplaneLD-COL-0500-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0500-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620724420254
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:196
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:207
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: LAUNCH INITIAL
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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AirplaneLD-COL-0500-CTLFireability-06: LTL/CTL 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-09: EF 0 0 0 0 2 0 0 2
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-15: AG 0 0 0 0 4 0 0 0
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AirplaneLD-COL-0500-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-09: EF 0 0 0 0 2 0 0 2
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-15: AG 0 0 0 0 4 0 0 0
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AirplaneLD-COL-0500-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-09: EF 0 0 0 0 2 0 0 2
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-15: AG 0 0 0 0 4 0 0 0
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AirplaneLD-COL-0500-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-09: EF 0 0 0 0 2 0 0 2
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-09: EF 0 0 0 0 2 0 0 2
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-09: EF 0 0 0 0 2 0 0 2
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-07: INITIAL 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 0 0
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68 EG EXCL 4/1147 2/32 AirplaneLD-COL-0500-CTLFireability-10 82463 m, 16492 m/sec, 193803 t fired, .
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68 EG EXCL 9/1147 3/32 AirplaneLD-COL-0500-CTLFireability-10 187145 m, 20936 m/sec, 439619 t fired, .
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68 EG EXCL 19/1147 6/32 AirplaneLD-COL-0500-CTLFireability-10 396234 m, 20943 m/sec, 931970 t fired, .
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68 EG EXCL 29/1147 9/32 AirplaneLD-COL-0500-CTLFireability-10 605925 m, 21070 m/sec, 1428569 t fired, .
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AirplaneLD-COL-0500-CTLFireability-08: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-09: EF true state space
AirplaneLD-COL-0500-CTLFireability-11: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-12: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-13: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-14: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-15: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0500-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-06: LTL/CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
68 EG EXCL 109/1147 29/32 AirplaneLD-COL-0500-CTLFireability-10 1994115 m, 15758 m/sec, 4998638 t fired, .
Time elapsed: 266 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0500-CTLFireability-00: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-02: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-03: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-04: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-05: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-07: INITIAL true preprocessing
AirplaneLD-COL-0500-CTLFireability-08: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-09: EF true state space
AirplaneLD-COL-0500-CTLFireability-11: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-12: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-13: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-14: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-15: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0500-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-06: LTL/CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
68 EG EXCL 114/1147 30/32 AirplaneLD-COL-0500-CTLFireability-10 2070728 m, 15322 m/sec, 5214842 t fired, .
Time elapsed: 271 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0500-CTLFireability-00: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-02: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-03: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-04: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-05: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-07: INITIAL true preprocessing
AirplaneLD-COL-0500-CTLFireability-08: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-09: EF true state space
AirplaneLD-COL-0500-CTLFireability-11: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-12: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-13: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-14: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-15: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0500-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-06: LTL/CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
68 EG EXCL 119/1147 31/32 AirplaneLD-COL-0500-CTLFireability-10 2148017 m, 15457 m/sec, 5433870 t fired, .
Time elapsed: 276 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0500-CTLFireability-00: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-02: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-03: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-04: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-05: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-07: INITIAL true preprocessing
AirplaneLD-COL-0500-CTLFireability-08: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-09: EF true state space
AirplaneLD-COL-0500-CTLFireability-11: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-12: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-13: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-14: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-15: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0500-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-06: LTL/CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
68 EG EXCL 124/1147 32/32 AirplaneLD-COL-0500-CTLFireability-10 2224507 m, 15298 m/sec, 5653170 t fired, .
Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 68 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0500-CTLFireability-00: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-02: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-03: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-04: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-05: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-07: INITIAL true preprocessing
AirplaneLD-COL-0500-CTLFireability-08: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-09: EF true state space
AirplaneLD-COL-0500-CTLFireability-11: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-12: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-13: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-14: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-15: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0500-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-06: LTL/CTL 0 1 0 0 1 0 0 0
AirplaneLD-COL-0500-CTLFireability-10: F 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 AirplaneLD-COL-0500-CTLFireability-06
lola: time limit : 1657 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-06
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-COL-0500-CTLFireability-01
lola: time limit : 3314 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for AirplaneLD-COL-0500-CTLFireability-01
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0500-CTLFireability-00: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-01: CTL true CTL model checker
AirplaneLD-COL-0500-CTLFireability-02: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-03: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-04: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-05: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-06: LTL/CTL true CTL model checker
AirplaneLD-COL-0500-CTLFireability-07: INITIAL true preprocessing
AirplaneLD-COL-0500-CTLFireability-08: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-09: EF true state space
AirplaneLD-COL-0500-CTLFireability-10: F unknown AGGR
AirplaneLD-COL-0500-CTLFireability-11: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-12: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-13: INITIAL false skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-14: INITIAL true skeleton: preprocessing
AirplaneLD-COL-0500-CTLFireability-15: AG false state space
Time elapsed: 286 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0500"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0500, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r004-tall-162037985700212"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0500.tgz
mv AirplaneLD-COL-0500 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;