MCC'2021- Execution of r308-tall-162132105200650

About the Execution of LoLA for UtilityControlRoom-PT-Z4T4N10

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
14643.676	3600000.00	560316.00	9189.00	?TTFT???F?FF?FTF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r308-tall-1621
Waiting for the VM to be ready (probing ssh)
................................................
==========================
Generated by BenchKit 2-4028
Executing tool lola
Input is UtilityControlRoom-PT-Z4T4N10,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r308-tall-162132105200650
================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.8M
-rw-r--r-- 1 mcc users 352K May 15 08:57
-rw-r--r-- 1 mcc users 1.5M May 15 08:57
-rw-r--r-- 1 mcc users 650K May 15 08:57
-rw-r--r-- 1 mcc users 2.4M May 15 08:57
-rw-r--r-- 1 mcc users 26K May 12 08:04
-rw-r--r-- 1 mcc users 87K May 12 08:04
-rw-r--r-- 1 mcc users 55K May 12 08:04
-rw-r--r-- 1 mcc users 154K May 12 08:04
-rw-r--r-- 1 mcc users 1 May 12 08:13
-rw-r--r-- 1 mcc users 29K May 12 04:39
-rw-r--r-- 1 mcc users 88K May 12 04:39
-rw-r--r-- 1 mcc users 49K May 11 18:15
-rw-r--r-- 1 mcc users 135K May 11 18:15
-rw-r--r-- 1 mcc users 8.9K May 12 04:43
-rw-r--r-- 1 mcc users 19K May 12 04:43
-rw-r--r-- 1 mcc users 5 May 12 08:13
-rw-r--r-- 1 mcc users 8 May 12 08:13
-rw-r--r-- 1 mcc users 6 May 12 08:13
-rw-r--r-- 1 mcc users 319K May 12 08:13

--------------------
content from stdout:

=== Data for post analysis generated by

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi
FORMULA_NAME UtilityControlRoom-PT-Z4T4N10-CTLFi

=== Now, execution of the tool begins

BK_START 1621389739795

starting LoLA
BK_INPUT UtilityControlRoom-PT-Z4T4N10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-13

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-08

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-10

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-03

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-02

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-15

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-14

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-04

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-01

FORMULA UtilityControlRoom-PT-Z4T4N10-CTLFireability-11

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/mod
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/mode
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: LAUNCH task # 102 (type SKEL/FNDP)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SKEL/EQUN)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 104 (type SKEL/SRCH)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: LAUNCH task # 105 (type SKEL/SRCH)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 104 (type SKEL/SRCH)
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 102 (type FNDP)
lola: CANCELED task # 103 (type EQUN)
lola: CANCELED task # 105 (type SRCH)
lola: FINISHED task # 103 (type SKEL/EQUN)
lola: result : unknown
lola: FINISHED task # 102 (type SKEL/FNDP)
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 50 (type CNST) for
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 50 (type CNST)
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 38 (type CNST) for
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 38 (type CNST)
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 44 (type CNST) for
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 44 (type CNST)
lola: result : false
lola: planning for (null) stopped (result
lola: planning for (null) stopped (result
lola: planning for (null) stopped (result
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.
lola: LAUNCH task # 106 (type SKEL/SRCH)
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 106 (type SKEL/SRCH)
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: LAUNCH task # 107 (type EXCL) for
lola: time limit : 96 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: FINISHED task # 107 (type EXCL)
lola: result : true
lola: markings : 63
lola: fired transitions : 63
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: LAUNCH task # 108 (type EXCL) for
lola: time limit : 101 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: FINISHED task # 108 (type EXCL)
lola: result : true
lola: markings : 61
lola: fired transitions : 61
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: LAUNCH task # 83 (type EXCL) for
lola: time limit : 118 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: FINISHED task # 83 (type EXCL)
lola: result : false
lola: markings : 974
lola: fired transitions : 1034
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for
lola: time limit : 131 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL)
lola: result : false
lola: markings : 274
lola: fired transitions : 430
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for
lola: time limit : 137 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: FINISHED task # 15 (type EXCL)
lola: result : true
lola: markings : 55
lola: fired transitions : 55
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: LAUNCH task # 98 (type EXCL) for
lola: time limit : 142 sec
lola: memory limit: 32 pages
lola: FINISHED task # 98 (type EXCL)
lola: result : false
lola: markings : 1800
lola: fired transitions : 3356
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 74 (type EXCL) for
lola: time limit : 154 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: LAUNCH task # 112 (type FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 115 (type SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: FINISHED task # 112 (type FNDP)
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: CANCELED task # 113 (type EQUN)
lola: CANCELED task # 115 (type SRCH)
lola: LAUNCH task # 117 (type FNDP) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type EQUN) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 120 (type SRCH) for
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 115 (type SRCH)
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 1.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.
lola: rewrite Frontend/Parser/formula_rewrite.
lola: Created skeleton in 1.000000 secs.
lola: FINISHED task # 113 (type EQUN)
lola: result : unknown
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 120 (type SRCH)
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 117 (type FNDP)
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 118 (type EQUN)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 5/254 3/32

Time elapsed: 43 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 10/254 5/32

Time elapsed: 48 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 15/254 7/32

Time elapsed: 53 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 20/254 9/32

Time elapsed: 58 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 118 (type EQUN)
lola: result : unknown
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 25/254 12/32

Time elapsed: 63 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 30/254 14/32

Time elapsed: 68 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 35/254 16/32

Time elapsed: 73 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 40/254 19/32

Time elapsed: 78 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 45/254 21/32

Time elapsed: 83 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 50/254 23/32

Time elapsed: 88 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 55/254 25/32

Time elapsed: 93 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 60/254 28/32

Time elapsed: 98 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 65/254 30/32

Time elapsed: 103 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
74 CTL EXCL 70/254 32/32

Time elapsed: 108 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 74 (type EXCL)
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 113 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 95 (type EXCL) for
lola: time limit : 268 sec
lola: memory limit: 32 pages
lola: FINISHED task # 95 (type EXCL)
lola: result : true
lola: markings : 7179
lola: fired transitions : 8303
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 71 (type EXCL) for
lola: time limit : 290 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
71 CTL EXCL 5/290 5/32

Time elapsed: 118 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
71 CTL EXCL 10/290 9/32

Time elapsed: 123 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
71 CTL EXCL 15/290 13/32

Time elapsed: 128 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
71 CTL EXCL 20/290 16/32

Time elapsed: 133 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
71 CTL EXCL 25/290 20/32

Time elapsed: 138 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
71 CTL EXCL 30/290 24/32

Time elapsed: 143 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
71 CTL EXCL 35/290 28/32

Time elapsed: 148 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
71 CTL EXCL 40/290 32/32

Time elapsed: 153 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 71 (type EXCL)
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 158 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 68 (type EXCL) for
lola: time limit : 312 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type EXCL)
lola: result : true
lola: markings : 10
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 66 (type EXCL) for
lola: time limit : 344 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL)
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for
lola: time limit : 382 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL)
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for
lola: time limit : 430 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 5/430 4/32

Time elapsed: 163 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 10/430 8/32

Time elapsed: 168 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 15/430 11/32

Time elapsed: 173 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 20/430 14/32

Time elapsed: 178 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 25/430 17/32

Time elapsed: 183 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 30/430 20/32

Time elapsed: 188 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 35/430 23/32

Time elapsed: 193 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 40/430 25/32

Time elapsed: 198 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 45/430 28/32

Time elapsed: 203 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
26 CTL EXCL 50/430 31/32

Time elapsed: 208 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 26 (type EXCL)
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 213 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 21 (type EXCL) for
lola: time limit : 483 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL)
lola: result : true
lola: markings : 70
lola: fired transitions : 142
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for
lola: time limit : 564 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL)
lola: result : true
lola: markings : 217
lola: fired transitions : 248
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 109 (type EXCL) for
lola: time limit : 677 sec
lola: memory limit: 32 pages
lola: FINISHED task # 109 (type EXCL)
lola: result : true
lola: markings : 59
lola: fired transitions : 59
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for
lola: time limit : 846 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 5/846 5/32

Time elapsed: 218 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 10/846 8/32

Time elapsed: 223 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 15/846 12/32

Time elapsed: 228 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 20/846 15/32

Time elapsed: 233 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 25/846 18/32

Time elapsed: 238 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 30/846 21/32

Time elapsed: 243 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 35/846 24/32

Time elapsed: 248 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 40/846 27/32

Time elapsed: 253 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 45/846 29/32

Time elapsed: 258 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
9 AGEF EXCL 50/846 32/32

Time elapsed: 263 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 9 (type EXCL) for
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 268 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 110 (type EXCL) for
lola: time limit : 1110 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 5/1110 4/32

Time elapsed: 273 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 10/1110 8/32

Time elapsed: 278 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 15/1110 11/32

Time elapsed: 283 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 20/1110 14/32

Time elapsed: 288 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 25/1110 16/32

Time elapsed: 293 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 30/1110 19/32

Time elapsed: 298 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 35/1110 22/32

Time elapsed: 303 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 40/1110 25/32

Time elapsed: 308 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 45/1110 27/32

Time elapsed: 313 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 50/1110 30/32

Time elapsed: 318 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
110 AGEF EXCL 55/1110 32/32

Time elapsed: 323 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 110 (type EXCL)
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 328 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 80 (type EXCL) for
lola: time limit : 1636 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 5/1636 2/32

Time elapsed: 333 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 10/1636 4/32

Time elapsed: 338 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 15/1636 6/32

Time elapsed: 343 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 20/1636 7/32

Time elapsed: 348 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 25/1636 9/32

Time elapsed: 353 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 30/1636 10/32

Time elapsed: 358 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 35/1636 12/32

Time elapsed: 363 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 40/1636 14/32

Time elapsed: 368 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 45/1636 15/32

Time elapsed: 373 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 50/1636 16/32

Time elapsed: 378 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 55/1636 18/32

Time elapsed: 383 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 60/1636 19/32

Time elapsed: 388 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 65/1636 21/32

Time elapsed: 393 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 70/1636 22/32

Time elapsed: 398 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 75/1636 24/32

Time elapsed: 403 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 80/1636 25/32

Time elapsed: 408 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 85/1636 27/32

Time elapsed: 413 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 90/1636 28/32

Time elapsed: 418 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 95/1636 29/32

Time elapsed: 423 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 100/1636 31/32

Time elapsed: 428 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
80 CTL EXCL 105/1636 32/32

Time elapsed: 433 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 80 (type EXCL)
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 438 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 89 (type EXCL) for
lola: time limit : 3162 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 5/3162 3/32

Time elapsed: 443 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 10/3162 5/32

Time elapsed: 448 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 15/3162 7/32

Time elapsed: 453 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 20/3162 8/32

Time elapsed: 458 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 25/3162 10/32

Time elapsed: 463 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 30/3162 12/32

Time elapsed: 468 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 35/3162 14/32

Time elapsed: 473 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 40/3162 15/32

Time elapsed: 478 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 45/3162 17/32

Time elapsed: 483 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 50/3162 19/32

Time elapsed: 488 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 55/3162 20/32

Time elapsed: 493 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 60/3162 22/32

Time elapsed: 498 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 65/3162 24/32

Time elapsed: 503 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 70/3162 25/32

Time elapsed: 508 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 75/3162 27/32

Time elapsed: 513 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 80/3162 29/32

Time elapsed: 518 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 85/3162 30/32

Time elapsed: 523 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA
89 CTL EXCL 90/3162 32/32

Time elapsed: 528 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 89 (type EXCL)
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 533 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 538 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 543 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 548 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 553 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 558 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 563 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 568 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 573 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 578 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 583 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 588 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 593 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 598 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 603 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 608 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 613 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 618 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 623 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 628 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 633 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 638 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 643 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 648 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 653 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 658 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 663 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 668 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 673 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 678 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 683 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 688 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 693 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 698 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 703 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 708 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 713 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 718 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 723 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 728 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 733 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 738 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 743 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 748 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 753 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 758 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 763 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 768 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 773 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 778 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 783 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 788 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 793 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 798 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 803 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 808 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 813 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 818 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 823 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 828 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 833 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 838 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 843 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 848 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 853 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 858 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 863 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 868 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 873 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 878 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 883 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 888 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 893 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 898 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 903 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 908 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 913 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 918 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 923 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 928 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 933 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 938 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 943 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 948 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 953 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 958 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 963 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 968 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 973 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 978 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 983 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 988 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 993 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 998 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1003 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1008 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1013 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1018 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1023 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1028 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1033 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1038 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1043 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1048 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1053 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1058 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1063 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1068 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1073 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1078 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1083 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1088 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1093 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1098 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1103 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1108 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1113 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1118 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1123 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1128 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1133 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1138 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1143 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1148 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1153 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1158 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1163 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1168 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1173 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1178 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1183 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1188 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1193 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1198 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1203 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1208 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1213 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1218 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1223 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1228 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1233 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1238 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1243 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1248 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1253 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1258 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1263 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1268 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1273 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1278 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1283 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1288 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1293 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1298 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1303 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1308 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1313 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1318 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1323 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1328 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1333 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1338 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1343 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1348 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1353 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1358 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1363 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1368 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1373 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1378 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1383 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1388 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1393 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1398 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1403 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1408 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1413 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1418 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1423 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1428 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1433 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1438 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1443 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1448 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1453 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1458 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1463 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1468 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1473 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1478 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1483 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1488 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1493 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1498 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1503 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1508 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1513 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1518 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1523 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1528 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1533 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1538 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1543 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1548 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1553 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1558 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1563 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1568 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1573 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1578 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1583 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1588 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1593 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1598 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1603 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1608 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1613 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1618 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1623 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1628 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1633 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1638 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1643 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1648 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1653 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1658 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1663 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1668 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1673 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1678 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1683 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1688 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1693 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1698 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1703 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1708 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1713 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1718 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1723 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1728 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1733 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1738 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1743 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1748 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1753 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1758 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1763 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1768 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1773 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1778 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1783 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1788 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1793 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1798 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1803 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1808 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1813 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1818 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1823 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1828 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1833 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1838 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1843 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1848 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1853 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1858 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1863 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1868 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1873 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1878 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1883 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1888 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1893 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1898 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1903 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1908 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1913 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1918 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1923 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1928 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1933 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1938 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1943 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1948 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1953 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1958 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1963 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1968 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1973 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1978 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1983 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1988 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1993 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 1998 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2003 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2008 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2013 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2018 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2023 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2028 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2033 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2038 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2043 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2048 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2053 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2058 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2063 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2068 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2073 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2078 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2083 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2088 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2093 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2098 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2103 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2108 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2113 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2118 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2123 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2128 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2133 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2138 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2143 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2148 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2153 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2158 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2163 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2168 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2173 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2178 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2183 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2188 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2193 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2198 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2203 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2208 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2213 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2218 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2223 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2228 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2233 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2238 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2243 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2248 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2253 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2258 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2263 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2268 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2273 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2278 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2283 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2288 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2293 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2298 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2303 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2308 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2313 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2318 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2323 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2328 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2333 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2338 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2343 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2348 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2353 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2358 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2363 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2368 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2373 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2378 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2383 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2388 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2393 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2398 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2403 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2408 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2413 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2418 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2423 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2428 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2433 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2438 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-13:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-14:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-15:

PENDING FORMULAS: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-00:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-05:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-06:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-07:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-09:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA

Time elapsed: 2443 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY
UtilityControlRoom-PT-Z4T4N10-CTLFireability-01:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-02:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-03:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-04:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-08:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-10:
UtilityControlRoom-PT-Z4T4N10-CTLFireability-11:

========== file over 1MB has been truncated
retrieve it from the run archives if needed
32105200650.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... =========================================== examination is CTLFireability ===================== CTLCardinality.txt CTLCardinality.xml CTLFireability.txt CTLFireability.xml LTLCardinality.txt LTLCardinality.xml LTLFireability.txt LTLFireability.xml NewModel ReachabilityCardinality.txt ReachabilityCardinality.xml ReachabilityFireability.txt ReachabilityFireability.xml UpperBounds.txt UpperBounds.xml equiv_col instance iscolored model.pnml BenchKit (invocation template) vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT el.pnml l.pnml /CTLFireability.xml k:322 k:328 k:325 k:331 k:296 k:400 k:400 k:322 k:328 k:325 k:331 k:296 k:314 k:325 k:331 k:296 k:325 k:331 k:322 k:328 k:299 k:544 k:457 k:317 k:314 k:322 k:328 k:296 k:322 k:328 k:325 k:337 k:296 k:296 k:322 k:328 k:296 k:325 k:337 k:296 k:296 k:253 k:553 k:553 k:250 k:325 k:328 k:317 k:296 k:322 k:331 k:325 k:334 k:296 k:322 k:331 k:314 k:299 k:325 k:328 k:322 k:334 k:299 k:325 k:331 k:296 k:322 k:334 k:296 k:253 k:325 k:328 k:317 k:322 k:328 k:299 k:317 k:322 k:337 k:296 k:296 k:317 k:325 k:334 k:299 k:322 k:334 k:296 k:322 k:331 k:314 k:325 k:331 k:296 k:314 k:325 k:340 k:299 k:299 k:314 k:322 k:334 k:296 k:325 k:334 k:299 k:325 k:328 k:317 k:322 k:328 k:299 k:317 k:322 k:337 k:296 k:296 k:317 k:325 k:334 k:299 k:322 k:334 k:296 k:314 k:325 k:328 k:322 k:337 k:296 k:296 k:317 k:322 k:331 k:296 k:325 k:334 k:296 k:317 k:322 k:331 k:325 k:340 k:299 k:299 k:314 k:325 k:328 k:299 k:322 k:334 k:299 k:325 k:334 k:322 k:334 k:322 k:328 k:296 k:322 k:334 k:296 k:317 k:322 k:331 k:296 k:296 k:478 k:550 k:550 k:253 k:253 k:325 k:337 k:296 k:296 k:253 k:253 k:253 k:314 k:317 k:322 k:337 k:322 k:331 k:296 k:296 k:317 k:325 k:337 k:296 k:296 k:317 k:325 k:331 k:314 k:325 k:334 k:296 k:296 k:325 k:328 k:322 k:334 k:296 k:322 k:331 k:296 k:454 k:250 k:253 k:460 k:400 k:325 k:331 k:325 k:328 k:296 k:325 k:337 k:296 k:296 k:317 k:296 k:325 k:328 k:296 k:550 k:325 k:328 k:314 k:322 k:334 k:299 k:322 k:334 k:322 k:331 k:299 k:322 k:337 k:322 k:337 k:322 k:331 k:296 k:296 k:314 k:322 k:337 k:296 k:322 k:337 k:296 k:296 k:296 k:325 k:328 k:296 k:322 k:331 k:314 k:296 k:322 k:334 k:296 k:325 k:328 k:317 k:299 k:325 k:334 k:299 k:721 k:788 k:721 k:788 k:721 k:788 for 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 for 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 for 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 k:721 k:788 for 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 (obsolete) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 (obsolete) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 (obsolete) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 places removed 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 already fixed). already fixed). already fixed). k:812 for 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 k:749 k:788 91 UtilityControlRoom-PT-Z4T4N10-CTLFireability-13 k:806 k:808 k:809 k:815 k:809 k:808 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-13 k:808 k:810 k:810 k:810 k:810 k:813 k:734 k:788 k:734 k:787 76 UtilityControlRoom-PT-Z4T4N10-CTLFireability-08 k:807 k:811 k:808 k:807 k:808 k:807 k:811 k:806 k:815 k:806 k:806 k:815 k:807 k:807 k:807 k:811 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-08 k:806 k:810 k:812 k:807 k:811 82 UtilityControlRoom-PT-Z4T4N10-CTLFireability-10 k:807 k:806 k:812 k:811 k:807 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-10 17 UtilityControlRoom-PT-Z4T4N10-CTLFireability-03 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-03 14 UtilityControlRoom-PT-Z4T4N10-CTLFireability-02 k:726 k:788 k:814 k:808 k:811 k:807 k:811 k:812 k:808 k:812 k:806 k:807 k:812 k:811 k:811 k:812 k:808 k:810 k:815 k:812 k:813 k:807 k:811 k:808 k:806 k:811 k:814 k:813 k:814 k:814 k:815 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-02 k:811 k:814 k:809 k:812 k:808 k:811 k:809 k:811 97 UtilityControlRoom-PT-Z4T4N10-CTLFireability-15 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-15 73 UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 k:721 k:788 k:703 k:806 k:807 k:812 k:808 k:721 k:788 k:721 k:788 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 k:721 k:788 k:721 k:787 k:721 k:787 k:812 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 k:807 k:811 k:808 k:811 k:721 k:787 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 (obsolete) for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 (obsolete) 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 k:721 k:787 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 (obsolete) VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 14 0 0 3 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 458277 m, 91655 m/sec, 841283 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 14 0 0 3 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 978438 m, 104032 m/sec, 1813500 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 14 0 0 3 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 1493744 m, 103061 m/sec, 2780046 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 14 0 0 3 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 2012660 m, 103783 m/sec, 3740782 t fired, . for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 2528841 m, 103236 m/sec, 4704842 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 3040815 m, 102394 m/sec, 5686221 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 3543607 m, 100558 m/sec, 6673316 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 4055414 m, 102361 m/sec, 7622176 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 4561711 m, 101259 m/sec, 8567251 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 5066283 m, 100914 m/sec, 9514060 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 5570249 m, 100793 m/sec, 10459657 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 6082548 m, 102459 m/sec, 11404515 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 6581644 m, 99819 m/sec, 12372716 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 7081080 m, 99887 m/sec, 13343279 t fired, . for UtilityControlRoom-PT-Z4T4N10-CTLFireability-07 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS 94 UtilityControlRoom-PT-Z4T4N10-CTLFireability-14 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-14 70 UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 578445 m, 115689 m/sec, 842610 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 1144525 m, 113216 m/sec, 1692311 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 1695688 m, 110232 m/sec, 2544285 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 2255451 m, 111952 m/sec, 3377434 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 2810123 m, 110934 m/sec, 4223546 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 3357144 m, 109404 m/sec, 5069674 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 3904810 m, 109533 m/sec, 5914975 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 4444263 m, 107890 m/sec, 6751901 t fired, . for UtilityControlRoom-PT-Z4T4N10-CTLFireability-06 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 4 0 0 15 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 23 UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 573518 m, 114703 m/sec, 1223341 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 1088580 m, 103012 m/sec, 2389062 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 1568327 m, 95949 m/sec, 3527144 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 2034986 m, 93331 m/sec, 4653120 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 2490647 m, 91132 m/sec, 5765257 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 2935556 m, 88981 m/sec, 6853535 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 3366218 m, 86132 m/sec, 7929516 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 3790487 m, 84853 m/sec, 8998102 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 4212183 m, 84339 m/sec, 10056811 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 1 0 18 0 0 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 4629127 m, 83388 m/sec, 11112380 t fired, . for UtilityControlRoom-PT-Z4T4N10-CTLFireability-05 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL false CTL model checker AGAF false state space /EFEG CTL false CTL model checker F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 2 0 0 8 0 0 2 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGAF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS 20 UtilityControlRoom-PT-Z4T4N10-CTLFireability-04 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-04 11 UtilityControlRoom-PT-Z4T4N10-CTLFireability-01 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-01 85 UtilityControlRoom-PT-Z4T4N10-CTLFireability-11 for UtilityControlRoom-PT-Z4T4N10-CTLFireability-11 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 663363 m, 132672 m/sec, 1428647 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 1253875 m, 118102 m/sec, 2773470 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 1786659 m, 106556 m/sec, 4051756 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 2304840 m, 103636 m/sec, 5312856 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 2811651 m, 101362 m/sec, 6548366 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 3299116 m, 97493 m/sec, 7760268 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 3774889 m, 95154 m/sec, 8958531 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 4248412 m, 94704 m/sec, 10148435 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 4714195 m, 93156 m/sec, 11329648 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 1 0 8 0 0 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 5177507 m, 92662 m/sec, 12502946 t fired, . UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 1 0 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS 0 UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 588916 m, 117783 m/sec, 1257632 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 1119850 m, 106186 m/sec, 2463871 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 1613243 m, 98678 m/sec, 3635636 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 2094437 m, 96238 m/sec, 4798128 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 2563394 m, 93791 m/sec, 5943951 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 3023138 m, 91948 m/sec, 7071063 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 3466278 m, 88628 m/sec, 8178661 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 3903048 m, 87354 m/sec, 9281557 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 4338943 m, 87179 m/sec, 10380451 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 4769879 m, 86187 m/sec, 11466591 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 1 0 8 0 1 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 5197563 m, 85536 m/sec, 12554623 t fired, . for UtilityControlRoom-PT-Z4T4N10-CTLFireability-00 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS 79 UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 348375 m, 69675 m/sec, 2782204 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 676463 m, 65617 m/sec, 5436358 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 995881 m, 63883 m/sec, 8051039 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 1309648 m, 62753 m/sec, 10630743 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 1619433 m, 61957 m/sec, 13190996 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 1927003 m, 61514 m/sec, 15730329 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 2231048 m, 60809 m/sec, 18259851 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 2532771 m, 60344 m/sec, 20778652 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 2832248 m, 59895 m/sec, 23274887 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 3127106 m, 58971 m/sec, 25752804 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 3422537 m, 59086 m/sec, 28235800 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 3716163 m, 58725 m/sec, 30707473 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 4009357 m, 58638 m/sec, 33173094 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 4300563 m, 58241 m/sec, 35627825 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 4590486 m, 57984 m/sec, 38072014 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 4877843 m, 57471 m/sec, 40504215 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 5164295 m, 57290 m/sec, 42935232 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 5452075 m, 57556 m/sec, 45369119 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 5736216 m, 56828 m/sec, 47782410 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 6021529 m, 57062 m/sec, 50203761 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 6304579 m, 56610 m/sec, 52619857 t fired, . for UtilityControlRoom-PT-Z4T4N10-CTLFireability-09 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS 88 UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 409457 m, 81891 m/sec, 2796568 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 791332 m, 76375 m/sec, 5487146 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 1161114 m, 73956 m/sec, 8122443 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 1519788 m, 71734 m/sec, 10699238 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 1872885 m, 70619 m/sec, 13256638 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 2222503 m, 69923 m/sec, 15794268 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 2568335 m, 69166 m/sec, 18309201 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 2909996 m, 68332 m/sec, 20808118 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 3248132 m, 67627 m/sec, 23288806 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 3586386 m, 67650 m/sec, 25763667 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 3920760 m, 66874 m/sec, 28224123 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 4251883 m, 66224 m/sec, 30674431 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 4585004 m, 66624 m/sec, 33106876 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 4914904 m, 65980 m/sec, 35537971 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 5242257 m, 65470 m/sec, 37960893 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 5567974 m, 65143 m/sec, 40373201 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 5893473 m, 65099 m/sec, 42774805 t fired, . VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 6215282 m, 64361 m/sec, 45168299 t fired, . for UtilityControlRoom-PT-Z4T4N10-CTLFireability-12 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG F false state space / EG CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CONJ 0 0 0 0 8 0 2 2 DISJ 0 0 0 0 18 0 1 2 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker AGAF false state space /EFEG CTL false CTL model checker AGAF false state space /EFEG ======

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z4T4N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z4T4N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-162132105200650"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z4T4N10.tgz
mv UtilityControlRoom-PT-Z4T4N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;