About the Execution of LoLA for UtilityControlRoom-PT-Z2T4N10
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
3882.728 | 268207.00 | 261060.00 | 662.90 | T?TF?FFFFTFTT?FF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r308-tall-162132105100586.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is UtilityControlRoom-PT-Z2T4N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r308-tall-162132105100586
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.9M
-rw-r--r-- 1 mcc users 115K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 502K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 165K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 661K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 17K May 12 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 61K May 12 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 12 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 52K May 12 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 9.6K May 12 04:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 30K May 12 04:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 22K May 11 18:10 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 71K May 11 18:10 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.4K May 12 04:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 9.0K May 12 04:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 8 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 116K May 12 08:13 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z2T4N10-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1621384483234
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z2T4N10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T4N10-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621384751441
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 105/199 29/32 UtilityControlRoom-PT-Z2T4N10-CTLFireability-04 5751933 m, 51327 m/sec, 24431419 t fired, .
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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13 CTL EXCL 110/199 30/32 UtilityControlRoom-PT-Z2T4N10-CTLFireability-04 6006171 m, 50847 m/sec, 25579104 t fired, .
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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lola: result : false
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lola: fired transitions : 282429
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lola: result : true
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 34/267 28/32 UtilityControlRoom-PT-Z2T4N10-CTLFireability-13 5365568 m, 140432 m/sec, 13802747 t fired, .
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-14: CONJ false CTL model checker
UtilityControlRoom-PT-Z2T4N10-CTLFireability-15: CTL false CTL model checker
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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lola: result : true
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lola: time used : 0.000000
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lola: fired transitions : 454
lola: time used : 0.000000
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-03: EG 0 1 0 0 1 0 0 0
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UtilityControlRoom-PT-Z2T4N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N10-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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lola: fired transitions : 42
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FINAL RESULTS
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T4N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z2T4N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-162132105100586"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T4N10.tgz
mv UtilityControlRoom-PT-Z2T4N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;