fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r308-tall-162132104600306
Last Updated
Jun 28, 2021

About the Execution of LoLA for TwoPhaseLocking-PT-nC00500vD

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3327.067 140261.00 127912.00 324.80 TT?TFFFT?FTTF??T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r308-tall-162132104600306.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is TwoPhaseLocking-PT-nC00500vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r308-tall-162132104600306
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 336K
-rw-r--r-- 1 mcc users 12K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.1K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 76K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 12 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 12 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 12 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 12 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 3.7K May 12 04:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 12 04:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 11 18:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 11 18:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 12 04:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 12 04:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 10 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 4.6K May 12 08:13 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00500vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1621370147224

starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00500vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00500vD-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621370287485

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00500vD-CTLFireability-00
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-00
lola: result : true
lola: markings : 1001
lola: fired transitions : 1001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC00500vD-CTLFireability-03
lola: time limit : 116 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-03
lola: result : true
lola: markings : 4977
lola: fired transitions : 6219
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 40 TwoPhaseLocking-PT-nC00500vD-CTLFireability-12
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 47 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-12
lola: result : false
lola: markings : 1000
lola: fired transitions : 2748
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC00500vD-CTLFireability-04
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-04
lola: result : false
lola: markings : 1755
lola: fired transitions : 10004
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00500vD-CTLFireability-01
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 69 (type FNDP) for 37 TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type EQUN) for 37 TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SRCH) for 37 TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 74 (type SRCH) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 77 (type FNDP) for 58 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-01
lola: result : true
lola: markings : 1001
lola: fired transitions : 4254
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 63 (type EXCL) for 58 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 77 (type FNDP) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-14
lola: result : true
lola: fired transitions : 249
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: try reading problem file /home/mcc/execution/CTLFireability-72.sara.
lola: LAUNCH task # 70 (type FNDP) for 18 TwoPhaseLocking-PT-nC00500vD-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 70 (type FNDP) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-06
lola: result : true
lola: fired transitions : 249
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0

lola: FINISHED task # 72 (type EQUN) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
lola: result : true
lola: CANCELED task # 69 (type FNDP) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-11 (obsolete)
lola: FINISHED task # 69 (type FNDP) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-11
lola: result : unknown
lola: fired transitions : 310466
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 1 0 3 0 0 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 5/400 8/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14 1836738 m, 367347 m/sec, 6962475 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 1 0 3 0 0 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 10/400 14/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14 3345752 m, 301802 m/sec, 12983019 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 1 0 3 0 0 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 15/400 20/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14 4737598 m, 278369 m/sec, 18630511 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 1 0 3 0 0 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 20/400 25/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14 6069835 m, 266447 m/sec, 24075976 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 1 0 3 0 0 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 25/400 30/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-14 7355253 m, 257083 m/sec, 29360877 t fired, .

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lola: CANCELED task # 63 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 32 (type EXCL) for 31 TwoPhaseLocking-PT-nC00500vD-CTLFireability-09
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-09
lola: result : false
lola: markings : 2746
lola: fired transitions : 8985
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08
lola: time limit : 510 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/510 8/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08 1777755 m, 355551 m/sec, 8542704 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/510 13/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08 3187638 m, 281976 m/sec, 15581361 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/510 18/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08 4466188 m, 255710 m/sec, 22051676 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 20/510 23/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08 5559783 m, 218719 m/sec, 27611931 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 25/510 27/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08 6684238 m, 224891 m/sec, 33355875 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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29 CTL EXCL 30/510 32/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-08 7859283 m, 235009 m/sec, 39374682 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 5/707 6/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 1388189 m, 277637 m/sec, 7981177 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 10/707 11/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 2584078 m, 239177 m/sec, 15091193 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 15/707 15/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 3701890 m, 223562 m/sec, 21828691 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 20/707 20/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 4777342 m, 215090 m/sec, 28349152 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 25/707 24/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 5822487 m, 209029 m/sec, 34707878 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 30/707 28/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 6842609 m, 204024 m/sec, 40939150 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/707 32/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-02 7846616 m, 200801 m/sec, 47080100 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 5/873 7/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 1578219 m, 315643 m/sec, 7532393 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 10/873 12/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 2924176 m, 269191 m/sec, 14209675 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 15/873 17/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 4161900 m, 247544 m/sec, 20450872 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 20/873 22/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 5346742 m, 236968 m/sec, 26470421 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 25/873 27/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 6495496 m, 229750 m/sec, 32331721 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 30/873 31/32 TwoPhaseLocking-PT-nC00500vD-CTLFireability-13 7618924 m, 224685 m/sec, 38075028 t fired, .

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TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ 0 0 0 0 3 0 1 3
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 35 (type EXCL) for 34 TwoPhaseLocking-PT-nC00500vD-CTLFireability-10
lola: time limit : 1153 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-10
lola: result : true
lola: markings : 32884
lola: fired transitions : 102656
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 TwoPhaseLocking-PT-nC00500vD-CTLFireability-07
lola: time limit : 1730 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-07
lola: result : true
lola: markings : 1005
lola: fired transitions : 3010
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 66 (type EXCL) for 65 TwoPhaseLocking-PT-nC00500vD-CTLFireability-15
lola: time limit : 3460 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL) for TwoPhaseLocking-PT-nC00500vD-CTLFireability-15
lola: result : true
lola: markings : 2507
lola: fired transitions : 3521
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00500vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-02: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-03: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC00500vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-06: CONJ false findpath
TwoPhaseLocking-PT-nC00500vD-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-08: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-11: EF true state equation
TwoPhaseLocking-PT-nC00500vD-CTLFireability-12: CONJ false CTL model checker
TwoPhaseLocking-PT-nC00500vD-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC00500vD-CTLFireability-14: CONJ unknown CONJ
TwoPhaseLocking-PT-nC00500vD-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00500vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC00500vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-162132104600306"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00500vD.tgz
mv TwoPhaseLocking-PT-nC00500vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;