MCC'2021- Execution of r308-tall-162132104400197

About the Execution of LoLA for ServersAndClients-PT-400080

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
15775.848	651648.00	1505613.00	1021.00	T??F???F?F??FFT?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-inp
Waiting for the VM to
...............................
=========
Generated by BenchKit 2-4028
Executing tool lola
Input is ServersAndClients-PT-400080,
Time confinement is
Memory confinement
Number of cores is 4
Run identifier is
===============================

--------------------
preparation of the directory
/home/mcc/execution
total 63M
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
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-rw-r--r-- 1 mcc users

--------------------
content from stdout:

=== Data for post analysis

The expected result is
BOOL_VECTOR

here is the order used
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-
FORMULA_NAME ServersAndClients-

=== Now, execution of

BK_START 1621363463285

starting LoLA
BK_INPUT ServersAndClients-PT-4
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchK
current directory: /home/mcc/ex
LTLFireability

FORMULA ServersAndClients-PT-400080-00

FORMULA ServersAndClients-PT-400080-13

FORMULA ServersAndClients-PT-400080-12

FORMULA ServersAndClients-PT-400080-07

FORMULA ServersAndClients-PT-400080-14

FORMULA ServersAndClients-PT-400080-03

FORMULA ServersAndClients-PT-400080-09

BK_STOP 1621364114933

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file
lola: reading net from
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file
lola: Reading formula.
lola: Using XML format
lola: reading XML formula
lola: reading formula
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: RELEASE
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: RELEASE
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lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
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lola: rewrite Frontend/Parser
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lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: rewrite Frontend/Parser
lola: Created skeleton
lola: RELEASE
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Rule S: 0 transitions
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/home/mcc/BenchKit/BenchKit_head.sh:
ut.r308-tall-162132104400197.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off be ready (probing ssh) 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.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. ============================================================ examination is LTLFireability 3600 seconds is 16384 MBytes r308-tall-162132104400197 ====================================== to be used: 13K May 15 08:57 CTLCardinality.txt 89K May 15 08:57 CTLCardinality.xml 17K May 15 08:57 CTLFireability.txt 113K May 15 08:57 CTLFireability.xml 3.9K May 12 08:02 LTLCardinality.txt 28K May 12 08:02 LTLCardinality.xml 2.4K May 12 08:02 LTLFireability.txt 17K May 12 08:02 LTLFireability.xml 1 May 12 08:13 NewModel 3.4K May 11 20:31 ReachabilityCardinality.txt 17K May 11 20:31 ReachabilityCardinality.xml 2.9K May 11 17:33 ReachabilityFireability.txt 17K May 11 17:33 ReachabilityFireability.xml 1.5K May 12 04:43 UpperBounds.txt 3.5K May 12 04:43 UpperBounds.xml 6 May 12 08:13 equiv_col 7 May 12 08:13 instance 6 May 12 08:13 iscolored 62M May 12 08:13 model.pnml generated by BenchKit (invocation template) a vector of booleans to build the result vector(from text file) PT-400080-00 PT-400080-01 PT-400080-02 PT-400080-03 PT-400080-04 PT-400080-05 PT-400080-06 PT-400080-07 PT-400080-08 PT-400080-09 PT-400080-10 PT-400080-11 PT-400080-12 PT-400080-13 PT-400080-14 PT-400080-15 the tool begins 00080 it/bin ecution TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT (--pnmlnet) /home/mcc/execution/model.pnml place/transition net /home/mcc/execution/model.pnml (--xmlformula) from /home/mcc/execution/LTLFireability.xml /formula_rewrite.k:352 /formula_rewrite.k:334 /formula_rewrite.k:328 /formula_rewrite.k:296 /formula_rewrite.k:317 /formula_rewrite.k:296 /formula_rewrite.k:337 /formula_rewrite.k:334 /formula_rewrite.k:296 /formula_rewrite.k:296 /formula_rewrite.k:436 /formula_rewrite.k:355 /formula_rewrite.k:379 /formula_rewrite.k:373 /formula_rewrite.k:314 /formula_rewrite.k:331 /formula_rewrite.k:328 /formula_rewrite.k:296 /formula_rewrite.k:328 /formula_rewrite.k:317 /formula_rewrite.k:296 /formula_rewrite.k:334 /formula_rewrite.k:328 /formula_rewrite.k:296 /formula_rewrite.k:317 /formula_rewrite.k:328 /formula_rewrite.k:296 /formula_rewrite.k:317 /formula_rewrite.k:328 /formula_rewrite.k:331 /formula_rewrite.k:299 /formula_rewrite.k:331 /formula_rewrite.k:314 /formula_rewrite.k:299 /formula_rewrite.k:334 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LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE 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16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 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0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 VALUE PRODUCED BY LTL true skeleton: LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker LTL false LTL model checker CONJ false preprocessing LTL true LTL model checker IDL ACT RUN SUS FIN C/T C/M OBS LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 LTL 0 0 0 0 1 0 0 0 CONJ 0 0 0 0 2 0 0 0 CONJ 0 0 0 0 3 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS Pages in use: 1 4 Visible: 16 line 62: 407 Killed lola --conf=$BIN_DIR/configfiles/ltlfireabilityconf --formula=$DIR/LTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ServersAndClients-PT-400080"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is ServersAndClients-PT-400080, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-162132104400197"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ServersAndClients-PT-400080.tgz
mv ServersAndClients-PT-400080 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;