About the Execution of LoLA for MultiCrashLeafsetExtension-PT-S24C04
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16199.527 | 172254.00 | 315300.00 | 274.60 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r289-tall-162124152800646.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is MultiCrashLeafsetExtension-PT-S24C04, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r289-tall-162124152800646
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 21M
-rw-r--r-- 1 mcc users 43K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 151K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 33K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 107K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.5K May 12 07:59 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 12 07:59 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.0K May 12 07:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 12 07:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 6.2K May 11 18:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 11 18:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.9K May 11 15:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 11 15:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K May 12 04:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 12 04:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 7 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 20M May 12 08:13 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME gen-ReachabilityCardinality-00
FORMULA_NAME gen-ReachabilityCardinality-01
FORMULA_NAME gen-ReachabilityCardinality-02
FORMULA_NAME gen-ReachabilityCardinality-03
FORMULA_NAME gen-ReachabilityCardinality-04
FORMULA_NAME gen-ReachabilityCardinality-05
FORMULA_NAME gen-ReachabilityCardinality-06
FORMULA_NAME gen-ReachabilityCardinality-07
FORMULA_NAME gen-ReachabilityCardinality-08
FORMULA_NAME gen-ReachabilityCardinality-09
FORMULA_NAME gen-ReachabilityCardinality-10
FORMULA_NAME gen-ReachabilityCardinality-11
FORMULA_NAME gen-ReachabilityCardinality-12
FORMULA_NAME gen-ReachabilityCardinality-13
FORMULA_NAME gen-ReachabilityCardinality-14
FORMULA_NAME gen-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1621307173160
starting LoLA
BK_INPUT MultiCrashLeafsetExtension-PT-S24C04
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
BK_STOP 1621307345414
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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lola: Rule S: 0 transitions removed,0 places removed
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 6 gen-ReachabilityCardinality-02
lola: time limit : 214 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 6 gen-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 6 gen-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 6 gen-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 49 (type EQUN) for gen-ReachabilityCardinality-02
lola: result : unknown
lola: LAUNCH task # 53 (type SRCH) for 6 gen-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 390 Killed lola --conf=$BIN_DIR/configfiles/reachabilitycardinalityconf --formula=$DIR/ReachabilityCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MultiCrashLeafsetExtension-PT-S24C04"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is MultiCrashLeafsetExtension-PT-S24C04, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r289-tall-162124152800646"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MultiCrashLeafsetExtension-PT-S24C04.tgz
mv MultiCrashLeafsetExtension-PT-S24C04 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;