About the Execution of LoLA for MultiCrashLeafsetExtension-PT-S24C02
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16233.084 | 142220.00 | 295636.00 | 1186.00 | ?TFT????F??????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r289-tall-162124152800630.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is MultiCrashLeafsetExtension-PT-S24C02, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r289-tall-162124152800630
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 16M
-rw-r--r-- 1 mcc users 41K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 146K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 25K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 82K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 6.4K May 12 07:59 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K May 12 07:59 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.9K May 12 07:59 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 12 07:59 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 6.7K May 11 18:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 24K May 11 18:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.6K May 11 15:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 11 15:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K May 12 04:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 12 04:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 7 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 15M May 12 08:13 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME gen-ReachabilityCardinality-00
FORMULA_NAME gen-ReachabilityCardinality-01
FORMULA_NAME gen-ReachabilityCardinality-02
FORMULA_NAME gen-ReachabilityCardinality-03
FORMULA_NAME gen-ReachabilityCardinality-04
FORMULA_NAME gen-ReachabilityCardinality-05
FORMULA_NAME gen-ReachabilityCardinality-06
FORMULA_NAME gen-ReachabilityCardinality-07
FORMULA_NAME gen-ReachabilityCardinality-08
FORMULA_NAME gen-ReachabilityCardinality-09
FORMULA_NAME gen-ReachabilityCardinality-10
FORMULA_NAME gen-ReachabilityCardinality-11
FORMULA_NAME gen-ReachabilityCardinality-12
FORMULA_NAME gen-ReachabilityCardinality-13
FORMULA_NAME gen-ReachabilityCardinality-14
FORMULA_NAME gen-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1621305706992
starting LoLA
BK_INPUT MultiCrashLeafsetExtension-PT-S24C02
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA gen-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621305849212
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 29 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: Created skeleton in 1.000000 secs.
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: Created skeleton in 6.000000 secs.
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
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gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 6 gen-ReachabilityCardinality-02
lola: time limit : 218 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 6 gen-ReachabilityCardinality-02
lola: time limit : 32000000 sec
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lola: LAUNCH task # 49 (type EQUN) for 6 gen-ReachabilityCardinality-02
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lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 6 gen-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 1 4 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 5/1748 0/5 gen-ReachabilityCardinality-02 5519 t fired, 389 attempts, .
49 EF STEQ 5/3496 0/5 gen-ReachabilityCardinality-02 sara is running.
51 EF SRCH 5/3496 1/5 gen-ReachabilityCardinality-02 5734 m, 1146 m/sec, 6534 t fired, .
52 EF EXCL 5/218 2/32 gen-ReachabilityCardinality-02 15010 m, 3002 m/sec, 17771 t fired, .
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gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: EF 0 1 4 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 10/1743 0/5 gen-ReachabilityCardinality-02 27968 t fired, 2188 attempts, .
49 EF STEQ 10/3491 0/5 gen-ReachabilityCardinality-02 sara is running.
51 EF SRCH 10/3491 2/5 gen-ReachabilityCardinality-02 24984 m, 3850 m/sec, 28916 t fired, .
52 EF EXCL 10/218 5/32 gen-ReachabilityCardinality-02 58390 m, 8676 m/sec, 69309 t fired, .
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lola: FINISHED task # 51 (type SRCH) for gen-ReachabilityCardinality-02
lola: result : false
lola: markings : 26752
lola: fired transitions : 30889
lola: time used : 10.000000
lola: memory pages used : 2
lola: CANCELED task # 48 (type FNDP) for gen-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 49 (type EQUN) for gen-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 52 (type EXCL) for gen-ReachabilityCardinality-02 (obsolete)
lola: FINISHED task # 48 (type FNDP) for gen-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 31223
lola: tried executions : 2454
lola: time used : 10.000000
lola: memory pages used : 0
lola: FINISHED task # 49 (type EQUN) for gen-ReachabilityCardinality-02
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 59 (type EXCL) for 3 gen-ReachabilityCardinality-01
lola: time limit : 232 sec
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lola: LAUNCH task # 55 (type FNDP) for 3 gen-ReachabilityCardinality-01
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lola: LAUNCH task # 58 (type SRCH) for 3 gen-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-56.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-02: EF false tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 1 4 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 3/1161 0/5 gen-ReachabilityCardinality-01 7043 t fired, 677 attempts, .
56 EF STEQ 3/1161 0/5 gen-ReachabilityCardinality-01 sara is running.
58 EF SRCH 3/1742 1/5 gen-ReachabilityCardinality-01 --
59 EF EXCL 3/232 2/32 gen-ReachabilityCardinality-01 22485 m, 4497 m/sec, 26633 t fired, .
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gen-ReachabilityCardinality-02: EF false tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: AG 0 1 4 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 8/1158 0/5 gen-ReachabilityCardinality-01 28125 t fired, 2750 attempts, .
56 EF STEQ 8/1158 0/5 gen-ReachabilityCardinality-01 sara is running.
58 EF SRCH 8/1739 1/5 gen-ReachabilityCardinality-01 --
59 EF EXCL 8/232 6/32 gen-ReachabilityCardinality-01 72473 m, 9997 m/sec, 86103 t fired, .
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lola: FINISHED task # 59 (type EXCL) for gen-ReachabilityCardinality-01
lola: result : false
lola: markings : 77506
lola: fired transitions : 92107
lola: time used : 9.000000
lola: memory pages used : 6
lola: CANCELED task # 55 (type FNDP) for gen-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 56 (type EQUN) for gen-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 58 (type SRCH) for gen-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 66 (type EXCL) for 9 gen-ReachabilityCardinality-03
lola: time limit : 248 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 62 (type FNDP) for 9 gen-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type EQUN) for 9 gen-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 65 (type SRCH) for 9 gen-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type FNDP) for gen-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 30960
lola: tried executions : 3031
lola: time used : 9.000000
lola: memory pages used : 0
lola: FINISHED task # 56 (type EQUN) for gen-ReachabilityCardinality-01
lola: result : unknown
lola: FINISHED task # 63 (type EQUN) for gen-ReachabilityCardinality-03
lola: result : unknown
lola: LAUNCH task # 67 (type SRCH) for 9 gen-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 67 (type SRCH) for gen-ReachabilityCardinality-03
lola: result : unknown
lola: markings : 1614
lola: fired transitions : 1900
lola: time used : 3.000000
lola: memory pages used : 1
lola: LAUNCH task # 82 (type FNDP) for 42 gen-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-01: AG true tandem / relaxed
gen-ReachabilityCardinality-02: EF false tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 3 0 3 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 4/312 0/5 gen-ReachabilityCardinality-03 6598 t fired, 582 attempts, .
65 EF SRCH 4/312 1/5 gen-ReachabilityCardinality-03 5022 m, 1004 m/sec, 5891 t fired, .
66 EF EXCL 4/248 2/32 gen-ReachabilityCardinality-03 24824 m, 4964 m/sec, 29416 t fired, .
82 EF FNDP 1/289 0/5 gen-ReachabilityCardinality-14 339 t fired, 32 attempts, .
Time elapsed: 129 secs. Pages in use: 7
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 65 (type SRCH) for gen-ReachabilityCardinality-03
lola: result : false
lola: markings : 13684
lola: fired transitions : 15896
lola: time used : 5.000000
lola: memory pages used : 2
lola: CANCELED task # 62 (type FNDP) for gen-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 66 (type EXCL) for gen-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 94 (type EXCL) for 24 gen-ReachabilityCardinality-08
lola: time limit : 266 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 108 (type FNDP) for 30 gen-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 109 (type EQUN) for 30 gen-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 62 (type FNDP) for gen-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 14036
lola: tried executions : 1311
lola: time used : 5.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 109 (type EQUN) for gen-ReachabilityCardinality-10
lola: result : unknown
lola: LAUNCH task # 75 (type FNDP) for 45 gen-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-01: AG true tandem / relaxed
gen-ReachabilityCardinality-02: EF false tandem / insertion
gen-ReachabilityCardinality-03: AG true tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 3 1 0 2 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: AG 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 EF FNDP 5/231 0/5 gen-ReachabilityCardinality-15 363 t fired, 31 attempts, .
82 EF FNDP 8/245 0/5 gen-ReachabilityCardinality-14 12187 t fired, 1115 attempts, .
94 EF EXCL 6/266 1/32 gen-ReachabilityCardinality-08 6302 m, 1260 m/sec, 7459 t fired, .
108 EF FNDP 6/246 0/5 gen-ReachabilityCardinality-10 1362 t fired, 127 attempts, .
Time elapsed: 136 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 94 (type EXCL) for gen-ReachabilityCardinality-08
lola: result : false
lola: markings : 77494
lola: fired transitions : 92095
lola: time used : 10.000000
lola: memory pages used : 6
lola: Error: Could not create thread
lola: LAUNCH task # 130 (type EXCL) for 39 gen-ReachabilityCardinality-13
lola: time limit : 288 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-01: AG true tandem / relaxed
gen-ReachabilityCardinality-02: EF false tandem / insertion
gen-ReachabilityCardinality-03: AG true tandem / insertion
gen-ReachabilityCardinality-08: EF false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-09: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 3 1 0 2 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: EF 0 4 0 0 1 0 1 0
gen-ReachabilityCardinality-14: AG 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 EF FNDP 10/207 0/5 gen-ReachabilityCardinality-15 25061 t fired, 2057 attempts, .
82 EF FNDP 13/219 0/5 gen-ReachabilityCardinality-14 38952 t fired, 3588 attempts, .
108 EF FNDP 11/206 0/5 gen-ReachabilityCardinality-10 24397 t fired, 2327 attempts, .
Time elapsed: 141 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 118 (type EXCL) for 18 gen-ReachabilityCardinality-06
lola: time limit : 314 sec
lola: memory limit: 32 pages
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 411 Killed lola --conf=$BIN_DIR/configfiles/reachabilitycardinalityconf --formula=$DIR/ReachabilityCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MultiCrashLeafsetExtension-PT-S24C02"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is MultiCrashLeafsetExtension-PT-S24C02, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r289-tall-162124152800630"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MultiCrashLeafsetExtension-PT-S24C02.tgz
mv MultiCrashLeafsetExtension-PT-S24C02 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;