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Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r289-tall-162124152700582
Last Updated
Jun 28, 2021

About the Execution of LoLA for MultiCrashLeafsetExtension-PT-S16C03

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3271.888 48368.00 152473.00 62.10 TFTTTFFTTFTTTTTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r289-tall-162124152700582.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is MultiCrashLeafsetExtension-PT-S16C03, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r289-tall-162124152700582
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 7.4M
-rw-r--r-- 1 mcc users 50K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 176K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 25K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 84K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.6K May 12 07:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 12 07:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.0K May 12 07:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 12 07:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 5.7K May 11 18:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 11 18:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.0K May 11 15:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 11 15:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K May 12 04:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K May 12 04:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 7 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 6.9M May 12 08:13 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME gen-ReachabilityCardinality-00
FORMULA_NAME gen-ReachabilityCardinality-01
FORMULA_NAME gen-ReachabilityCardinality-02
FORMULA_NAME gen-ReachabilityCardinality-03
FORMULA_NAME gen-ReachabilityCardinality-04
FORMULA_NAME gen-ReachabilityCardinality-05
FORMULA_NAME gen-ReachabilityCardinality-06
FORMULA_NAME gen-ReachabilityCardinality-07
FORMULA_NAME gen-ReachabilityCardinality-08
FORMULA_NAME gen-ReachabilityCardinality-09
FORMULA_NAME gen-ReachabilityCardinality-10
FORMULA_NAME gen-ReachabilityCardinality-11
FORMULA_NAME gen-ReachabilityCardinality-12
FORMULA_NAME gen-ReachabilityCardinality-13
FORMULA_NAME gen-ReachabilityCardinality-14
FORMULA_NAME gen-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1621295250064

starting LoLA
BK_INPUT MultiCrashLeafsetExtension-PT-S16C03
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA gen-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621295298432

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 11 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 16 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 15 gen-ReachabilityCardinality-05
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 15 gen-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 15 gen-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type SRCH) for 15 gen-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 1 4 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 5/592 0/5 gen-ReachabilityCardinality-05 34077 t fired, 1587 attempts, .
49 EF STEQ 5/711 0/5 gen-ReachabilityCardinality-05 sara is running.
51 EF SRCH 5/711 1/5 gen-ReachabilityCardinality-05 27803 m, 5560 m/sec, 32410 t fired, .
52 EF EXCL 5/224 4/32 gen-ReachabilityCardinality-05 110618 m, 22123 m/sec, 130635 t fired, .

Time elapsed: 21 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 52 (type EXCL) for gen-ReachabilityCardinality-05
lola: result : false
lola: markings : 194067
lola: fired transitions : 229606
lola: time used : 8.000000
lola: memory pages used : 7
lola: CANCELED task # 48 (type FNDP) for gen-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 49 (type EQUN) for gen-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 51 (type SRCH) for gen-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 150 (type EXCL) for 27 gen-ReachabilityCardinality-09
lola: time limit : 238 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 134 (type FNDP) for 21 gen-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 135 (type EQUN) for 21 gen-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 137 (type SRCH) for 21 gen-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 48 (type FNDP) for gen-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 89431
lola: tried executions : 4136
lola: time used : 8.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 49 (type EQUN) for gen-ReachabilityCardinality-05
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-135.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-05: EF false tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 2 3 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF FNDP 2/178 0/5 gen-ReachabilityCardinality-07 29884 t fired, 1344 attempts, .
135 EF STEQ 2/178 0/5 gen-ReachabilityCardinality-07 sara is running.
137 EF SRCH 2/178 2/5 gen-ReachabilityCardinality-07 34090 m, 6818 m/sec, 38090 t fired, .
150 EF EXCL 2/238 3/32 gen-ReachabilityCardinality-09 79799 m, 15959 m/sec, 94289 t fired, .

Time elapsed: 26 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 137 (type SRCH) for gen-ReachabilityCardinality-07
lola: result : false
lola: markings : 72114
lola: fired transitions : 80568
lola: time used : 4.000000
lola: memory pages used : 3
lola: CANCELED task # 134 (type FNDP) for gen-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 135 (type EQUN) for gen-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 100 (type FNDP) for 39 gen-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 101 (type EQUN) for 39 gen-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SRCH) for 39 gen-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 134 (type FNDP) for gen-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 68196
lola: tried executions : 2989
lola: time used : 4.000000
lola: memory pages used : 0
lola: FINISHED task # 135 (type EQUN) for gen-ReachabilityCardinality-07
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-101.sara.
lola: FINISHED task # 150 (type EXCL) for gen-ReachabilityCardinality-09
lola: result : false
lola: markings : 192667
lola: fired transitions : 228206
lola: time used : 4.000000
lola: memory pages used : 7
lola: LAUNCH task # 144 (type EXCL) for 0 gen-ReachabilityCardinality-00
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 144 (type EXCL) for gen-ReachabilityCardinality-00
lola: result : true
lola: markings : 90710
lola: fired transitions : 107228
lola: time used : 2.000000
lola: memory pages used : 3
lola: LAUNCH task # 97 (type EXCL) for 45 gen-ReachabilityCardinality-15
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 103 (type SRCH) for gen-ReachabilityCardinality-13
lola: result : false
lola: markings : 39795
lola: fired transitions : 45713
lola: time used : 2.000000
lola: memory pages used : 2
lola: CANCELED task # 100 (type FNDP) for gen-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 101 (type EQUN) for gen-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 121 (type FNDP) for 30 gen-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 122 (type EQUN) for 30 gen-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 124 (type SRCH) for 30 gen-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 100 (type FNDP) for gen-ReachabilityCardinality-13
lola: result : unknown
lola: fired transitions : 38969
lola: tried executions : 2066
lola: time used : 2.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 101 (type EQUN) for gen-ReachabilityCardinality-13
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-122.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-05: EF false tandem / relaxed
gen-ReachabilityCardinality-07: AG true tandem / insertion
gen-ReachabilityCardinality-09: EF false tandem / relaxed
gen-ReachabilityCardinality-13: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: AG 0 2 3 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
97 EF EXCL 1/324 2/32 gen-ReachabilityCardinality-15 30488 m, 6097 m/sec, 35985 t fired, .
121 EF FNDP 1/238 0/5 gen-ReachabilityCardinality-10 9037 t fired, 438 attempts, .
122 EF STEQ 1/238 0/5 gen-ReachabilityCardinality-10 sara is running.
124 EF SRCH 1/255 1/5 gen-ReachabilityCardinality-10 10164 m, 2032 m/sec, 11920 t fired, .

Time elapsed: 31 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 97 (type EXCL) for gen-ReachabilityCardinality-15
lola: result : false
lola: markings : 192630
lola: fired transitions : 228169
lola: time used : 4.000000
lola: memory pages used : 7
lola: LAUNCH task # 131 (type EXCL) for 36 gen-ReachabilityCardinality-12
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: FINISHED task # 131 (type EXCL) for gen-ReachabilityCardinality-12
lola: result : true
lola: markings : 22105
lola: fired transitions : 26097
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 91 (type EXCL) for 9 gen-ReachabilityCardinality-03
lola: time limit : 396 sec
lola: memory limit: 32 pages
lola: FINISHED task # 124 (type SRCH) for gen-ReachabilityCardinality-10
lola: result : false
lola: markings : 93665
lola: fired transitions : 110108
lola: time used : 5.000000
lola: memory pages used : 3
lola: CANCELED task # 121 (type FNDP) for gen-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 122 (type EQUN) for gen-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 74 (type FNDP) for 24 gen-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 24 gen-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SRCH) for 24 gen-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 121 (type FNDP) for gen-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 90075
lola: tried executions : 4410
lola: time used : 5.000000
lola: memory pages used : 0
lola: FINISHED task # 122 (type EQUN) for gen-ReachabilityCardinality-10
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-75.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-05: EF false tandem / relaxed
gen-ReachabilityCardinality-07: AG true tandem / insertion
gen-ReachabilityCardinality-09: EF false tandem / relaxed
gen-ReachabilityCardinality-10: AG true tandem / insertion
gen-ReachabilityCardinality-12: EF true tandem / relaxed
gen-ReachabilityCardinality-13: AG true tandem / insertion
gen-ReachabilityCardinality-15: EF false tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: AG 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-08: AG 0 2 3 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
74 EF FNDP 1/324 0/5 gen-ReachabilityCardinality-08 8622 t fired, 457 attempts, .
75 EF STEQ 1/324 0/5 gen-ReachabilityCardinality-08 sara is running.
77 EF SRCH 1/356 1/5 gen-ReachabilityCardinality-08 10270 m, 2054 m/sec, 11855 t fired, .
91 EF EXCL 2/445 2/32 gen-ReachabilityCardinality-03 51880 m, 10376 m/sec, 61231 t fired, .

Time elapsed: 36 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 91 (type EXCL) for gen-ReachabilityCardinality-03
lola: result : false
lola: markings : 193198
lola: fired transitions : 228737
lola: time used : 5.000000
lola: memory pages used : 7
lola: LAUNCH task # 118 (type EXCL) for 6 gen-ReachabilityCardinality-02
lola: time limit : 508 sec
lola: memory limit: 32 pages
lola: FINISHED task # 75 (type EQUN) for gen-ReachabilityCardinality-08
lola: result : false
lola: CANCELED task # 74 (type FNDP) for gen-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 77 (type SRCH) for gen-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 107 (type FNDP) for 33 gen-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type EQUN) for 33 gen-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 110 (type SRCH) for 33 gen-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 74 (type FNDP) for gen-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 71652
lola: tried executions : 3855
lola: time used : 4.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-108.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-03: AG true tandem / relaxed
gen-ReachabilityCardinality-05: EF false tandem / relaxed
gen-ReachabilityCardinality-07: AG true tandem / insertion
gen-ReachabilityCardinality-08: AG true state equation
gen-ReachabilityCardinality-09: EF false tandem / relaxed
gen-ReachabilityCardinality-10: AG true tandem / insertion
gen-ReachabilityCardinality-12: EF true tandem / relaxed
gen-ReachabilityCardinality-13: AG true tandem / insertion
gen-ReachabilityCardinality-15: EF false tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 2 3 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
107 EF FNDP 2/445 0/5 gen-ReachabilityCardinality-11 24366 t fired, 1153 attempts, .
108 EF STEQ 2/445 0/5 gen-ReachabilityCardinality-11 sara is running.
110 EF SRCH 2/445 1/5 gen-ReachabilityCardinality-11 25351 m, 5070 m/sec, 29466 t fired, .
118 EF EXCL 2/593 3/32 gen-ReachabilityCardinality-02 88572 m, 17714 m/sec, 104683 t fired, .

Time elapsed: 41 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 118 (type EXCL) for gen-ReachabilityCardinality-02
lola: result : false
lola: markings : 192679
lola: fired transitions : 228218
lola: time used : 4.000000
lola: memory pages used : 7
lola: LAUNCH task # 65 (type EXCL) for 42 gen-ReachabilityCardinality-14
lola: time limit : 711 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EXCL) for gen-ReachabilityCardinality-14
lola: result : true
lola: markings : 20520
lola: fired transitions : 24225
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 84 (type EXCL) for 3 gen-ReachabilityCardinality-01
lola: time limit : 889 sec
lola: memory limit: 32 pages
lola: FINISHED task # 110 (type SRCH) for gen-ReachabilityCardinality-11
lola: result : false
lola: markings : 97831
lola: fired transitions : 114274
lola: time used : 6.000000
lola: memory pages used : 4
lola: CANCELED task # 107 (type FNDP) for gen-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 108 (type EQUN) for gen-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 67 (type FNDP) for 18 gen-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type EQUN) for 18 gen-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 70 (type SRCH) for 18 gen-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 107 (type FNDP) for gen-ReachabilityCardinality-11
lola: result : unknown
lola: fired transitions : 98035
lola: tried executions : 4711
lola: time used : 6.000000
lola: memory pages used : 0
lola: FINISHED task # 108 (type EQUN) for gen-ReachabilityCardinality-11
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-68.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-02: AG true tandem / relaxed
gen-ReachabilityCardinality-03: AG true tandem / relaxed
gen-ReachabilityCardinality-05: EF false tandem / relaxed
gen-ReachabilityCardinality-07: AG true tandem / insertion
gen-ReachabilityCardinality-08: AG true state equation
gen-ReachabilityCardinality-09: EF false tandem / relaxed
gen-ReachabilityCardinality-10: AG true tandem / insertion
gen-ReachabilityCardinality-11: AG true tandem / insertion
gen-ReachabilityCardinality-12: EF true tandem / relaxed
gen-ReachabilityCardinality-13: AG true tandem / insertion
gen-ReachabilityCardinality-14: EF true tandem / relaxed
gen-ReachabilityCardinality-15: EF false tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-01: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: EF 0 2 3 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF FNDP 1/888 0/5 gen-ReachabilityCardinality-06 15775 t fired, 811 attempts, .
68 EF STEQ 1/888 0/5 gen-ReachabilityCardinality-06 sara is running.
70 EF SRCH 1/888 1/5 gen-ReachabilityCardinality-06 15540 m, 3108 m/sec, 17341 t fired, .
84 EF EXCL 3/1185 4/32 gen-ReachabilityCardinality-01 103191 m, 20638 m/sec, 122000 t fired, .

Time elapsed: 46 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 70 (type SRCH) for gen-ReachabilityCardinality-06
lola: result : false
lola: markings : 32073
lola: fired transitions : 36448
lola: time used : 2.000000
lola: memory pages used : 2
lola: CANCELED task # 67 (type FNDP) for gen-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 68 (type EQUN) for gen-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 55 (type FNDP) for 12 gen-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 12 gen-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SRCH) for 12 gen-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 68 (type EQUN) for gen-ReachabilityCardinality-06
lola: result : unknown
lola: FINISHED task # 67 (type FNDP) for gen-ReachabilityCardinality-06
lola: result : unknown
lola: fired transitions : 35345
lola: tried executions : 1831
lola: time used : 2.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-56.sara.
lola: FINISHED task # 84 (type EXCL) for gen-ReachabilityCardinality-01
lola: result : false
lola: markings : 192658
lola: fired transitions : 228197
lola: time used : 5.000000
lola: memory pages used : 7
lola: LAUNCH task # 59 (type EXCL) for 12 gen-ReachabilityCardinality-04
lola: time limit : 3552 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type SRCH) for gen-ReachabilityCardinality-04
lola: result : false
lola: markings : 13828
lola: fired transitions : 16111
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 55 (type FNDP) for gen-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 56 (type EQUN) for gen-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 59 (type EXCL) for gen-ReachabilityCardinality-04 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF false tandem / relaxed
gen-ReachabilityCardinality-02: AG true tandem / relaxed
gen-ReachabilityCardinality-03: AG true tandem / relaxed
gen-ReachabilityCardinality-04: AG true tandem / insertion
gen-ReachabilityCardinality-05: EF false tandem / relaxed
gen-ReachabilityCardinality-06: EF false tandem / insertion
gen-ReachabilityCardinality-07: AG true tandem / insertion
gen-ReachabilityCardinality-08: AG true state equation
gen-ReachabilityCardinality-09: EF false tandem / relaxed
gen-ReachabilityCardinality-10: AG true tandem / insertion
gen-ReachabilityCardinality-11: AG true tandem / insertion
gen-ReachabilityCardinality-12: EF true tandem / relaxed
gen-ReachabilityCardinality-13: AG true tandem / insertion
gen-ReachabilityCardinality-14: EF true tandem / relaxed
gen-ReachabilityCardinality-15: EF false tandem / relaxed


Time elapsed: 48 secs. Pages in use: 10

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MultiCrashLeafsetExtension-PT-S16C03"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is MultiCrashLeafsetExtension-PT-S16C03, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r289-tall-162124152700582"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/MultiCrashLeafsetExtension-PT-S16C03.tgz
mv MultiCrashLeafsetExtension-PT-S16C03 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;