About the Execution of LoLA for SmallOperatingSystem-PT-MT4096DC1024
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
9605.403 | 220469.00 | 190673.00 | 514.70 | ?FTF???????T???T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r251-tall-162106741600122.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is SmallOperatingSystem-PT-MT4096DC1024, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r251-tall-162106741600122
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 392K
-rw-r--r-- 1 mcc users 14K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K May 10 09:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 100K May 10 09:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Mar 28 16:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Mar 28 16:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Mar 28 16:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 16:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.2K Mar 27 13:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 27 13:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Mar 25 19:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 25 19:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Mar 22 08:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Mar 22 08:16 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:52 equiv_col
-rw-r--r-- 1 mcc users 13 May 5 16:52 instance
-rw-r--r-- 1 mcc users 6 May 5 16:52 iscolored
-rw-r--r-- 1 mcc users 8.1K May 5 16:52 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1621119405102
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT4096DC1024
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621119625571
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 65 (type FNDP) for 25 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type EQUN) for 25 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SRCH) for 25 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 68 (type SRCH) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/CTLFireability-66.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 66 (type EQUN) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
lola: result : false
lola: CANCELED task # 65 (type FNDP) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07 (obsolete)
lola: FINISHED task # 65 (type FNDP) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
lola: result : unknown
lola: fired transitions : 13248245
lola: tried executions : 15
lola: time used : 3.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/189 15/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 3408058 m, 681611 m/sec, 10209917 t fired, .
Time elapsed: 5 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/189 28/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 6475815 m, 613551 m/sec, 19407016 t fired, .
Time elapsed: 10 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 62 (type EXCL) for 61 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15
lola: result : true
lola: markings : 3152893
lola: fired transitions : 6323196
lola: time used : 3.000000
lola: memory pages used : 14
lola: LAUNCH task # 59 (type EXCL) for 58 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14
lola: time limit : 210 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 2/210 6/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14 1278166 m, 255633 m/sec, 2548553 t fired, .
Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 7/210 21/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14 4848893 m, 714145 m/sec, 9684000 t fired, .
Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 59 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 56 (type EXCL) for 55 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13
lola: time limit : 223 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 5/223 13/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13 3094682 m, 618936 m/sec, 9276861 t fired, .
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 10/223 24/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13 5639810 m, 509025 m/sec, 16905902 t fired, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 56 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 53 (type EXCL) for 52 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12
lola: time limit : 237 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 5/237 8/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12 1880297 m, 376059 m/sec, 5616389 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 10/237 16/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12 3607703 m, 345481 m/sec, 10800589 t fired, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 15/237 23/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12 5330145 m, 344488 m/sec, 15969871 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 20/237 30/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12 7095009 m, 352972 m/sec, 20986287 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 53 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 50 (type EXCL) for 41 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11
lola: time limit : 252 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 2 1 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 5/252 14/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 3317361 m, 663472 m/sec, 9937795 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 2 1 0 3 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 10/252 26/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 6109056 m, 558339 m/sec, 18313791 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 50 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 2 0 0 3 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 48 (type EXCL) for 41 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11
lola: time limit : 270 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 1 1 0 3 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 5/270 16/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 3609239 m, 721847 m/sec, 10813524 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 1 1 0 3 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 10/270 28/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 6663177 m, 610787 m/sec, 19969163 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 48 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ 0 1 0 0 3 0 2 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 44 (type EXCL) for 41 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11
lola: time limit : 291 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11
lola: result : true
lola: markings : 8193
lola: fired transitions : 16385
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10
lola: time limit : 318 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/318 14/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10 3229772 m, 645954 m/sec, 9674999 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/318 25/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10 5926439 m, 539333 m/sec, 17765881 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 39 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 36 (type EXCL) for 35 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09
lola: time limit : 348 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 5/348 17/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09 3930052 m, 786010 m/sec, 7846016 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 10/348 32/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09 7408091 m, 695607 m/sec, 14796053 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 36 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 33 (type EXCL) for 32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08
lola: time limit : 385 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 5/385 7/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 1573046 m, 314609 m/sec, 6277810 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 10/385 14/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 3106464 m, 306683 m/sec, 12416481 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 15/385 14/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 3164158 m, 11538 m/sec, 21542253 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 20/385 19/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 4512038 m, 269576 m/sec, 27476421 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 25/385 25/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 5920545 m, 281701 m/sec, 33115035 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 30/385 32/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 7435785 m, 303048 m/sec, 39170442 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 33 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 25 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
lola: time limit : 429 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 1 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/429 17/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07 3865095 m, 773019 m/sec, 7716081 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 1 0 5 0 0 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/429 31/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07 7270921 m, 681165 m/sec, 14521672 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 23 (type EXCL) for 22 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06
lola: time limit : 488 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/488 20/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06 4560093 m, 912018 m/sec, 9106304 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05
lola: time limit : 568 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/568 12/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05 2721357 m, 544271 m/sec, 8157786 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/568 21/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05 4868448 m, 429418 m/sec, 14592591 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/568 30/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05 7065041 m, 439318 m/sec, 21175918 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 20 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 17 (type EXCL) for 16 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04
lola: time limit : 678 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/678 20/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 4535559 m, 907111 m/sec, 9057227 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 17 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ 0 0 0 0 5 0 1 1
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 14 (type EXCL) for 13 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03
lola: time limit : 845 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03
lola: result : false
lola: markings : 2047
lola: fired transitions : 2048
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 8 (type EXCL) for 3 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01
lola: time limit : 1126 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01
lola: result : false
lola: markings : 2048
lola: fired transitions : 2047
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02
lola: time limit : 3380 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02
lola: result : true
lola: markings : 13310
lola: fired transitions : 22529
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CONJ false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CONJ unknown CONJ
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: DISJ true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CTL true CTL model checker
Time elapsed: 220 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT4096DC1024"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT4096DC1024, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r251-tall-162106741600122"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT4096DC1024.tgz
mv SmallOperatingSystem-PT-MT4096DC1024 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;