About the Execution of LoLA for ResAllocation-PT-R100C002
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
2951.371 | 232511.00 | 214900.00 | 52.60 | ????T?FTF??FT?T? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2021-input.r175-tajo-162089412100818.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is ResAllocation-PT-R100C002, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r175-tajo-162089412100818
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 844K
-rw-r--r-- 1 mcc users 21K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 177K May 10 09:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 79K May 10 09:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 16:33 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 16:33 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 16:33 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Mar 28 16:33 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Mar 27 10:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 16K Mar 27 10:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Mar 25 14:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K Mar 25 14:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Mar 22 08:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 08:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 9 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 422K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R100C002-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1621097380900
starting LoLA
BK_INPUT ResAllocation-PT-R100C002
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA ResAllocation-PT-R100C002-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R100C002-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R100C002-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R100C002-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R100C002-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R100C002-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ResAllocation-PT-R100C002-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621097613411
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R100C002-CTLFireability-00
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 64 (type FNDP) for 54 ResAllocation-PT-R100C002-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 54 ResAllocation-PT-R100C002-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SRCH) for 54 ResAllocation-PT-R100C002-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 67 (type SRCH) for ResAllocation-PT-R100C002-CTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-65.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 64 (type FNDP) for ResAllocation-PT-R100C002-CTLFireability-14
lola: result : true
lola: fired transitions : 73
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 65 (type EQUN) for ResAllocation-PT-R100C002-CTLFireability-14 (obsolete)
lola: FINISHED task # 65 (type EQUN) for ResAllocation-PT-R100C002-CTLFireability-14
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/199 8/32 ResAllocation-PT-R100C002-CTLFireability-00 1810398 m, 362079 m/sec, 4226945 t fired, .
Time elapsed: 8 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/199 16/32 ResAllocation-PT-R100C002-CTLFireability-00 3513906 m, 340701 m/sec, 8289003 t fired, .
Time elapsed: 13 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/199 21/32 ResAllocation-PT-R100C002-CTLFireability-00 4754446 m, 248108 m/sec, 11288531 t fired, .
Time elapsed: 18 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/199 25/32 ResAllocation-PT-R100C002-CTLFireability-00 5766037 m, 202318 m/sec, 14184942 t fired, .
Time elapsed: 23 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 28 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 62 (type EXCL) for 61 ResAllocation-PT-R100C002-CTLFireability-15
lola: time limit : 210 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 CTL EXCL 5/210 9/32 ResAllocation-PT-R100C002-CTLFireability-15 1975482 m, 395096 m/sec, 5738996 t fired, .
Time elapsed: 33 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 CTL EXCL 10/210 16/32 ResAllocation-PT-R100C002-CTLFireability-15 3572990 m, 319501 m/sec, 10732175 t fired, .
Time elapsed: 38 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 CTL EXCL 15/210 24/32 ResAllocation-PT-R100C002-CTLFireability-15 5207024 m, 326806 m/sec, 15688559 t fired, .
Time elapsed: 43 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 CTL EXCL 20/210 30/32 ResAllocation-PT-R100C002-CTLFireability-15 6623168 m, 283228 m/sec, 20054632 t fired, .
Time elapsed: 48 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 62 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 4 0 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 53 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 49 (type EXCL) for 48 ResAllocation-PT-R100C002-CTLFireability-12
lola: time limit : 221 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-12
lola: result : true
lola: markings : 648968
lola: fired transitions : 1261878
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 43 (type EXCL) for 30 ResAllocation-PT-R100C002-CTLFireability-10
lola: time limit : 236 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 3 1 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 4/236 5/32 ResAllocation-PT-R100C002-CTLFireability-10 1014092 m, 202818 m/sec, 3029454 t fired, .
Time elapsed: 58 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 3 1 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 9/236 13/32 ResAllocation-PT-R100C002-CTLFireability-10 2816809 m, 360543 m/sec, 7766624 t fired, .
Time elapsed: 63 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 3 1 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 14/236 18/32 ResAllocation-PT-R100C002-CTLFireability-10 3991721 m, 234982 m/sec, 10672803 t fired, .
Time elapsed: 68 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 3 1 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 19/236 22/32 ResAllocation-PT-R100C002-CTLFireability-10 4787198 m, 159095 m/sec, 13960170 t fired, .
Time elapsed: 73 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 3 1 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 24/236 24/32 ResAllocation-PT-R100C002-CTLFireability-10 5287287 m, 100017 m/sec, 16385835 t fired, .
Time elapsed: 78 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 3 1 0 4 0 0 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 29/236 30/32 ResAllocation-PT-R100C002-CTLFireability-10 6585993 m, 259741 m/sec, 19891866 t fired, .
Time elapsed: 83 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 3 0 0 4 0 1 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 88 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 41 (type EXCL) for 30 ResAllocation-PT-R100C002-CTLFireability-10
lola: time limit : 250 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 2 1 0 4 0 1 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/250 6/32 ResAllocation-PT-R100C002-CTLFireability-10 1161913 m, 232382 m/sec, 6314011 t fired, .
Time elapsed: 93 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 2 1 0 4 0 1 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/250 11/32 ResAllocation-PT-R100C002-CTLFireability-10 2204356 m, 208488 m/sec, 12594090 t fired, .
Time elapsed: 98 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 2 1 0 4 0 1 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/250 17/32 ResAllocation-PT-R100C002-CTLFireability-10 3303704 m, 219869 m/sec, 19073026 t fired, .
Time elapsed: 103 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 2 1 0 4 0 1 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/250 21/32 ResAllocation-PT-R100C002-CTLFireability-10 4234329 m, 186125 m/sec, 25184458 t fired, .
Time elapsed: 108 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 2 1 0 4 0 1 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/250 26/32 ResAllocation-PT-R100C002-CTLFireability-10 5142166 m, 181567 m/sec, 30942279 t fired, .
Time elapsed: 113 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 2 1 0 4 0 1 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/250 31/32 ResAllocation-PT-R100C002-CTLFireability-10 6235300 m, 218626 m/sec, 37662936 t fired, .
Time elapsed: 118 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 41 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 2 0 0 4 0 2 0
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 123 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 35 (type EXCL) for 30 ResAllocation-PT-R100C002-CTLFireability-10
lola: time limit : 267 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-10
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 ResAllocation-PT-R100C002-CTLFireability-09
lola: time limit : 316 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/316 12/32 ResAllocation-PT-R100C002-CTLFireability-09 2400479 m, 480095 m/sec, 6490176 t fired, .
Time elapsed: 128 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/316 23/32 ResAllocation-PT-R100C002-CTLFireability-09 4455902 m, 411084 m/sec, 12690173 t fired, .
Time elapsed: 133 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 138 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 ResAllocation-PT-R100C002-CTLFireability-08
lola: time limit : 346 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-08
lola: result : false
lola: markings : 4951
lola: fired transitions : 4950
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 ResAllocation-PT-R100C002-CTLFireability-07
lola: time limit : 384 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-07
lola: result : true
lola: markings : 4952
lola: fired transitions : 4954
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 ResAllocation-PT-R100C002-CTLFireability-06
lola: time limit : 432 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-06
lola: result : false
lola: markings : 4945
lola: fired transitions : 4944
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 ResAllocation-PT-R100C002-CTLFireability-05
lola: time limit : 494 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/494 12/32 ResAllocation-PT-R100C002-CTLFireability-05 2294775 m, 458955 m/sec, 6406063 t fired, .
Time elapsed: 143 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/494 22/32 ResAllocation-PT-R100C002-CTLFireability-05 4476924 m, 436429 m/sec, 13140204 t fired, .
Time elapsed: 148 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/494 32/32 ResAllocation-PT-R100C002-CTLFireability-05 6656128 m, 435840 m/sec, 19669951 t fired, .
Time elapsed: 153 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 158 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 ResAllocation-PT-R100C002-CTLFireability-04
lola: time limit : 573 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-04
lola: result : true
lola: markings : 4952
lola: fired transitions : 4953
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 ResAllocation-PT-R100C002-CTLFireability-03
lola: time limit : 688 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/688 11/32 ResAllocation-PT-R100C002-CTLFireability-03 2226447 m, 445289 m/sec, 6690111 t fired, .
Time elapsed: 163 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/688 20/32 ResAllocation-PT-R100C002-CTLFireability-03 4299250 m, 414560 m/sec, 13712071 t fired, .
Time elapsed: 168 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/688 29/32 ResAllocation-PT-R100C002-CTLFireability-03 6211126 m, 382375 m/sec, 20245227 t fired, .
Time elapsed: 173 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 178 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 ResAllocation-PT-R100C002-CTLFireability-02
lola: time limit : 855 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/855 13/32 ResAllocation-PT-R100C002-CTLFireability-02 2446917 m, 489383 m/sec, 5547842 t fired, .
Time elapsed: 183 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/855 24/32 ResAllocation-PT-R100C002-CTLFireability-02 4703524 m, 451321 m/sec, 11207696 t fired, .
Time elapsed: 188 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 193 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 ResAllocation-PT-R100C002-CTLFireability-01
lola: time limit : 1135 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/1135 15/32 ResAllocation-PT-R100C002-CTLFireability-01 2764736 m, 552947 m/sec, 5362486 t fired, .
Time elapsed: 198 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/1135 22/32 ResAllocation-PT-R100C002-CTLFireability-01 4312912 m, 309635 m/sec, 8902994 t fired, .
Time elapsed: 203 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/1135 31/32 ResAllocation-PT-R100C002-CTLFireability-01 6066824 m, 350782 m/sec, 12888129 t fired, .
Time elapsed: 208 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 213 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 52 (type EXCL) for 51 ResAllocation-PT-R100C002-CTLFireability-13
lola: time limit : 1693 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 5/1693 10/32 ResAllocation-PT-R100C002-CTLFireability-13 1832091 m, 366418 m/sec, 4614333 t fired, .
Time elapsed: 218 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 10/1693 19/32 ResAllocation-PT-R100C002-CTLFireability-13 3647278 m, 363037 m/sec, 9475904 t fired, .
Time elapsed: 223 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 15/1693 26/32 ResAllocation-PT-R100C002-CTLFireability-13 5021245 m, 274793 m/sec, 13620774 t fired, .
Time elapsed: 228 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R100C002-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-10: DISJ 0 0 0 0 5 0 2 1
ResAllocation-PT-R100C002-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R100C002-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R100C002-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 233 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 ResAllocation-PT-R100C002-CTLFireability-11
lola: time limit : 3367 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for ResAllocation-PT-R100C002-CTLFireability-11
lola: result : false
lola: markings : 4952
lola: fired transitions : 9903
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R100C002-CTLFireability-00: CTL unknown AGGR
ResAllocation-PT-R100C002-CTLFireability-01: CTL unknown AGGR
ResAllocation-PT-R100C002-CTLFireability-02: CTL unknown AGGR
ResAllocation-PT-R100C002-CTLFireability-03: CTL unknown AGGR
ResAllocation-PT-R100C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-05: CTL unknown AGGR
ResAllocation-PT-R100C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-09: CTL unknown AGGR
ResAllocation-PT-R100C002-CTLFireability-10: DISJ unknown DISJ
ResAllocation-PT-R100C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R100C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R100C002-CTLFireability-13: CTL unknown AGGR
ResAllocation-PT-R100C002-CTLFireability-14: DISJ true findpath
ResAllocation-PT-R100C002-CTLFireability-15: CTL unknown AGGR
Time elapsed: 233 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R100C002"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R100C002, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r175-tajo-162089412100818"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R100C002.tgz
mv ResAllocation-PT-R100C002 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;