About the Execution of LoLA for RERS17pb113-PT-7
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15509.319 | 3600000.00 | 10832352.00 | 167.30 | ????FTT?TF?T???? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2021-input.r175-tajo-162089411100172.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is RERS17pb113-PT-7, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r175-tajo-162089411100172
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 100K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 20K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 100K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.1K Mar 28 16:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 16:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Mar 28 16:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 28 16:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Mar 27 10:05 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 10:05 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.1K Mar 25 13:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K Mar 25 13:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 08:13 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 08:13 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 2 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 15M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-7-00
FORMULA_NAME RERS17pb113-PT-7-01
FORMULA_NAME RERS17pb113-PT-7-02
FORMULA_NAME RERS17pb113-PT-7-03
FORMULA_NAME RERS17pb113-PT-7-04
FORMULA_NAME RERS17pb113-PT-7-05
FORMULA_NAME RERS17pb113-PT-7-06
FORMULA_NAME RERS17pb113-PT-7-07
FORMULA_NAME RERS17pb113-PT-7-08
FORMULA_NAME RERS17pb113-PT-7-09
FORMULA_NAME RERS17pb113-PT-7-10
FORMULA_NAME RERS17pb113-PT-7-11
FORMULA_NAME RERS17pb113-PT-7-12
FORMULA_NAME RERS17pb113-PT-7-13
FORMULA_NAME RERS17pb113-PT-7-14
FORMULA_NAME RERS17pb113-PT-7-15
=== Now, execution of the tool begins
BK_START 1621069406381
starting LoLA
BK_INPUT RERS17pb113-PT-7
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLCardinality
FORMULA RERS17pb113-PT-7-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-7-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-7-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-7-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-7-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-7-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:184
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:430
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RERS17pb113-PT-7-06: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-07: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-08: LTL/CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-09: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-10: LTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-7-11: LTL/CTL 0 0 0 0 0 0 0 0
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1 LTL EXCL 110/2423 1/5 RERS17pb113-PT-7-00 9424 m, 96 m/sec, 9423 t fired, .
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1 LTL EXCL 185/2423 1/5 RERS17pb113-PT-7-00 15760 m, 78 m/sec, 15759 t fired, .
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1 LTL EXCL 190/2423 1/5 RERS17pb113-PT-7-00 16181 m, 84 m/sec, 16180 t fired, .
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1 LTL EXCL 200/2423 1/5 RERS17pb113-PT-7-00 17068 m, 89 m/sec, 17067 t fired, .
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1 LTL EXCL 330/2423 1/5 RERS17pb113-PT-7-00 27603 m, 87 m/sec, 27602 t fired, .
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1 LTL EXCL 335/2423 1/5 RERS17pb113-PT-7-00 27876 m, 54 m/sec, 27875 t fired, .
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1 LTL EXCL 340/2423 1/5 RERS17pb113-PT-7-00 28280 m, 80 m/sec, 28279 t fired, .
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1 LTL EXCL 345/2423 1/5 RERS17pb113-PT-7-00 28760 m, 96 m/sec, 28759 t fired, .
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1 LTL EXCL 350/2423 1/5 RERS17pb113-PT-7-00 29212 m, 90 m/sec, 29211 t fired, .
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1 LTL EXCL 5/1938 1/5 RERS17pb113-PT-7-00 408 m, -7745 m/sec, 407 t fired, .
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1 LTL EXCL 10/1938 1/5 RERS17pb113-PT-7-00 856 m, 89 m/sec, 855 t fired, .
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1 LTL EXCL 65/1938 1/5 RERS17pb113-PT-7-00 4085 m, 76 m/sec, 4084 t fired, .
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1 LTL EXCL 70/1938 1/5 RERS17pb113-PT-7-00 4517 m, 86 m/sec, 4516 t fired, .
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1 LTL EXCL 75/1938 1/5 RERS17pb113-PT-7-00 4906 m, 77 m/sec, 4905 t fired, .
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1 LTL EXCL 80/1938 1/5 RERS17pb113-PT-7-00 5343 m, 87 m/sec, 5342 t fired, .
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1 LTL EXCL 85/1938 1/5 RERS17pb113-PT-7-00 5717 m, 74 m/sec, 5716 t fired, .
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1 LTL EXCL 90/1938 1/5 RERS17pb113-PT-7-00 6110 m, 78 m/sec, 6109 t fired, .
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1 LTL EXCL 95/1938 1/5 RERS17pb113-PT-7-00 6437 m, 65 m/sec, 6436 t fired, .
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1 LTL EXCL 135/1938 1/5 RERS17pb113-PT-7-00 9025 m, 70 m/sec, 9024 t fired, .
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1 LTL EXCL 140/1938 1/5 RERS17pb113-PT-7-00 9363 m, 67 m/sec, 9362 t fired, .
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1 LTL EXCL 145/1938 1/5 RERS17pb113-PT-7-00 9767 m, 80 m/sec, 9766 t fired, .
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1 LTL EXCL 150/1938 1/5 RERS17pb113-PT-7-00 10110 m, 68 m/sec, 10109 t fired, .
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1 LTL EXCL 155/1938 1/5 RERS17pb113-PT-7-00 10412 m, 60 m/sec, 10411 t fired, .
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1 LTL EXCL 160/1938 1/5 RERS17pb113-PT-7-00 10865 m, 90 m/sec, 10864 t fired, .
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1 LTL EXCL 165/1938 1/5 RERS17pb113-PT-7-00 11315 m, 90 m/sec, 11314 t fired, .
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1 LTL EXCL 170/1938 1/5 RERS17pb113-PT-7-00 11701 m, 77 m/sec, 11700 t fired, .
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1 LTL EXCL 175/1938 1/5 RERS17pb113-PT-7-00 11925 m, 44 m/sec, 11924 t fired, .
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1 LTL EXCL 180/1938 1/5 RERS17pb113-PT-7-00 12342 m, 83 m/sec, 12341 t fired, .
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1 LTL EXCL 210/1938 1/5 RERS17pb113-PT-7-00 14463 m, 68 m/sec, 14462 t fired, .
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1 LTL EXCL 215/1938 1/5 RERS17pb113-PT-7-00 14741 m, 55 m/sec, 14740 t fired, .
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1 LTL EXCL 220/1938 1/5 RERS17pb113-PT-7-00 14896 m, 31 m/sec, 14895 t fired, .
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1 LTL EXCL 225/1938 1/5 RERS17pb113-PT-7-00 15162 m, 53 m/sec, 15161 t fired, .
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1 LTL EXCL 230/1938 1/5 RERS17pb113-PT-7-00 15566 m, 80 m/sec, 15565 t fired, .
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1 LTL EXCL 240/1938 1/5 RERS17pb113-PT-7-00 16293 m, 84 m/sec, 16292 t fired, .
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1 LTL EXCL 355/387 1/5 RERS17pb113-PT-7-00 23333 m, 65 m/sec, 23332 t fired, .
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1 LTL EXCL 165/247 1/5 RERS17pb113-PT-7-00 5072 m, 37 m/sec, 5071 t fired, .
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1 LTL EXCL 60/197 1/5 RERS17pb113-PT-7-00 1619 m, 12 m/sec, 1618 t fired, .
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1 LTL EXCL 65/197 1/5 RERS17pb113-PT-7-00 1676 m, 11 m/sec, 1675 t fired, .
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RERS17pb113-PT-7-06: LTL true LTL model checker
RERS17pb113-PT-7-08: LTL/CTL true LTL model checker
RERS17pb113-PT-7-09: LTL false LTL model checker
RERS17pb113-PT-7-11: LTL/CTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-00: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-7-01: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-02: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-03: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-7-07: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-7-10: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-12: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-13: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-14: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-15: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 LTL EXCL 50/252 1/5 RERS17pb113-PT-7-00 589 m, 12 m/sec, 588 t fired, .
10 LTL EXCL 50/50 1/32 RERS17pb113-PT-7-03 585 m, 9 m/sec, 584 t fired, .
22 LTL EXCL 5/207 1/5 RERS17pb113-PT-7-07 63 m, -85 m/sec, 62 t fired, .
Time elapsed: 3398 secs. Pages in use: 53
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for RERS17pb113-PT-7-03 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-7-04: LTL false LTL model checker
RERS17pb113-PT-7-05: INITIAL true preprocessing
RERS17pb113-PT-7-06: LTL true LTL model checker
RERS17pb113-PT-7-08: LTL/CTL true LTL model checker
RERS17pb113-PT-7-09: LTL false LTL model checker
RERS17pb113-PT-7-11: LTL/CTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-00: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-7-01: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-02: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-03: LTL 0 0 0 0 1 1 0 0
RERS17pb113-PT-7-07: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-7-10: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-12: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-13: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-14: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-15: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 LTL EXCL 55/252 1/5 RERS17pb113-PT-7-00 650 m, 12 m/sec, 649 t fired, .
22 LTL EXCL 10/34 1/5 RERS17pb113-PT-7-07 124 m, 12 m/sec, 123 t fired, .
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lola: LAUNCH task # 10 (type EXCL) for 9 RERS17pb113-PT-7-03
lola: time limit : 197 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-7-04: LTL false LTL model checker
RERS17pb113-PT-7-05: INITIAL true preprocessing
RERS17pb113-PT-7-06: LTL true LTL model checker
RERS17pb113-PT-7-08: LTL/CTL true LTL model checker
RERS17pb113-PT-7-09: LTL false LTL model checker
RERS17pb113-PT-7-11: LTL/CTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-00: LTL 0 0 1 0 1 0 0 0
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RERS17pb113-PT-7-07: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-7-10: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-12: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-13: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-14: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-15: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 LTL EXCL 60/252 1/5 RERS17pb113-PT-7-00 713 m, 12 m/sec, 712 t fired, .
10 LTL EXCL 5/197 1/5 RERS17pb113-PT-7-03 54 m, -106 m/sec, 53 t fired, .
22 LTL EXCL 15/41 1/5 RERS17pb113-PT-7-07 187 m, 12 m/sec, 186 t fired, .
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RERS17pb113-PT-7-05: INITIAL true preprocessing
RERS17pb113-PT-7-06: LTL true LTL model checker
RERS17pb113-PT-7-08: LTL/CTL true LTL model checker
RERS17pb113-PT-7-09: LTL false LTL model checker
RERS17pb113-PT-7-11: LTL/CTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RERS17pb113-PT-7-10: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-12: LTL 0 0 0 0 1 0 1 0
RERS17pb113-PT-7-13: LTL 0 0 0 0 1 0 1 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 LTL EXCL 65/252 1/5 RERS17pb113-PT-7-00 777 m, 12 m/sec, 776 t fired, .
10 LTL EXCL 10/197 1/5 RERS17pb113-PT-7-03 108 m, 10 m/sec, 107 t fired, .
22 LTL EXCL 20/34 1/5 RERS17pb113-PT-7-07 251 m, 12 m/sec, 250 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-7-04: LTL false LTL model checker
RERS17pb113-PT-7-05: INITIAL true preprocessing
RERS17pb113-PT-7-06: LTL true LTL model checker
RERS17pb113-PT-7-08: LTL/CTL true LTL model checker
RERS17pb113-PT-7-09: LTL false LTL model checker
RERS17pb113-PT-7-11: LTL/CTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-7-00: LTL 0 0 1 0 1 0 0 0
RERS17pb113-PT-7-01: LTL 0 1 0 0 1 0 0 0
RERS17pb113-PT-7-02: LTL 0 1 0 0 1 0 0 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-7"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-7, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r175-tajo-162089411100172"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-7.tgz
mv RERS17pb113-PT-7 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;