About the Execution of LoLA for RERS17pb113-PT-5
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16213.151 | 1086858.00 | 1713275.00 | 189.00 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2021-input.r175-tajo-162089411000154.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is RERS17pb113-PT-5, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r175-tajo-162089411000154
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 144K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 21K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 104K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.0K Mar 28 16:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 21K Mar 28 16:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 28 16:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 28 16:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Mar 27 10:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K Mar 27 10:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.9K Mar 25 13:11 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 25 13:11 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 08:13 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 08:13 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 2 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 15M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-00
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-01
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-02
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-03
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-04
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-05
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-06
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-07
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-08
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-09
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-10
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-11
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-12
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-13
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-14
FORMULA_NAME RERS17pb113-PT-5-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1621068717313
starting LoLA
BK_INPUT RERS17pb113-PT-5
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
BK_STOP 1621069804171
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-00: EG 0 0 0 0 1 0 0 0
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RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 4 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 5 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 5 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 5 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 5 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 5 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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RERS17pb113-PT-5-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-03: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-06: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-08: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-5-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-5-CTLFireability-11: CONJ 0 0 0 0 5 0 0 0
RERS17pb113-PT-5-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-5-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
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/home/mcc/BenchKit/BenchKit_head.sh: line 62: 415 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r175-tajo-162089411000154"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-5.tgz
mv RERS17pb113-PT-5 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;