About the Execution of LoLA for Planning-PT-none
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16237.128 | 142906.00 | 143670.00 | 55.10 | ??????????FT???F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fko/mcc2021-input.r156-oct2-162089264900066.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fko/mcc2021-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is Planning-PT-none, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r156-oct2-162089264900066
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 392K
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.6K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 78K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Mar 28 16:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 16:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K Mar 28 16:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 16:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Mar 27 09:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 09:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 25 11:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 25 11:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:16 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 5 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 56K May 5 16:51 model.pnml
-rw-r--r-- 1 mcc users 1 May 5 16:51 unfinite
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Planning-PT-none-CTLFireability-00
FORMULA_NAME Planning-PT-none-CTLFireability-01
FORMULA_NAME Planning-PT-none-CTLFireability-02
FORMULA_NAME Planning-PT-none-CTLFireability-03
FORMULA_NAME Planning-PT-none-CTLFireability-04
FORMULA_NAME Planning-PT-none-CTLFireability-05
FORMULA_NAME Planning-PT-none-CTLFireability-06
FORMULA_NAME Planning-PT-none-CTLFireability-07
FORMULA_NAME Planning-PT-none-CTLFireability-08
FORMULA_NAME Planning-PT-none-CTLFireability-09
FORMULA_NAME Planning-PT-none-CTLFireability-10
FORMULA_NAME Planning-PT-none-CTLFireability-11
FORMULA_NAME Planning-PT-none-CTLFireability-12
FORMULA_NAME Planning-PT-none-CTLFireability-13
FORMULA_NAME Planning-PT-none-CTLFireability-14
FORMULA_NAME Planning-PT-none-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1621020403512
starting LoLA
BK_INPUT Planning-PT-none
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA Planning-PT-none-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Planning-PT-none-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Planning-PT-none-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621020546418
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 7 (type EXCL) for 6 Planning-PT-none-CTLFireability-02
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 57 (type FNDP) for 31 Planning-PT-none-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type EQUN) for 31 Planning-PT-none-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SRCH) for 31 Planning-PT-none-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 57 (type FNDP) for Planning-PT-none-CTLFireability-09
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 58 (type EQUN) for Planning-PT-none-CTLFireability-09 (obsolete)
lola: CANCELED task # 60 (type SRCH) for Planning-PT-none-CTLFireability-09 (obsolete)
lola: FINISHED task # 60 (type SRCH) for Planning-PT-none-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/CTLFireability-58.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 58 (type EQUN) for Planning-PT-none-CTLFireability-09
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/211 11/32 Planning-PT-none-CTLFireability-02 2199363 m, 439872 m/sec, 6598088 t fired, .
Time elapsed: 5 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/211 20/32 Planning-PT-none-CTLFireability-02 4367536 m, 433634 m/sec, 13102608 t fired, .
Time elapsed: 10 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/211 30/32 Planning-PT-none-CTLFireability-02 6496878 m, 425868 m/sec, 19490635 t fired, .
Time elapsed: 15 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for Planning-PT-none-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 53 Planning-PT-none-CTLFireability-15
lola: time limit : 223 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for Planning-PT-none-CTLFireability-15
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 Planning-PT-none-CTLFireability-13
lola: time limit : 238 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 5/238 18/32 Planning-PT-none-CTLFireability-13 3738941 m, 747788 m/sec, 5608409 t fired, .
Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 48 (type EXCL) for Planning-PT-none-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
Planning-PT-none-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 42 (type EXCL) for 41 Planning-PT-none-CTLFireability-11
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for Planning-PT-none-CTLFireability-11
lola: result : true
lola: markings : 68
lola: fired transitions : 73
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 Planning-PT-none-CTLFireability-10
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for Planning-PT-none-CTLFireability-10
lola: result : false
lola: markings : 45
lola: fired transitions : 46
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 31 Planning-PT-none-CTLFireability-09
lola: time limit : 297 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 1 0 5 0 0 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/297 20/32 Planning-PT-none-CTLFireability-09 4192078 m, 838415 m/sec, 4192078 t fired, .
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for Planning-PT-none-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 29 (type EXCL) for 28 Planning-PT-none-CTLFireability-08
lola: time limit : 323 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/323 1/32 Planning-PT-none-CTLFireability-08 148089 m, 29617 m/sec, 296177 t fired, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/323 2/32 Planning-PT-none-CTLFireability-08 288460 m, 28074 m/sec, 576919 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/323 2/32 Planning-PT-none-CTLFireability-08 428584 m, 28024 m/sec, 857167 t fired, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 20/323 3/32 Planning-PT-none-CTLFireability-08 569178 m, 28118 m/sec, 1138355 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 25/323 4/32 Planning-PT-none-CTLFireability-08 709402 m, 28044 m/sec, 1418803 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 30/323 4/32 Planning-PT-none-CTLFireability-08 849250 m, 27969 m/sec, 1698499 t fired, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 35/323 5/32 Planning-PT-none-CTLFireability-08 989474 m, 28044 m/sec, 1978947 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 40/323 6/32 Planning-PT-none-CTLFireability-08 1129420 m, 27989 m/sec, 2258839 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 45/323 6/32 Planning-PT-none-CTLFireability-08 1269258 m, 27967 m/sec, 2538515 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 50/323 7/32 Planning-PT-none-CTLFireability-08 1408956 m, 27939 m/sec, 2817911 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 55/323 8/32 Planning-PT-none-CTLFireability-08 1548295 m, 27867 m/sec, 3096589 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 60/323 8/32 Planning-PT-none-CTLFireability-08 1685198 m, 27380 m/sec, 3370395 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 65/323 9/32 Planning-PT-none-CTLFireability-08 1824844 m, 27929 m/sec, 3649687 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 70/323 10/32 Planning-PT-none-CTLFireability-08 1964636 m, 27958 m/sec, 3929271 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 75/323 10/32 Planning-PT-none-CTLFireability-08 2104865 m, 28045 m/sec, 4209729 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 80/323 11/32 Planning-PT-none-CTLFireability-08 2244871 m, 28001 m/sec, 4489741 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 85/323 11/32 Planning-PT-none-CTLFireability-08 2384529 m, 27931 m/sec, 4769057 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 90/323 12/32 Planning-PT-none-CTLFireability-08 2524214 m, 27937 m/sec, 5048427 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 95/323 13/32 Planning-PT-none-CTLFireability-08 2664041 m, 27965 m/sec, 5328081 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Planning-PT-none-CTLFireability-10: CTL false CTL model checker
Planning-PT-none-CTLFireability-11: CTL true CTL model checker
Planning-PT-none-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Planning-PT-none-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
Planning-PT-none-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Planning-PT-none-CTLFireability-09: DISJ 0 0 0 0 5 0 1 1
Planning-PT-none-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Planning-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Planning-PT-none-CTLFireability-14: EU 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 100/323 13/32 Planning-PT-none-CTLFireability-08 2803873 m, 27966 m/sec, 5607745 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 427 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Planning-PT-none"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is Planning-PT-none, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r156-oct2-162089264900066"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Planning-PT-none.tgz
mv Planning-PT-none execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;