About the Execution of LoLA for PermAdmissibility-PT-50
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
10947.796 | 1175574.00 | 1150438.00 | 2499.70 | ????????TF???F?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r137-tall-162089122300546.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is PermAdmissibility-PT-50, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-162089122300546
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.5M
-rw-r--r-- 1 mcc users 22K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 153K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 426K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 2.1M May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.3K Mar 28 16:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 32K Mar 28 16:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 18K Mar 28 16:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 70K Mar 28 16:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.5K Mar 27 06:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K Mar 27 06:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 26K Mar 25 08:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Mar 25 08:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.2K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 484K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-00
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-01
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-02
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-03
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-04
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-05
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-06
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-07
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-08
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-09
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-10
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-11
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-12
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-13
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-14
FORMULA_NAME PermAdmissibility-PT-50-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620954755622
starting LoLA
BK_INPUT PermAdmissibility-PT-50
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA PermAdmissibility-PT-50-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-50-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-50-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620955931196
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 4 (type EXCL) for 3 PermAdmissibility-PT-50-CTLFireability-01
lola: time limit : 146 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/195 3/32 PermAdmissibility-PT-50-CTLFireability-01 473873 m, 94774 m/sec, 3147501 t fired, .
Time elapsed: 95 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/195 4/32 PermAdmissibility-PT-50-CTLFireability-01 928157 m, 90856 m/sec, 6522382 t fired, .
Time elapsed: 100 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/195 6/32 PermAdmissibility-PT-50-CTLFireability-01 1309557 m, 76280 m/sec, 9957320 t fired, .
Time elapsed: 105 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/195 8/32 PermAdmissibility-PT-50-CTLFireability-01 1675277 m, 73144 m/sec, 13501786 t fired, .
Time elapsed: 110 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/195 9/32 PermAdmissibility-PT-50-CTLFireability-01 2049053 m, 74755 m/sec, 16930820 t fired, .
Time elapsed: 115 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/195 11/32 PermAdmissibility-PT-50-CTLFireability-01 2453838 m, 80957 m/sec, 20236571 t fired, .
Time elapsed: 120 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/195 13/32 PermAdmissibility-PT-50-CTLFireability-01 2848027 m, 78837 m/sec, 23499516 t fired, .
Time elapsed: 125 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/195 14/32 PermAdmissibility-PT-50-CTLFireability-01 3197721 m, 69938 m/sec, 26819031 t fired, .
Time elapsed: 130 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/195 16/32 PermAdmissibility-PT-50-CTLFireability-01 3543326 m, 69121 m/sec, 30104724 t fired, .
Time elapsed: 135 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/195 17/32 PermAdmissibility-PT-50-CTLFireability-01 3921932 m, 75721 m/sec, 33365715 t fired, .
Time elapsed: 140 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 55/195 19/32 PermAdmissibility-PT-50-CTLFireability-01 4282125 m, 72038 m/sec, 36652708 t fired, .
Time elapsed: 145 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 60/195 20/32 PermAdmissibility-PT-50-CTLFireability-01 4656402 m, 74855 m/sec, 39877853 t fired, .
Time elapsed: 150 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 65/195 22/32 PermAdmissibility-PT-50-CTLFireability-01 5016899 m, 72099 m/sec, 43074375 t fired, .
Time elapsed: 155 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 70/195 23/32 PermAdmissibility-PT-50-CTLFireability-01 5364744 m, 69569 m/sec, 46325603 t fired, .
Time elapsed: 160 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 75/195 25/32 PermAdmissibility-PT-50-CTLFireability-01 5700590 m, 67169 m/sec, 49565850 t fired, .
Time elapsed: 165 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 80/195 26/32 PermAdmissibility-PT-50-CTLFireability-01 6073782 m, 74638 m/sec, 52766535 t fired, .
Time elapsed: 170 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 85/195 28/32 PermAdmissibility-PT-50-CTLFireability-01 6412565 m, 67756 m/sec, 56001166 t fired, .
Time elapsed: 175 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 90/195 29/32 PermAdmissibility-PT-50-CTLFireability-01 6781018 m, 73690 m/sec, 59180622 t fired, .
Time elapsed: 180 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 95/195 31/32 PermAdmissibility-PT-50-CTLFireability-01 7136739 m, 71144 m/sec, 62346144 t fired, .
Time elapsed: 185 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 100/195 32/32 PermAdmissibility-PT-50-CTLFireability-01 7478765 m, 68405 m/sec, 65507779 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 53 PermAdmissibility-PT-50-CTLFireability-15
lola: time limit : 200 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 5/200 4/32 PermAdmissibility-PT-50-CTLFireability-15 772880 m, 154576 m/sec, 3320822 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 10/200 7/32 PermAdmissibility-PT-50-CTLFireability-15 1423211 m, 130066 m/sec, 6663215 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 15/200 9/32 PermAdmissibility-PT-50-CTLFireability-15 2020341 m, 119426 m/sec, 9992301 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 20/200 11/32 PermAdmissibility-PT-50-CTLFireability-15 2573911 m, 110714 m/sec, 13272394 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 25/200 14/32 PermAdmissibility-PT-50-CTLFireability-15 3106606 m, 106539 m/sec, 16714087 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 30/200 16/32 PermAdmissibility-PT-50-CTLFireability-15 3719258 m, 122530 m/sec, 20026388 t fired, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 35/200 19/32 PermAdmissibility-PT-50-CTLFireability-15 4312002 m, 118548 m/sec, 23384088 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 40/200 22/32 PermAdmissibility-PT-50-CTLFireability-15 4939370 m, 125473 m/sec, 26604585 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 45/200 24/32 PermAdmissibility-PT-50-CTLFireability-15 5499229 m, 111971 m/sec, 29885325 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 50/200 26/32 PermAdmissibility-PT-50-CTLFireability-15 6018691 m, 103892 m/sec, 33214283 t fired, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 55/200 28/32 PermAdmissibility-PT-50-CTLFireability-15 6506001 m, 97462 m/sec, 36485862 t fired, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 60/200 30/32 PermAdmissibility-PT-50-CTLFireability-15 7053989 m, 109597 m/sec, 39772947 t fired, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 51 (type EXCL) for 42 PermAdmissibility-PT-50-CTLFireability-14
lola: time limit : 208 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-14
lola: result : true
lola: markings : 950
lola: fired transitions : 1902
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 42 PermAdmissibility-PT-50-CTLFireability-14
lola: time limit : 222 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 1 1 0 4 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 5/222 8/32 PermAdmissibility-PT-50-CTLFireability-14 1554811 m, 310962 m/sec, 2181845 t fired, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 1 1 0 4 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 10/222 15/32 PermAdmissibility-PT-50-CTLFireability-14 3002467 m, 289531 m/sec, 4394724 t fired, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 1 1 0 4 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 15/222 22/32 PermAdmissibility-PT-50-CTLFireability-14 4404103 m, 280327 m/sec, 6570178 t fired, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 1 1 0 4 0 0 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 20/222 29/32 PermAdmissibility-PT-50-CTLFireability-14 5861204 m, 291420 m/sec, 8740970 t fired, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 49 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 1 0 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 45 (type EXCL) for 42 PermAdmissibility-PT-50-CTLFireability-14
lola: time limit : 236 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 5/236 3/32 PermAdmissibility-PT-50-CTLFireability-14 559180 m, 111836 m/sec, 3806361 t fired, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 10/236 5/32 PermAdmissibility-PT-50-CTLFireability-14 1101458 m, 108455 m/sec, 7369989 t fired, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 15/236 7/32 PermAdmissibility-PT-50-CTLFireability-14 1564822 m, 92672 m/sec, 11172754 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 20/236 9/32 PermAdmissibility-PT-50-CTLFireability-14 1964795 m, 79994 m/sec, 15001802 t fired, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 25/236 11/32 PermAdmissibility-PT-50-CTLFireability-14 2354994 m, 78039 m/sec, 18734170 t fired, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 30/236 12/32 PermAdmissibility-PT-50-CTLFireability-14 2783486 m, 85698 m/sec, 22413923 t fired, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 35/236 14/32 PermAdmissibility-PT-50-CTLFireability-14 3186396 m, 80582 m/sec, 26099173 t fired, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 40/236 16/32 PermAdmissibility-PT-50-CTLFireability-14 3574761 m, 77673 m/sec, 29888450 t fired, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 45/236 18/32 PermAdmissibility-PT-50-CTLFireability-14 4002256 m, 85499 m/sec, 33615402 t fired, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 50/236 19/32 PermAdmissibility-PT-50-CTLFireability-14 4394608 m, 78470 m/sec, 37279546 t fired, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 55/236 21/32 PermAdmissibility-PT-50-CTLFireability-14 4800574 m, 81193 m/sec, 40909551 t fired, .
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 60/236 23/32 PermAdmissibility-PT-50-CTLFireability-14 5182073 m, 76299 m/sec, 44642106 t fired, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 65/236 24/32 PermAdmissibility-PT-50-CTLFireability-14 5574230 m, 78431 m/sec, 48286552 t fired, .
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 70/236 26/32 PermAdmissibility-PT-50-CTLFireability-14 5932698 m, 71693 m/sec, 51856962 t fired, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 75/236 27/32 PermAdmissibility-PT-50-CTLFireability-14 6310084 m, 75477 m/sec, 55351344 t fired, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 80/236 29/32 PermAdmissibility-PT-50-CTLFireability-14 6668049 m, 71593 m/sec, 58881483 t fired, .
Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 85/236 30/32 PermAdmissibility-PT-50-CTLFireability-14 7023449 m, 71080 m/sec, 62389878 t fired, .
Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 1 0 4 0 1 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 90/236 32/32 PermAdmissibility-PT-50-CTLFireability-14 7363882 m, 68086 m/sec, 65941057 t fired, .
Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 45 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 PermAdmissibility-PT-50-CTLFireability-13
lola: time limit : 247 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-13
lola: result : false
lola: markings : 800
lola: fired transitions : 1599
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 PermAdmissibility-PT-50-CTLFireability-11
lola: time limit : 268 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/268 5/32 PermAdmissibility-PT-50-CTLFireability-11 1008298 m, 201659 m/sec, 3084761 t fired, .
Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/268 8/32 PermAdmissibility-PT-50-CTLFireability-11 1839328 m, 166206 m/sec, 6349276 t fired, .
Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/268 12/32 PermAdmissibility-PT-50-CTLFireability-11 2710806 m, 174295 m/sec, 9512360 t fired, .
Time elapsed: 395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/268 15/32 PermAdmissibility-PT-50-CTLFireability-11 3525200 m, 162878 m/sec, 12655708 t fired, .
Time elapsed: 400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/268 19/32 PermAdmissibility-PT-50-CTLFireability-11 4332440 m, 161448 m/sec, 15757997 t fired, .
Time elapsed: 405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/268 22/32 PermAdmissibility-PT-50-CTLFireability-11 5142327 m, 161977 m/sec, 18830864 t fired, .
Time elapsed: 410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/268 26/32 PermAdmissibility-PT-50-CTLFireability-11 5918416 m, 155217 m/sec, 21906471 t fired, .
Time elapsed: 415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 40/268 29/32 PermAdmissibility-PT-50-CTLFireability-11 6718964 m, 160109 m/sec, 24988167 t fired, .
Time elapsed: 420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 45/268 32/32 PermAdmissibility-PT-50-CTLFireability-11 7358675 m, 127942 m/sec, 28178120 t fired, .
Time elapsed: 425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 PermAdmissibility-PT-50-CTLFireability-10
lola: time limit : 288 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/288 2/32 PermAdmissibility-PT-50-CTLFireability-10 413558 m, 82711 m/sec, 3223675 t fired, .
Time elapsed: 435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/288 4/32 PermAdmissibility-PT-50-CTLFireability-10 816714 m, 80631 m/sec, 6266107 t fired, .
Time elapsed: 440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/288 6/32 PermAdmissibility-PT-50-CTLFireability-10 1208675 m, 78392 m/sec, 9277622 t fired, .
Time elapsed: 445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/288 7/32 PermAdmissibility-PT-50-CTLFireability-10 1550733 m, 68411 m/sec, 12575057 t fired, .
Time elapsed: 450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 25/288 8/32 PermAdmissibility-PT-50-CTLFireability-10 1860476 m, 61948 m/sec, 15883425 t fired, .
Time elapsed: 455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 30/288 10/32 PermAdmissibility-PT-50-CTLFireability-10 2169698 m, 61844 m/sec, 19094791 t fired, .
Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/288 11/32 PermAdmissibility-PT-50-CTLFireability-10 2480890 m, 62238 m/sec, 22277935 t fired, .
Time elapsed: 465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 40/288 12/32 PermAdmissibility-PT-50-CTLFireability-10 2806114 m, 65044 m/sec, 25426327 t fired, .
Time elapsed: 470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 45/288 14/32 PermAdmissibility-PT-50-CTLFireability-10 3112286 m, 61234 m/sec, 28594077 t fired, .
Time elapsed: 475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 50/288 15/32 PermAdmissibility-PT-50-CTLFireability-10 3426449 m, 62832 m/sec, 31811798 t fired, .
Time elapsed: 480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 55/288 16/32 PermAdmissibility-PT-50-CTLFireability-10 3732353 m, 61180 m/sec, 34964891 t fired, .
Time elapsed: 485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 60/288 18/32 PermAdmissibility-PT-50-CTLFireability-10 4055364 m, 64602 m/sec, 38196767 t fired, .
Time elapsed: 490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 65/288 19/32 PermAdmissibility-PT-50-CTLFireability-10 4363174 m, 61562 m/sec, 41327048 t fired, .
Time elapsed: 495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 70/288 20/32 PermAdmissibility-PT-50-CTLFireability-10 4672308 m, 61826 m/sec, 44412011 t fired, .
Time elapsed: 500 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 75/288 22/32 PermAdmissibility-PT-50-CTLFireability-10 4980795 m, 61697 m/sec, 47582928 t fired, .
Time elapsed: 505 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 80/288 23/32 PermAdmissibility-PT-50-CTLFireability-10 5275101 m, 58861 m/sec, 50822219 t fired, .
Time elapsed: 510 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 85/288 24/32 PermAdmissibility-PT-50-CTLFireability-10 5580621 m, 61104 m/sec, 53928420 t fired, .
Time elapsed: 515 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 90/288 25/32 PermAdmissibility-PT-50-CTLFireability-10 5860585 m, 55992 m/sec, 57017238 t fired, .
Time elapsed: 520 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 95/288 27/32 PermAdmissibility-PT-50-CTLFireability-10 6158617 m, 59606 m/sec, 60053537 t fired, .
Time elapsed: 525 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 100/288 28/32 PermAdmissibility-PT-50-CTLFireability-10 6446889 m, 57654 m/sec, 63066656 t fired, .
Time elapsed: 530 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 105/288 29/32 PermAdmissibility-PT-50-CTLFireability-10 6721488 m, 54919 m/sec, 66066378 t fired, .
Time elapsed: 535 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 110/288 30/32 PermAdmissibility-PT-50-CTLFireability-10 6997320 m, 55166 m/sec, 69091489 t fired, .
Time elapsed: 540 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 115/288 31/32 PermAdmissibility-PT-50-CTLFireability-10 7265006 m, 53537 m/sec, 72115718 t fired, .
Time elapsed: 545 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 120/288 32/32 PermAdmissibility-PT-50-CTLFireability-10 7527020 m, 52402 m/sec, 75315610 t fired, .
Time elapsed: 550 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 555 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 PermAdmissibility-PT-50-CTLFireability-09
lola: time limit : 304 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-09
lola: result : false
lola: markings : 813
lola: fired transitions : 3992
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 PermAdmissibility-PT-50-CTLFireability-08
lola: time limit : 338 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-08
lola: result : true
lola: markings : 201
lola: fired transitions : 200
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 PermAdmissibility-PT-50-CTLFireability-07
lola: time limit : 380 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/380 2/32 PermAdmissibility-PT-50-CTLFireability-07 447309 m, 89461 m/sec, 3591592 t fired, .
Time elapsed: 560 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/380 4/32 PermAdmissibility-PT-50-CTLFireability-07 880309 m, 86600 m/sec, 6979237 t fired, .
Time elapsed: 565 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/380 6/32 PermAdmissibility-PT-50-CTLFireability-07 1296405 m, 83219 m/sec, 10295889 t fired, .
Time elapsed: 570 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/380 8/32 PermAdmissibility-PT-50-CTLFireability-07 1641236 m, 68966 m/sec, 14045441 t fired, .
Time elapsed: 575 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/380 9/32 PermAdmissibility-PT-50-CTLFireability-07 1983173 m, 68387 m/sec, 17649708 t fired, .
Time elapsed: 580 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 30/380 10/32 PermAdmissibility-PT-50-CTLFireability-07 2308808 m, 65127 m/sec, 21207158 t fired, .
Time elapsed: 585 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 35/380 12/32 PermAdmissibility-PT-50-CTLFireability-07 2666108 m, 71460 m/sec, 24664896 t fired, .
Time elapsed: 590 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 40/380 13/32 PermAdmissibility-PT-50-CTLFireability-07 3008945 m, 68567 m/sec, 28190057 t fired, .
Time elapsed: 595 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 45/380 15/32 PermAdmissibility-PT-50-CTLFireability-07 3343686 m, 66948 m/sec, 31708996 t fired, .
Time elapsed: 600 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 50/380 16/32 PermAdmissibility-PT-50-CTLFireability-07 3665064 m, 64275 m/sec, 35219929 t fired, .
Time elapsed: 605 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 55/380 18/32 PermAdmissibility-PT-50-CTLFireability-07 4019226 m, 70832 m/sec, 38754210 t fired, .
Time elapsed: 610 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 60/380 19/32 PermAdmissibility-PT-50-CTLFireability-07 4352008 m, 66556 m/sec, 42216655 t fired, .
Time elapsed: 615 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 65/380 20/32 PermAdmissibility-PT-50-CTLFireability-07 4682693 m, 66137 m/sec, 45608409 t fired, .
Time elapsed: 620 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 70/380 22/32 PermAdmissibility-PT-50-CTLFireability-07 5014827 m, 66426 m/sec, 49089525 t fired, .
Time elapsed: 625 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 75/380 23/32 PermAdmissibility-PT-50-CTLFireability-07 5341790 m, 65392 m/sec, 52652841 t fired, .
Time elapsed: 630 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 80/380 25/32 PermAdmissibility-PT-50-CTLFireability-07 5654287 m, 62499 m/sec, 56084749 t fired, .
Time elapsed: 635 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 85/380 26/32 PermAdmissibility-PT-50-CTLFireability-07 5963517 m, 61846 m/sec, 59439927 t fired, .
Time elapsed: 640 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 90/380 27/32 PermAdmissibility-PT-50-CTLFireability-07 6281010 m, 63498 m/sec, 62758410 t fired, .
Time elapsed: 645 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 95/380 28/32 PermAdmissibility-PT-50-CTLFireability-07 6580051 m, 59808 m/sec, 66106891 t fired, .
Time elapsed: 650 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 100/380 30/32 PermAdmissibility-PT-50-CTLFireability-07 6890067 m, 62003 m/sec, 69429527 t fired, .
Time elapsed: 655 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 105/380 31/32 PermAdmissibility-PT-50-CTLFireability-07 7179572 m, 57901 m/sec, 72764051 t fired, .
Time elapsed: 660 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 110/380 32/32 PermAdmissibility-PT-50-CTLFireability-07 7464159 m, 56917 m/sec, 76167462 t fired, .
Time elapsed: 665 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 670 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 PermAdmissibility-PT-50-CTLFireability-05
lola: time limit : 418 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/418 7/32 PermAdmissibility-PT-50-CTLFireability-05 1226883 m, 245376 m/sec, 1340692 t fired, .
Time elapsed: 675 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/418 14/32 PermAdmissibility-PT-50-CTLFireability-05 2429426 m, 240508 m/sec, 2693738 t fired, .
Time elapsed: 680 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/418 20/32 PermAdmissibility-PT-50-CTLFireability-05 3626016 m, 239318 m/sec, 4042979 t fired, .
Time elapsed: 685 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/418 27/32 PermAdmissibility-PT-50-CTLFireability-05 4804562 m, 235709 m/sec, 5397527 t fired, .
Time elapsed: 690 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 695 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 PermAdmissibility-PT-50-CTLFireability-04
lola: time limit : 484 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/484 7/32 PermAdmissibility-PT-50-CTLFireability-04 1248275 m, 249655 m/sec, 2335961 t fired, .
Time elapsed: 700 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/484 17/32 PermAdmissibility-PT-50-CTLFireability-04 3037273 m, 357799 m/sec, 6012435 t fired, .
Time elapsed: 705 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/484 26/32 PermAdmissibility-PT-50-CTLFireability-04 4776760 m, 347897 m/sec, 9630987 t fired, .
Time elapsed: 710 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 715 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 PermAdmissibility-PT-50-CTLFireability-03
lola: time limit : 577 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/577 3/32 PermAdmissibility-PT-50-CTLFireability-03 674890 m, 134978 m/sec, 3406987 t fired, .
Time elapsed: 720 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/577 6/32 PermAdmissibility-PT-50-CTLFireability-03 1303833 m, 125788 m/sec, 6635533 t fired, .
Time elapsed: 725 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/577 9/32 PermAdmissibility-PT-50-CTLFireability-03 2051710 m, 149575 m/sec, 9584794 t fired, .
Time elapsed: 730 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/577 12/32 PermAdmissibility-PT-50-CTLFireability-03 2770687 m, 143795 m/sec, 12494474 t fired, .
Time elapsed: 735 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/577 15/32 PermAdmissibility-PT-50-CTLFireability-03 3487653 m, 143393 m/sec, 15357825 t fired, .
Time elapsed: 740 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/577 18/32 PermAdmissibility-PT-50-CTLFireability-03 4215129 m, 145495 m/sec, 18073847 t fired, .
Time elapsed: 745 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 35/577 22/32 PermAdmissibility-PT-50-CTLFireability-03 4982304 m, 153435 m/sec, 20718912 t fired, .
Time elapsed: 750 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 40/577 25/32 PermAdmissibility-PT-50-CTLFireability-03 5721618 m, 147862 m/sec, 23350706 t fired, .
Time elapsed: 755 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 45/577 28/32 PermAdmissibility-PT-50-CTLFireability-03 6471136 m, 149903 m/sec, 25949268 t fired, .
Time elapsed: 760 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 50/577 32/32 PermAdmissibility-PT-50-CTLFireability-03 7320711 m, 169915 m/sec, 28425556 t fired, .
Time elapsed: 765 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 770 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 PermAdmissibility-PT-50-CTLFireability-02
lola: time limit : 707 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/707 3/32 PermAdmissibility-PT-50-CTLFireability-02 644823 m, 128964 m/sec, 3345172 t fired, .
Time elapsed: 775 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/707 6/32 PermAdmissibility-PT-50-CTLFireability-02 1286544 m, 128344 m/sec, 6430276 t fired, .
Time elapsed: 780 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/707 8/32 PermAdmissibility-PT-50-CTLFireability-02 1820169 m, 106725 m/sec, 9792654 t fired, .
Time elapsed: 785 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/707 10/32 PermAdmissibility-PT-50-CTLFireability-02 2288080 m, 93582 m/sec, 13192282 t fired, .
Time elapsed: 790 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/707 12/32 PermAdmissibility-PT-50-CTLFireability-02 2751399 m, 92663 m/sec, 16545526 t fired, .
Time elapsed: 795 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/707 14/32 PermAdmissibility-PT-50-CTLFireability-02 3225583 m, 94836 m/sec, 19803849 t fired, .
Time elapsed: 800 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/707 16/32 PermAdmissibility-PT-50-CTLFireability-02 3729167 m, 100716 m/sec, 23088250 t fired, .
Time elapsed: 805 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/707 18/32 PermAdmissibility-PT-50-CTLFireability-02 4225896 m, 99345 m/sec, 26373312 t fired, .
Time elapsed: 810 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/707 20/32 PermAdmissibility-PT-50-CTLFireability-02 4668987 m, 88618 m/sec, 29666504 t fired, .
Time elapsed: 815 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/707 22/32 PermAdmissibility-PT-50-CTLFireability-02 5106865 m, 87575 m/sec, 32959733 t fired, .
Time elapsed: 820 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 55/707 24/32 PermAdmissibility-PT-50-CTLFireability-02 5568037 m, 92234 m/sec, 36188173 t fired, .
Time elapsed: 825 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 60/707 26/32 PermAdmissibility-PT-50-CTLFireability-02 6079093 m, 102211 m/sec, 39397286 t fired, .
Time elapsed: 830 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 65/707 28/32 PermAdmissibility-PT-50-CTLFireability-02 6507003 m, 85582 m/sec, 42597311 t fired, .
Time elapsed: 835 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 70/707 30/32 PermAdmissibility-PT-50-CTLFireability-02 6917043 m, 82008 m/sec, 45729170 t fired, .
Time elapsed: 840 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 75/707 32/32 PermAdmissibility-PT-50-CTLFireability-02 7374923 m, 91576 m/sec, 48758817 t fired, .
Time elapsed: 845 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 850 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 PermAdmissibility-PT-50-CTLFireability-00
lola: time limit : 916 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/916 8/32 PermAdmissibility-PT-50-CTLFireability-00 1594438 m, 318887 m/sec, 2449141 t fired, .
Time elapsed: 855 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/916 14/32 PermAdmissibility-PT-50-CTLFireability-00 3173890 m, 315890 m/sec, 4946453 t fired, .
Time elapsed: 860 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/916 16/32 PermAdmissibility-PT-50-CTLFireability-00 3568186 m, 78859 m/sec, 6537779 t fired, .
Time elapsed: 865 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/916 17/32 PermAdmissibility-PT-50-CTLFireability-00 3753646 m, 37092 m/sec, 8052332 t fired, .
Time elapsed: 870 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/916 18/32 PermAdmissibility-PT-50-CTLFireability-00 3932888 m, 35848 m/sec, 9475351 t fired, .
Time elapsed: 875 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/916 18/32 PermAdmissibility-PT-50-CTLFireability-00 4113862 m, 36194 m/sec, 10849189 t fired, .
Time elapsed: 880 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/916 19/32 PermAdmissibility-PT-50-CTLFireability-00 4303054 m, 37838 m/sec, 12247740 t fired, .
Time elapsed: 885 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/916 20/32 PermAdmissibility-PT-50-CTLFireability-00 4476440 m, 34677 m/sec, 13610937 t fired, .
Time elapsed: 890 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/916 21/32 PermAdmissibility-PT-50-CTLFireability-00 4646880 m, 34088 m/sec, 14948652 t fired, .
Time elapsed: 895 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/916 21/32 PermAdmissibility-PT-50-CTLFireability-00 4806301 m, 31884 m/sec, 16333578 t fired, .
Time elapsed: 900 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/916 22/32 PermAdmissibility-PT-50-CTLFireability-00 4927668 m, 24273 m/sec, 17759719 t fired, .
Time elapsed: 905 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/916 22/32 PermAdmissibility-PT-50-CTLFireability-00 5049573 m, 24381 m/sec, 19181102 t fired, .
Time elapsed: 910 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 65/916 23/32 PermAdmissibility-PT-50-CTLFireability-00 5184205 m, 26926 m/sec, 20578106 t fired, .
Time elapsed: 915 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 70/916 24/32 PermAdmissibility-PT-50-CTLFireability-00 5310789 m, 25316 m/sec, 21972243 t fired, .
Time elapsed: 920 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 75/916 24/32 PermAdmissibility-PT-50-CTLFireability-00 5440365 m, 25915 m/sec, 23358909 t fired, .
Time elapsed: 925 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 80/916 25/32 PermAdmissibility-PT-50-CTLFireability-00 5568713 m, 25669 m/sec, 24724907 t fired, .
Time elapsed: 930 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 85/916 25/32 PermAdmissibility-PT-50-CTLFireability-00 5693780 m, 25013 m/sec, 26126299 t fired, .
Time elapsed: 935 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 90/916 26/32 PermAdmissibility-PT-50-CTLFireability-00 5824679 m, 26179 m/sec, 27495546 t fired, .
Time elapsed: 940 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 95/916 26/32 PermAdmissibility-PT-50-CTLFireability-00 5966322 m, 28328 m/sec, 28870082 t fired, .
Time elapsed: 945 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 100/916 27/32 PermAdmissibility-PT-50-CTLFireability-00 6109571 m, 28649 m/sec, 30267262 t fired, .
Time elapsed: 950 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 105/916 28/32 PermAdmissibility-PT-50-CTLFireability-00 6248654 m, 27816 m/sec, 31675444 t fired, .
Time elapsed: 955 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 110/916 28/32 PermAdmissibility-PT-50-CTLFireability-00 6382438 m, 26756 m/sec, 33069899 t fired, .
Time elapsed: 960 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 115/916 29/32 PermAdmissibility-PT-50-CTLFireability-00 6507067 m, 24925 m/sec, 34442397 t fired, .
Time elapsed: 965 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 120/916 29/32 PermAdmissibility-PT-50-CTLFireability-00 6656063 m, 29799 m/sec, 35826833 t fired, .
Time elapsed: 970 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 125/916 30/32 PermAdmissibility-PT-50-CTLFireability-00 6780361 m, 24859 m/sec, 37231858 t fired, .
Time elapsed: 975 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 130/916 30/32 PermAdmissibility-PT-50-CTLFireability-00 6900478 m, 24023 m/sec, 38618068 t fired, .
Time elapsed: 980 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 135/916 31/32 PermAdmissibility-PT-50-CTLFireability-00 7021777 m, 24259 m/sec, 40003193 t fired, .
Time elapsed: 985 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 140/916 31/32 PermAdmissibility-PT-50-CTLFireability-00 7163149 m, 28274 m/sec, 41381194 t fired, .
Time elapsed: 990 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 145/916 32/32 PermAdmissibility-PT-50-CTLFireability-00 7317720 m, 30914 m/sec, 42778440 t fired, .
Time elapsed: 995 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1000 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 PermAdmissibility-PT-50-CTLFireability-06
lola: time limit : 1300 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/1300 2/32 PermAdmissibility-PT-50-CTLFireability-06 443451 m, 88690 m/sec, 3568837 t fired, .
Time elapsed: 1005 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/1300 4/32 PermAdmissibility-PT-50-CTLFireability-06 882690 m, 87847 m/sec, 6976352 t fired, .
Time elapsed: 1010 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/1300 6/32 PermAdmissibility-PT-50-CTLFireability-06 1311231 m, 85708 m/sec, 10341652 t fired, .
Time elapsed: 1015 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/1300 8/32 PermAdmissibility-PT-50-CTLFireability-06 1648642 m, 67482 m/sec, 14043854 t fired, .
Time elapsed: 1020 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/1300 9/32 PermAdmissibility-PT-50-CTLFireability-06 1985503 m, 67372 m/sec, 17613568 t fired, .
Time elapsed: 1025 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/1300 10/32 PermAdmissibility-PT-50-CTLFireability-06 2310528 m, 65005 m/sec, 21137765 t fired, .
Time elapsed: 1030 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/1300 12/32 PermAdmissibility-PT-50-CTLFireability-06 2666140 m, 71122 m/sec, 24585197 t fired, .
Time elapsed: 1035 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 40/1300 13/32 PermAdmissibility-PT-50-CTLFireability-06 3009472 m, 68666 m/sec, 28092981 t fired, .
Time elapsed: 1040 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 45/1300 15/32 PermAdmissibility-PT-50-CTLFireability-06 3346077 m, 67321 m/sec, 31597538 t fired, .
Time elapsed: 1045 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 50/1300 16/32 PermAdmissibility-PT-50-CTLFireability-06 3667765 m, 64337 m/sec, 35078744 t fired, .
Time elapsed: 1050 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 55/1300 18/32 PermAdmissibility-PT-50-CTLFireability-06 4022564 m, 70959 m/sec, 38581695 t fired, .
Time elapsed: 1055 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 60/1300 19/32 PermAdmissibility-PT-50-CTLFireability-06 4352685 m, 66024 m/sec, 42026115 t fired, .
Time elapsed: 1060 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 65/1300 20/32 PermAdmissibility-PT-50-CTLFireability-06 4684078 m, 66278 m/sec, 45409982 t fired, .
Time elapsed: 1065 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 70/1300 22/32 PermAdmissibility-PT-50-CTLFireability-06 5017741 m, 66732 m/sec, 48893370 t fired, .
Time elapsed: 1070 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 75/1300 23/32 PermAdmissibility-PT-50-CTLFireability-06 5344080 m, 65267 m/sec, 52399160 t fired, .
Time elapsed: 1075 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 80/1300 25/32 PermAdmissibility-PT-50-CTLFireability-06 5653629 m, 61909 m/sec, 55794485 t fired, .
Time elapsed: 1080 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 85/1300 26/32 PermAdmissibility-PT-50-CTLFireability-06 5961421 m, 61558 m/sec, 59127360 t fired, .
Time elapsed: 1085 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 90/1300 27/32 PermAdmissibility-PT-50-CTLFireability-06 6279157 m, 63547 m/sec, 62425143 t fired, .
Time elapsed: 1090 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 95/1300 28/32 PermAdmissibility-PT-50-CTLFireability-06 6578426 m, 59853 m/sec, 65751629 t fired, .
Time elapsed: 1095 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 100/1300 30/32 PermAdmissibility-PT-50-CTLFireability-06 6889513 m, 62217 m/sec, 69053375 t fired, .
Time elapsed: 1100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 105/1300 31/32 PermAdmissibility-PT-50-CTLFireability-06 7177537 m, 57604 m/sec, 72371602 t fired, .
Time elapsed: 1105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 110/1300 32/32 PermAdmissibility-PT-50-CTLFireability-06 7463476 m, 57187 m/sec, 75750445 t fired, .
Time elapsed: 1110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 37 (type EXCL) for 36 PermAdmissibility-PT-50-CTLFireability-12
lola: time limit : 2485 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/2485 4/32 PermAdmissibility-PT-50-CTLFireability-12 773192 m, 154638 m/sec, 4280319 t fired, .
Time elapsed: 1120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/2485 7/32 PermAdmissibility-PT-50-CTLFireability-12 1502938 m, 145949 m/sec, 8488817 t fired, .
Time elapsed: 1125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/2485 10/32 PermAdmissibility-PT-50-CTLFireability-12 2216141 m, 142640 m/sec, 12683611 t fired, .
Time elapsed: 1130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/2485 13/32 PermAdmissibility-PT-50-CTLFireability-12 2908463 m, 138464 m/sec, 16887833 t fired, .
Time elapsed: 1135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/2485 16/32 PermAdmissibility-PT-50-CTLFireability-12 3495734 m, 117454 m/sec, 21033438 t fired, .
Time elapsed: 1140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 30/2485 18/32 PermAdmissibility-PT-50-CTLFireability-12 4067613 m, 114375 m/sec, 25144374 t fired, .
Time elapsed: 1145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 35/2485 20/32 PermAdmissibility-PT-50-CTLFireability-12 4634849 m, 113447 m/sec, 29246243 t fired, .
Time elapsed: 1150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 40/2485 23/32 PermAdmissibility-PT-50-CTLFireability-12 5200604 m, 113151 m/sec, 33357700 t fired, .
Time elapsed: 1155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 45/2485 25/32 PermAdmissibility-PT-50-CTLFireability-12 5761862 m, 112251 m/sec, 37435252 t fired, .
Time elapsed: 1160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 50/2485 28/32 PermAdmissibility-PT-50-CTLFireability-12 6403654 m, 128358 m/sec, 41583362 t fired, .
Time elapsed: 1165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 55/2485 30/32 PermAdmissibility-PT-50-CTLFireability-12 6982984 m, 115866 m/sec, 45704778 t fired, .
Time elapsed: 1170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for PermAdmissibility-PT-50-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-50-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-06: AFAG 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-50-CTLFireability-14: CONJ 0 0 0 0 4 0 2 0
PermAdmissibility-PT-50-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-50-CTLFireability-00: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-01: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-02: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-03: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-04: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-05: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-06: AFAG unknown AGGR
PermAdmissibility-PT-50-CTLFireability-07: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-08: CTL true CTL model checker
PermAdmissibility-PT-50-CTLFireability-09: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-10: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-11: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-12: CTL unknown AGGR
PermAdmissibility-PT-50-CTLFireability-13: CTL false CTL model checker
PermAdmissibility-PT-50-CTLFireability-14: CONJ unknown CONJ
PermAdmissibility-PT-50-CTLFireability-15: CTL unknown AGGR
Time elapsed: 1175 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-50"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is PermAdmissibility-PT-50, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-162089122300546"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-50.tgz
mv PermAdmissibility-PT-50 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;