About the Execution of LoLA for PermAdmissibility-PT-05
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4315.539 | 708488.00 | 703067.00 | 1381.20 | ?FFTT??F??FF?F?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r137-tall-162089122300525.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is PermAdmissibility-PT-05, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-162089122300525
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.0M
-rw-r--r-- 1 mcc users 23K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 163K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 338K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 1.7M May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.7K Mar 28 16:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 35K Mar 28 16:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K Mar 28 16:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 62K Mar 28 16:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Mar 27 06:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K Mar 27 06:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 20K Mar 25 08:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 73K Mar 25 08:17 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.7K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 481K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-PT-05-00
FORMULA_NAME PermAdmissibility-PT-05-01
FORMULA_NAME PermAdmissibility-PT-05-02
FORMULA_NAME PermAdmissibility-PT-05-03
FORMULA_NAME PermAdmissibility-PT-05-04
FORMULA_NAME PermAdmissibility-PT-05-05
FORMULA_NAME PermAdmissibility-PT-05-06
FORMULA_NAME PermAdmissibility-PT-05-07
FORMULA_NAME PermAdmissibility-PT-05-08
FORMULA_NAME PermAdmissibility-PT-05-09
FORMULA_NAME PermAdmissibility-PT-05-10
FORMULA_NAME PermAdmissibility-PT-05-11
FORMULA_NAME PermAdmissibility-PT-05-12
FORMULA_NAME PermAdmissibility-PT-05-13
FORMULA_NAME PermAdmissibility-PT-05-14
FORMULA_NAME PermAdmissibility-PT-05-15
=== Now, execution of the tool begins
BK_START 1620952920161
starting LoLA
BK_INPUT PermAdmissibility-PT-05
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability
FORMULA PermAdmissibility-PT-05-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-05-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-05-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-05-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-05-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-05-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-05-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-05-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-PT-05-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620953628649
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:490
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 41 (type EXCL) for 40 PermAdmissibility-PT-05-12
lola: time limit : 211 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-05-00: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-01: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-02: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-03: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-04: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-05: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-06: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-07: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-05-08: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-09: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-10: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-11: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-12: LTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-05-13: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-14: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 LTL EXCL 4/211 4/32 PermAdmissibility-PT-05-12 603274 m, 120654 m/sec, 3395725 t fired, .
Time elapsed: 7 secs. Pages in use: 4
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PermAdmissibility-PT-05-03: LTL 0 1 0 0 1 0 0 0
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PermAdmissibility-PT-05-05: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-06: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-07: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-05-08: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-09: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-10: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-11: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-12: LTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-05-13: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-14: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 LTL EXCL 9/211 8/32 PermAdmissibility-PT-05-12 1090335 m, 97412 m/sec, 7148457 t fired, .
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PermAdmissibility-PT-05-03: LTL 0 1 0 0 1 0 0 0
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PermAdmissibility-PT-05-05: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-06: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-07: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-05-08: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-09: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-10: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-11: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-12: LTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-05-13: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-14: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 LTL EXCL 14/211 11/32 PermAdmissibility-PT-05-12 1554552 m, 92843 m/sec, 10907727 t fired, .
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PermAdmissibility-PT-05-02: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-03: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-04: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-05: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-06: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-07: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-05-08: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-09: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-10: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-11: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-12: LTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-05-13: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-14: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 LTL EXCL 19/211 14/32 PermAdmissibility-PT-05-12 2041153 m, 97320 m/sec, 14528910 t fired, .
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PermAdmissibility-PT-05-03: LTL 0 1 0 0 1 0 0 0
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PermAdmissibility-PT-05-05: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-06: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-07: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-05-08: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-09: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-10: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-11: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-12: LTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-05-13: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-14: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 LTL EXCL 24/211 17/32 PermAdmissibility-PT-05-12 2467594 m, 85288 m/sec, 18208618 t fired, .
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PermAdmissibility-PT-05-05: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-06: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-07: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-05-08: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-09: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-10: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-11: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-12: LTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-05-13: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-14: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 LTL EXCL 29/211 20/32 PermAdmissibility-PT-05-12 2925642 m, 91609 m/sec, 21877104 t fired, .
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PermAdmissibility-PT-05-05: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-06: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-07: CONJ 0 2 0 0 2 0 0 0
PermAdmissibility-PT-05-08: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-09: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-10: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-11: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-12: LTL 0 0 1 0 1 0 0 0
PermAdmissibility-PT-05-13: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-14: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 LTL EXCL 34/211 23/32 PermAdmissibility-PT-05-12 3370894 m, 89050 m/sec, 25560838 t fired, .
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32 LTL EXCL 35/977 32/32 PermAdmissibility-PT-05-09 4847969 m, 86238 m/sec, 16430390 t fired, .
Time elapsed: 702 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 32 (type EXCL) for PermAdmissibility-PT-05-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-05-01: LTL false LTL model checker
PermAdmissibility-PT-05-02: LTL false LTL model checker
PermAdmissibility-PT-05-07: CONJ false LTL model checker
PermAdmissibility-PT-05-10: LTL false LTL model checker
PermAdmissibility-PT-05-11: LTL false LTL model checker
PermAdmissibility-PT-05-13: LTL false LTL model checker
PermAdmissibility-PT-05-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-PT-05-00: LTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-05-03: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-04: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-PT-05-05: LTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-05-06: LTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-05-08: LTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-05-09: LTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-05-12: LTL 0 0 0 0 1 0 1 0
PermAdmissibility-PT-05-14: LTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 707 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 PermAdmissibility-PT-05-04
lola: time limit : 1446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for PermAdmissibility-PT-05-04
lola: result : true
lola: markings : 160650
lola: fired transitions : 299064
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 10 (type EXCL) for 9 PermAdmissibility-PT-05-03
lola: time limit : 2892 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for PermAdmissibility-PT-05-03
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-PT-05-00: LTL unknown AGGR
PermAdmissibility-PT-05-01: LTL false LTL model checker
PermAdmissibility-PT-05-02: LTL false LTL model checker
PermAdmissibility-PT-05-03: LTL true LTL model checker
PermAdmissibility-PT-05-04: LTL true LTL model checker
PermAdmissibility-PT-05-05: LTL unknown AGGR
PermAdmissibility-PT-05-06: LTL unknown AGGR
PermAdmissibility-PT-05-07: CONJ false LTL model checker
PermAdmissibility-PT-05-08: LTL unknown AGGR
PermAdmissibility-PT-05-09: LTL unknown AGGR
PermAdmissibility-PT-05-10: LTL false LTL model checker
PermAdmissibility-PT-05-11: LTL false LTL model checker
PermAdmissibility-PT-05-12: LTL unknown AGGR
PermAdmissibility-PT-05-13: LTL false LTL model checker
PermAdmissibility-PT-05-14: LTL unknown AGGR
PermAdmissibility-PT-05-15: LTL false LTL model checker
Time elapsed: 708 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-05"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is PermAdmissibility-PT-05, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-162089122300525"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-05.tgz
mv PermAdmissibility-PT-05 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;