About the Execution of LoLA for PermAdmissibility-COL-05
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4732.720 | 226104.00 | 224865.00 | 542.30 | TFFTTT?F?TFFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r137-tall-162089122200477.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is PermAdmissibility-COL-05, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-162089122200477
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 396K
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 105K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 78K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 16:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Mar 28 16:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Mar 28 16:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 16:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.1K Mar 27 06:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 14K Mar 27 06:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Mar 25 08:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K Mar 25 08:17 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 54K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-05-00
FORMULA_NAME PermAdmissibility-COL-05-01
FORMULA_NAME PermAdmissibility-COL-05-02
FORMULA_NAME PermAdmissibility-COL-05-03
FORMULA_NAME PermAdmissibility-COL-05-04
FORMULA_NAME PermAdmissibility-COL-05-05
FORMULA_NAME PermAdmissibility-COL-05-06
FORMULA_NAME PermAdmissibility-COL-05-07
FORMULA_NAME PermAdmissibility-COL-05-08
FORMULA_NAME PermAdmissibility-COL-05-09
FORMULA_NAME PermAdmissibility-COL-05-10
FORMULA_NAME PermAdmissibility-COL-05-11
FORMULA_NAME PermAdmissibility-COL-05-12
FORMULA_NAME PermAdmissibility-COL-05-13
FORMULA_NAME PermAdmissibility-COL-05-14
FORMULA_NAME PermAdmissibility-COL-05-15
=== Now, execution of the tool begins
BK_START 1620950028513
starting LoLA
BK_INPUT PermAdmissibility-COL-05
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability
FORMULA PermAdmissibility-COL-05-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-05-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620950254617
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:490
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: start findlow
lola: CHECK FINDLOW FOR TRANS display1
lola: NOTDEADLOCKFREE
lola: INVENT VAR FOR PLACE aux15
lola: INVENT VAR FOR PLACE aux13
lola: INVENT VAR FOR PLACE c17
lola: CHECK EQ TRANS display1
lola: TR BINDINGS
lola: TR BINDINGS DONE
lola: Places: 208, Transitions: 1024
lola: CHECK FINDLOW FOR TRANS display2
lola: INVENT VAR FOR PLACE aux15
lola: INVENT VAR FOR PLACE aux13
lola: INVENT VAR FOR PLACE c18
lola: CHECK EQ TRANS display2
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: @ trans switch9
lola: @ trans switch3
lola: @ trans switch4
lola: LAUNCH task # 70 (type SKEL/FNDP) for 56 PermAdmissibility-COL-05-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: @ trans display4
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 71 (type SKEL/EQUN) for 56 PermAdmissibility-COL-05-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type SKEL/SRCH) for 56 PermAdmissibility-COL-05-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 73 (type SKEL/SRCH) for 56 PermAdmissibility-COL-05-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 70 (type SKEL/FNDP) for PermAdmissibility-COL-05-12
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 73 (type SKEL/SRCH) for PermAdmissibility-COL-05-12
lola: result : unknown
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CHECK FINDLOW FOR TRANS display3
lola: CANCELED task # 71 (type EQUN) for PermAdmissibility-COL-05-12 (obsolete)
lola: CANCELED task # 72 (type SRCH) for PermAdmissibility-COL-05-12 (obsolete)
lola: @ trans display3
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 76 (type SKEL/FNDP) for 49 PermAdmissibility-COL-05-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/EQUN) for 49 PermAdmissibility-COL-05-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SKEL/SRCH) for 49 PermAdmissibility-COL-05-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/LTLFireability-71.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 79 (type SKEL/SRCH) for 49 PermAdmissibility-COL-05-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type SKEL/FNDP) for PermAdmissibility-COL-05-11
lola: result : true
lola: fired transitions : 13
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 77 (type EQUN) for PermAdmissibility-COL-05-11 (obsolete)
lola: CANCELED task # 78 (type SRCH) for PermAdmissibility-COL-05-11 (obsolete)
lola: CANCELED task # 79 (type SRCH) for PermAdmissibility-COL-05-11 (obsolete)
lola: @ trans switch7
lola: @ trans switch8
lola: @ trans switch11
lola: @ trans switch10
sara: try reading problem file /home/mcc/execution/LTLFireability-77.sara.
lola: FINISHED task # 71 (type SKEL/EQUN) for PermAdmissibility-COL-05-12
lola: result : true
sara: place or transition ordering is non-deterministic
lola: @ trans switch2
lola: @ trans switch1
lola: FINISHED task # 77 (type SKEL/EQUN) for PermAdmissibility-COL-05-11
lola: result : true
lola: @ trans switch5
lola: INVENT VAR FOR PLACE c19
lola: INVENT VAR FOR PLACE aux16
lola: INVENT VAR FOR PLACE aux14
lola: CHECK EQ TRANS display3
lola: @ trans switch12
lola: @ trans display2
lola: @ trans display1
lola: @ trans switch6
lola: CHECK FINDLOW FOR TRANS display4
lola: INVENT VAR FOR PLACE aux14
lola: INVENT VAR FOR PLACE aux16
lola: INVENT VAR FOR PLACE c20
lola: CHECK EQ TRANS display4
lola: CHECK FINDLOW FOR TRANS switch10
lola: INVENT VAR FOR PLACE c14
lola: INVENT VAR FOR PLACE aux9
lola: INVENT VAR FOR PLACE aux11
lola: CHECK EQ TRANS switch10
lola: CHECK FINDLOW FOR TRANS switch11
lola: INVENT VAR FOR PLACE c15
lola: INVENT VAR FOR PLACE aux12
lola: INVENT VAR FOR PLACE aux10
lola: CHECK EQ TRANS switch11
lola: CHECK FINDLOW FOR TRANS switch12
lola: INVENT VAR FOR PLACE c16
lola: INVENT VAR FOR PLACE aux12
lola: INVENT VAR FOR PLACE aux10
lola: CHECK EQ TRANS switch12
lola: CHECK FINDLOW FOR TRANS switch1
lola: INVENT VAR FOR PLACE in1
lola: INVENT VAR FOR PLACE in3
lola: INVENT VAR FOR PLACE c5
lola: CHECK EQ TRANS switch1
lola: CHECK FINDLOW FOR TRANS switch2
lola: INVENT VAR FOR PLACE in1
lola: INVENT VAR FOR PLACE in3
lola: INVENT VAR FOR PLACE c6
lola: CHECK EQ TRANS switch2
lola: CHECK FINDLOW FOR TRANS switch3
lola: INVENT VAR FOR PLACE in2
lola: INVENT VAR FOR PLACE in4
lola: INVENT VAR FOR PLACE c7
lola: CHECK EQ TRANS switch3
lola: CHECK FINDLOW FOR TRANS switch4
lola: INVENT VAR FOR PLACE in2
lola: INVENT VAR FOR PLACE c8
lola: INVENT VAR FOR PLACE in4
lola: CHECK EQ TRANS switch4
lola: CHECK FINDLOW FOR TRANS switch5
lola: INVENT VAR FOR PLACE aux5
lola: INVENT VAR FOR PLACE c9
lola: INVENT VAR FOR PLACE aux7
lola: CHECK EQ TRANS switch5
lola: CHECK FINDLOW FOR TRANS switch6
lola: INVENT VAR FOR PLACE c110
lola: INVENT VAR FOR PLACE aux5
lola: INVENT VAR FOR PLACE aux7
lola: CHECK EQ TRANS switch6
lola: CHECK FINDLOW FOR TRANS switch7
lola: INVENT VAR FOR PLACE c11
lola: INVENT VAR FOR PLACE aux8
lola: INVENT VAR FOR PLACE aux6
lola: CHECK EQ TRANS switch7
lola: CHECK FINDLOW FOR TRANS switch8
lola: INVENT VAR FOR PLACE c12
lola: INVENT VAR FOR PLACE aux8
lola: INVENT VAR FOR PLACE aux6
lola: CHECK EQ TRANS switch8
lola: CHECK FINDLOW FOR TRANS switch9
lola: INVENT VAR FOR PLACE c13
lola: INVENT VAR FOR PLACE aux9
lola: INVENT VAR FOR PLACE aux11
lola: CHECK EQ TRANS switch9
lola: findlow criterion satisfied
lola: Time for checking findlow: 1.000000
lola: TRANS 0: display1 is minimal, eq to 0
lola: TRANS 1: display2 is minimal, eq to 1
lola: TRANS 2: display3 is minimal, eq to 2
lola: TRANS 3: display4 is minimal, eq to 3
lola: TRANS 4: switch10 is minimal, eq to 4
lola: TRANS 5: switch11 is minimal, eq to 5
lola: TRANS 6: switch12 is minimal, eq to 6
lola: TRANS 7: switch1 is minimal, eq to 7
lola: TRANS 8: switch2 is minimal, eq to 8
lola: TRANS 9: switch3 is minimal, eq to 9
lola: TRANS 10: switch4 is minimal, eq to 10
lola: TRANS 11: switch5 is minimal, eq to 11
lola: TRANS 12: switch6 is minimal, eq to 12
lola: TRANS 13: switch7 is minimal, eq to 13
lola: TRANS 14: switch8 is minimal, eq to 14
lola: TRANS 15: switch9 is minimal, eq to 15
lola: HLFINDLOW
lola: HLFINDLOW
lola: HLFINDLOW
lola: HLFINDLOW
lola: HLFINDLOW
lola: HLFINDLOW
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-05-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-05-01: CONJ 3 0 0 0 0 0 0 0
PermAdmissibility-COL-05-02: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-03: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-05: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-05-06: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-07: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-05-08: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-05-10: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-05-11: CONJ 0 0 0 0 3 0 0 2
PermAdmissibility-COL-05-12: AG 0 0 0 0 3 0 0 1
PermAdmissibility-COL-05-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 5 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-05-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-05-01: CONJ 3 0 0 0 0 0 0 0
PermAdmissibility-COL-05-02: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-03: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-05: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-05-06: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-07: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-05-08: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-05-10: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-05-11: CONJ 0 0 0 0 3 0 0 2
PermAdmissibility-COL-05-12: AG 0 0 0 0 3 0 0 1
PermAdmissibility-COL-05-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 10 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-05-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-05-01: CONJ 3 0 0 0 0 0 0 0
PermAdmissibility-COL-05-02: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-03: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-05-04: LTL 0 0 0 0 1 0 0 0
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37 LTL EXCL 2/311 4/32 PermAdmissibility-COL-05-08 512077 m, 102415 m/sec, 769738 t fired, .
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37 LTL EXCL 7/311 11/32 PermAdmissibility-COL-05-08 1632326 m, 224049 m/sec, 2600918 t fired, .
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37 LTL EXCL 17/311 25/32 PermAdmissibility-COL-05-08 3814518 m, 218987 m/sec, 6188802 t fired, .
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37 LTL EXCL 22/311 32/32 PermAdmissibility-COL-05-08 4894857 m, 216067 m/sec, 7992495 t fired, .
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lola: LAUNCH task # 63 (type EXCL) for 62 PermAdmissibility-COL-05-14
lola: time limit : 340 sec
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lola: FINISHED task # 63 (type EXCL) for PermAdmissibility-COL-05-14
lola: result : false
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PermAdmissibility-COL-05-10: CONJ false state space
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27 LTL EXCL 20/485 29/32 PermAdmissibility-COL-05-06 4393816 m, 214370 m/sec, 7172357 t fired, .
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PermAdmissibility-COL-05-10: CONJ false state space
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lola: LAUNCH task # 15 (type EXCL) for 14 PermAdmissibility-COL-05-02
lola: time limit : 562 sec
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lola: FINISHED task # 15 (type EXCL) for PermAdmissibility-COL-05-02
lola: result : false
lola: markings : 130
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lola: LAUNCH task # 10 (type EXCL) for 3 PermAdmissibility-COL-05-01
lola: time limit : 675 sec
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lola: time limit : 843 sec
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lola: FINISHED task # 21 (type EXCL) for PermAdmissibility-COL-05-04
lola: result : true
lola: markings : 160650
lola: fired transitions : 299064
lola: time used : 1.000000
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lola: result : true
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lola: time limit : 1687 sec
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lola: FINISHED task # 60 (type EXCL) for PermAdmissibility-COL-05-13
lola: result : false
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lola: result : true
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lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-COL-05-00: LTL true skeleton: LTL model checker
PermAdmissibility-COL-05-01: CONJ false LTL model checker
PermAdmissibility-COL-05-02: LTL false LTL model checker
PermAdmissibility-COL-05-03: LTL true LTL model checker
PermAdmissibility-COL-05-04: LTL true LTL model checker
PermAdmissibility-COL-05-05: LTL true skeleton: LTL model checker
PermAdmissibility-COL-05-06: LTL unknown AGGR
PermAdmissibility-COL-05-07: CONJ false LTL model checker
PermAdmissibility-COL-05-08: LTL unknown AGGR
PermAdmissibility-COL-05-09: LTL true skeleton: LTL model checker
PermAdmissibility-COL-05-10: CONJ false state space
PermAdmissibility-COL-05-11: CONJ false findpath
PermAdmissibility-COL-05-12: AG false findpath
PermAdmissibility-COL-05-13: LTL false LTL model checker
PermAdmissibility-COL-05-14: LTL false LTL model checker
PermAdmissibility-COL-05-15: LTL true LTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-05"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-05, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-162089122200477"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-05.tgz
mv PermAdmissibility-COL-05 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;