About the Execution of LoLA for PermAdmissibility-COL-01
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1458.199 | 135380.00 | 138975.00 | 289.90 | TTFFTTTTFTFFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r137-tall-162089122200461.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is PermAdmissibility-COL-01, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-162089122200461
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 380K
-rw-r--r-- 1 mcc users 8.5K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 88K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Mar 28 16:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Mar 28 16:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Mar 28 16:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 16:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Mar 27 06:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 06:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Mar 25 08:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 21K Mar 25 08:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 54K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-01-00
FORMULA_NAME PermAdmissibility-COL-01-01
FORMULA_NAME PermAdmissibility-COL-01-02
FORMULA_NAME PermAdmissibility-COL-01-03
FORMULA_NAME PermAdmissibility-COL-01-04
FORMULA_NAME PermAdmissibility-COL-01-05
FORMULA_NAME PermAdmissibility-COL-01-06
FORMULA_NAME PermAdmissibility-COL-01-07
FORMULA_NAME PermAdmissibility-COL-01-08
FORMULA_NAME PermAdmissibility-COL-01-09
FORMULA_NAME PermAdmissibility-COL-01-10
FORMULA_NAME PermAdmissibility-COL-01-11
FORMULA_NAME PermAdmissibility-COL-01-12
FORMULA_NAME PermAdmissibility-COL-01-13
FORMULA_NAME PermAdmissibility-COL-01-14
FORMULA_NAME PermAdmissibility-COL-01-15
=== Now, execution of the tool begins
BK_START 1620949552035
starting LoLA
BK_INPUT PermAdmissibility-COL-01
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability
FORMULA PermAdmissibility-COL-01-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA PermAdmissibility-COL-01-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620949687415
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:184
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:496
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:490
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:499
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: NOTDEADLOCKFREE
lola: start findlow
lola: CHECK FINDLOW FOR TRANS display1
lola: INVENT VAR FOR PLACE aux15
lola: INVENT VAR FOR PLACE aux13
lola: INVENT VAR FOR PLACE c17
lola: CHECK EQ TRANS display1
lola: LAUNCH INITIAL
lola: LAUNCH task # 72 (type SKEL/CNST) for 6 PermAdmissibility-COL-01-02
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 73 (type SKEL/CNST) for 17 PermAdmissibility-COL-01-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 74 (type SKEL/CNST) for 40 PermAdmissibility-COL-01-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 72 (type SKEL/CNST) for PermAdmissibility-COL-01-02
lola: result : false
lola: FINISHED task # 73 (type SKEL/CNST) for PermAdmissibility-COL-01-03
lola: result : false
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: FINISHED task # 74 (type SKEL/CNST) for PermAdmissibility-COL-01-08
lola: result : false
lola: LAUNCH INITIAL
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 75 (type SKEL/CNST) for 56 PermAdmissibility-COL-01-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 75 (type SKEL/CNST) for PermAdmissibility-COL-01-12
lola: result : true
lola: TR BINDINGS
lola: CHECK FINDLOW FOR TRANS display2
lola: INVENT VAR FOR PLACE aux15
lola: INVENT VAR FOR PLACE aux13
lola: INVENT VAR FOR PLACE c18
lola: CHECK EQ TRANS display2
lola: TR BINDINGS DONE
lola: Places: 208, Transitions: 1024
lola: @ trans switch9
lola: @ trans switch3
lola: @ trans switch4
lola: @ trans display4
lola: @ trans display3
lola: @ trans switch7
lola: @ trans switch8
lola: @ trans switch11
lola: @ trans switch10
lola: CHECK FINDLOW FOR TRANS display3
lola: @ trans switch2
lola: @ trans switch1
lola: @ trans switch5
lola: @ trans switch12
lola: INVENT VAR FOR PLACE aux16
lola: INVENT VAR FOR PLACE aux14
lola: INVENT VAR FOR PLACE c19
lola: CHECK EQ TRANS display3
lola: @ trans display2
lola: @ trans display1
lola: @ trans switch6
lola: CHECK FINDLOW FOR TRANS display4
lola: INVENT VAR FOR PLACE aux14
lola: INVENT VAR FOR PLACE aux16
lola: INVENT VAR FOR PLACE c20
lola: CHECK EQ TRANS display4
lola: CHECK FINDLOW FOR TRANS switch10
lola: INVENT VAR FOR PLACE c14
lola: INVENT VAR FOR PLACE aux11
lola: INVENT VAR FOR PLACE aux9
lola: CHECK EQ TRANS switch10
lola: CHECK FINDLOW FOR TRANS switch11
lola: INVENT VAR FOR PLACE c15
lola: INVENT VAR FOR PLACE aux12
lola: INVENT VAR FOR PLACE aux10
lola: CHECK EQ TRANS switch11
lola: CHECK FINDLOW FOR TRANS switch12
lola: INVENT VAR FOR PLACE aux12
lola: INVENT VAR FOR PLACE aux10
lola: INVENT VAR FOR PLACE c16
lola: CHECK EQ TRANS switch12
lola: CHECK FINDLOW FOR TRANS switch1
lola: INVENT VAR FOR PLACE in3
lola: INVENT VAR FOR PLACE in1
lola: INVENT VAR FOR PLACE c5
lola: CHECK EQ TRANS switch1
lola: CHECK FINDLOW FOR TRANS switch2
lola: INVENT VAR FOR PLACE in1
lola: INVENT VAR FOR PLACE in3
lola: INVENT VAR FOR PLACE c6
lola: CHECK EQ TRANS switch2
lola: CHECK FINDLOW FOR TRANS switch3
lola: INVENT VAR FOR PLACE c7
lola: INVENT VAR FOR PLACE in2
lola: INVENT VAR FOR PLACE in4
lola: CHECK EQ TRANS switch3
lola: CHECK FINDLOW FOR TRANS switch4
lola: INVENT VAR FOR PLACE in2
lola: INVENT VAR FOR PLACE in4
lola: INVENT VAR FOR PLACE c8
lola: CHECK EQ TRANS switch4
lola: CHECK FINDLOW FOR TRANS switch5
lola: INVENT VAR FOR PLACE aux7
lola: INVENT VAR FOR PLACE aux5
lola: INVENT VAR FOR PLACE c9
lola: CHECK EQ TRANS switch5
lola: CHECK FINDLOW FOR TRANS switch6
lola: INVENT VAR FOR PLACE aux7
lola: INVENT VAR FOR PLACE c110
lola: INVENT VAR FOR PLACE aux5
lola: CHECK EQ TRANS switch6
lola: CHECK FINDLOW FOR TRANS switch7
lola: INVENT VAR FOR PLACE aux6
lola: INVENT VAR FOR PLACE aux8
lola: INVENT VAR FOR PLACE c11
lola: CHECK EQ TRANS switch7
lola: CHECK FINDLOW FOR TRANS switch8
lola: INVENT VAR FOR PLACE aux8
lola: INVENT VAR FOR PLACE aux6
lola: INVENT VAR FOR PLACE c12
lola: CHECK EQ TRANS switch8
lola: CHECK FINDLOW FOR TRANS switch9
lola: INVENT VAR FOR PLACE aux9
lola: INVENT VAR FOR PLACE aux11
lola: INVENT VAR FOR PLACE c13
lola: CHECK EQ TRANS switch9
lola: findlow criterion satisfied
lola: Time for checking findlow: 1.000000
lola: TRANS 0: display1 is minimal, eq to 0
lola: TRANS 1: display2 is minimal, eq to 1
lola: TRANS 2: display3 is minimal, eq to 2
lola: TRANS 3: display4 is minimal, eq to 3
lola: TRANS 4: switch10 is minimal, eq to 4
lola: TRANS 5: switch11 is minimal, eq to 5
lola: TRANS 6: switch12 is minimal, eq to 6
lola: TRANS 7: switch1 is minimal, eq to 7
lola: TRANS 8: switch2 is minimal, eq to 8
lola: TRANS 9: switch3 is minimal, eq to 9
lola: TRANS 10: switch4 is minimal, eq to 10
lola: TRANS 11: switch5 is minimal, eq to 11
lola: TRANS 12: switch6 is minimal, eq to 12
lola: TRANS 13: switch7 is minimal, eq to 13
lola: TRANS 14: switch8 is minimal, eq to 14
lola: TRANS 15: switch9 is minimal, eq to 15
lola: HLFINDLOW
lola: HLFINDLOW
lola: HLFINDLOW
lola: HLFINDLOW
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-03: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-01-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-01-06: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-07: F 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
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PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-01-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-01-06: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-07: F 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 0 0 0 1 0 0 0
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PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
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PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-01-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-01-06: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-07: F 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 0 0 0 1 0 0 0
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PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
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PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-01-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-01-06: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-07: F 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 0 0 0 1 0 0 0
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PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
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PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-01-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-01-06: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-07: F 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 0 0 0 1 0 0 0
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PermAdmissibility-COL-01-06: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-07: F 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-03: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-01-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-01-06: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-07: F 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-03: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-01-00: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-01: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-04: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-05: CONJ 0 0 0 0 2 0 0 0
PermAdmissibility-COL-01-06: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-07: F 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-09: LTL 1 0 0 0 0 0 0 0
PermAdmissibility-COL-01-10: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-13: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 0 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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# running tasks: 0 of 4 Visible: 16
lola: LAUNCH task # 76 (type SKEL/SRCH) for 0 PermAdmissibility-COL-01-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SKEL/SRCH) for 47 PermAdmissibility-COL-01-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SKEL/SRCH) for 34 PermAdmissibility-COL-01-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type SKEL/SRCH) for PermAdmissibility-COL-01-00
lola: result : true
lola: markings : 18
lola: fired transitions : 18
lola: time used : 0.000000
lola: memory pages used : 1
lola: Rule S: 432 transitions removed,40 places removed
lola: FINISHED task # 79 (type SKEL/SRCH) for PermAdmissibility-COL-01-06
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 78 (type SKEL/SRCH) for PermAdmissibility-COL-01-09
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: planning for PermAdmissibility-COL-01-00 stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for PermAdmissibility-COL-01-06 stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for PermAdmissibility-COL-01-09 stopped (result already fixed).
lola: LAUNCH task # 64 (type EXCL) for 63 PermAdmissibility-COL-01-13
lola: time limit : 315 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for PermAdmissibility-COL-01-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 27 PermAdmissibility-COL-01-05
lola: time limit : 346 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-COL-01-00: LTL true skeleton: LTL model checker
PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-03: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-06: LTL true skeleton: LTL model checker
PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-09: LTL true skeleton: LTL model checker
PermAdmissibility-COL-01-13: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PermAdmissibility-COL-01-01: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-01-04: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-01-05: CONJ 0 1 1 0 2 0 0 0
PermAdmissibility-COL-01-07: F 0 1 0 0 1 0 0 0
PermAdmissibility-COL-01-10: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-01-11: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-01-12: CONJ 0 1 0 0 1 0 0 0
PermAdmissibility-COL-01-14: LTL 0 1 0 0 1 0 0 0
PermAdmissibility-COL-01-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 LTL EXCL 0/346 1/32 PermAdmissibility-COL-01-05 8386 m, 1677 m/sec, 15281 t fired, .
Time elapsed: 135 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 30 (type EXCL) for PermAdmissibility-COL-01-05
lola: result : true
lola: markings : 9863
lola: fired transitions : 17913
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 70 (type EXCL) for 69 PermAdmissibility-COL-01-15
lola: time limit : 385 sec
lola: memory limit: 32 pages
lola: FINISHED task # 70 (type EXCL) for PermAdmissibility-COL-01-15
lola: result : false
lola: markings : 28
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 PermAdmissibility-COL-01-11
lola: time limit : 433 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for PermAdmissibility-COL-01-11
lola: result : false
lola: markings : 17
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 PermAdmissibility-COL-01-10
lola: time limit : 495 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for PermAdmissibility-COL-01-10
lola: result : false
lola: markings : 5029
lola: fired transitions : 9147
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 PermAdmissibility-COL-01-04
lola: time limit : 577 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for PermAdmissibility-COL-01-04
lola: result : true
lola: markings : 25
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 PermAdmissibility-COL-01-01
lola: time limit : 693 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for PermAdmissibility-COL-01-01
lola: result : true
lola: markings : 17
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 80 (type EXCL) for 37 PermAdmissibility-COL-01-07
lola: time limit : 866 sec
lola: memory limit: 32 pages
lola: FINISHED task # 80 (type EXCL) for PermAdmissibility-COL-01-07
lola: result : false
lola: markings : 169
lola: fired transitions : 168
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 67 (type EXCL) for 66 PermAdmissibility-COL-01-14
lola: time limit : 1155 sec
lola: memory limit: 32 pages
lola: FINISHED task # 67 (type EXCL) for PermAdmissibility-COL-01-14
lola: result : false
lola: markings : 18
lola: fired transitions : 18
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 56 PermAdmissibility-COL-01-12
lola: time limit : 1732 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for PermAdmissibility-COL-01-12
lola: result : false
lola: markings : 17
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 27 PermAdmissibility-COL-01-05
lola: time limit : 3465 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for PermAdmissibility-COL-01-05
lola: result : true
lola: markings : 1361
lola: fired transitions : 2712
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PermAdmissibility-COL-01-00: LTL true skeleton: LTL model checker
PermAdmissibility-COL-01-01: LTL true LTL model checker
PermAdmissibility-COL-01-02: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-03: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-04: LTL true LTL model checker
PermAdmissibility-COL-01-05: CONJ true CONJ
PermAdmissibility-COL-01-06: LTL true skeleton: LTL model checker
PermAdmissibility-COL-01-07: F true state space / EG
PermAdmissibility-COL-01-08: CONJ false skeleton: preprocessing
PermAdmissibility-COL-01-09: LTL true skeleton: LTL model checker
PermAdmissibility-COL-01-10: LTL false LTL model checker
PermAdmissibility-COL-01-11: LTL false LTL model checker
PermAdmissibility-COL-01-12: CONJ false LTL model checker
PermAdmissibility-COL-01-13: LTL true LTL model checker
PermAdmissibility-COL-01-14: LTL false LTL model checker
PermAdmissibility-COL-01-15: LTL false LTL model checker
Time elapsed: 135 secs. Pages in use: 3
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-01"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is PermAdmissibility-COL-01, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-162089122200461"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-01.tgz
mv PermAdmissibility-COL-01 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;