About the Execution of LoLA for MAPK-PT-00040
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5601.039 | 140307.00 | 126546.00 | 297.30 | ????T??TTTFF?TTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r118-tall-162075403400714.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is MAPK-PT-00040, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r118-tall-162075403400714
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 384K
-rw-r--r-- 1 mcc users 13K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.4K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 81K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Mar 28 16:19 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Mar 28 16:19 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K Mar 28 16:19 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 28 16:19 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Mar 27 06:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 27 06:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Mar 25 07:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 21K Mar 25 07:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 6 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 25K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MAPK-PT-00040-CTLFireability-00
FORMULA_NAME MAPK-PT-00040-CTLFireability-01
FORMULA_NAME MAPK-PT-00040-CTLFireability-02
FORMULA_NAME MAPK-PT-00040-CTLFireability-03
FORMULA_NAME MAPK-PT-00040-CTLFireability-04
FORMULA_NAME MAPK-PT-00040-CTLFireability-05
FORMULA_NAME MAPK-PT-00040-CTLFireability-06
FORMULA_NAME MAPK-PT-00040-CTLFireability-07
FORMULA_NAME MAPK-PT-00040-CTLFireability-08
FORMULA_NAME MAPK-PT-00040-CTLFireability-09
FORMULA_NAME MAPK-PT-00040-CTLFireability-10
FORMULA_NAME MAPK-PT-00040-CTLFireability-11
FORMULA_NAME MAPK-PT-00040-CTLFireability-12
FORMULA_NAME MAPK-PT-00040-CTLFireability-13
FORMULA_NAME MAPK-PT-00040-CTLFireability-14
FORMULA_NAME MAPK-PT-00040-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620838168970
starting LoLA
BK_INPUT MAPK-PT-00040
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA MAPK-PT-00040-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620838309277
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 1 (type EXCL) for 0 MAPK-PT-00040-CTLFireability-00
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type FNDP) for 12 MAPK-PT-00040-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 12 MAPK-PT-00040-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SRCH) for 12 MAPK-PT-00040-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 67 (type SRCH) for MAPK-PT-00040-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 64 (type FNDP) for MAPK-PT-00040-CTLFireability-04
lola: result : true
lola: fired transitions : 156
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: CANCELED task # 65 (type EQUN) for MAPK-PT-00040-CTLFireability-04 (obsolete)
lola: LAUNCH task # 68 (type FNDP) for 32 MAPK-PT-00040-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type EQUN) for 32 MAPK-PT-00040-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SRCH) for 32 MAPK-PT-00040-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 65 (type EQUN) for MAPK-PT-00040-CTLFireability-04
lola: result : unknown
lola: FINISHED task # 68 (type FNDP) for MAPK-PT-00040-CTLFireability-08
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 69 (type EQUN) for MAPK-PT-00040-CTLFireability-08 (obsolete)
lola: CANCELED task # 71 (type SRCH) for MAPK-PT-00040-CTLFireability-08 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
sara: try reading problem file /home/mcc/execution/CTLFireability-69.sara.
lola: FINISHED task # 69 (type EQUN) for MAPK-PT-00040-CTLFireability-08
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/257 8/32 MAPK-PT-00040-CTLFireability-00 1762906 m, 352581 m/sec, 9766090 t fired, .
Time elapsed: 6 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/257 15/32 MAPK-PT-00040-CTLFireability-00 3553456 m, 358110 m/sec, 19329108 t fired, .
Time elapsed: 11 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/257 22/32 MAPK-PT-00040-CTLFireability-00 5260550 m, 341418 m/sec, 28678901 t fired, .
Time elapsed: 16 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/257 30/32 MAPK-PT-00040-CTLFireability-00 7058705 m, 359631 m/sec, 37996897 t fired, .
Time elapsed: 21 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for MAPK-PT-00040-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 26 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 62 (type EXCL) for 61 MAPK-PT-00040-CTLFireability-15
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for MAPK-PT-00040-CTLFireability-15
lola: result : false
lola: markings : 6
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 55 MAPK-PT-00040-CTLFireability-13
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for MAPK-PT-00040-CTLFireability-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 MAPK-PT-00040-CTLFireability-10
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for MAPK-PT-00040-CTLFireability-10
lola: result : false
lola: markings : 653985
lola: fired transitions : 1600809
lola: time used : 0.000000
lola: memory pages used : 3
lola: LAUNCH task # 44 (type EXCL) for 43 MAPK-PT-00040-CTLFireability-09
lola: time limit : 357 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for MAPK-PT-00040-CTLFireability-09
lola: result : true
lola: markings : 653986
lola: fired transitions : 1600811
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 30 (type EXCL) for 29 MAPK-PT-00040-CTLFireability-07
lola: time limit : 397 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for MAPK-PT-00040-CTLFireability-07
lola: result : true
lola: markings : 6
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 MAPK-PT-00040-CTLFireability-06
lola: time limit : 446 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 4/446 8/32 MAPK-PT-00040-CTLFireability-06 1786398 m, 357279 m/sec, 6154915 t fired, .
Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 9/446 18/32 MAPK-PT-00040-CTLFireability-06 4265003 m, 495721 m/sec, 14685962 t fired, .
Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 14/446 28/32 MAPK-PT-00040-CTLFireability-06 6691779 m, 485355 m/sec, 23040717 t fired, .
Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 27 (type EXCL) for MAPK-PT-00040-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 24 (type EXCL) for 23 MAPK-PT-00040-CTLFireability-05
lola: time limit : 507 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 5/507 15/32 MAPK-PT-00040-CTLFireability-05 3465658 m, 693131 m/sec, 8468811 t fired, .
Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 10/507 28/32 MAPK-PT-00040-CTLFireability-05 6612195 m, 629307 m/sec, 16154451 t fired, .
Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 24 (type EXCL) for MAPK-PT-00040-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 MAPK-PT-00040-CTLFireability-02
lola: time limit : 589 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/589 9/32 MAPK-PT-00040-CTLFireability-02 1998540 m, 399708 m/sec, 6249731 t fired, .
Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/589 19/32 MAPK-PT-00040-CTLFireability-02 4538909 m, 508073 m/sec, 12313150 t fired, .
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/589 29/32 MAPK-PT-00040-CTLFireability-02 6839558 m, 460129 m/sec, 18529175 t fired, .
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for MAPK-PT-00040-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 MAPK-PT-00040-CTLFireability-01
lola: time limit : 703 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/703 7/32 MAPK-PT-00040-CTLFireability-01 1606323 m, 321264 m/sec, 7628347 t fired, .
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/703 12/32 MAPK-PT-00040-CTLFireability-01 2699228 m, 218581 m/sec, 14349902 t fired, .
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/703 18/32 MAPK-PT-00040-CTLFireability-01 4092622 m, 278678 m/sec, 21385191 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/703 22/32 MAPK-PT-00040-CTLFireability-01 5255398 m, 232555 m/sec, 27971924 t fired, .
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/703 28/32 MAPK-PT-00040-CTLFireability-01 6632778 m, 275476 m/sec, 34961391 t fired, .
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for MAPK-PT-00040-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 53 (type EXCL) for 52 MAPK-PT-00040-CTLFireability-12
lola: time limit : 872 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 AGEF EXCL 5/872 12/32 MAPK-PT-00040-CTLFireability-12 3160091 m, 632018 m/sec, 7951067 t fired, .
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 AGEF EXCL 10/872 23/32 MAPK-PT-00040-CTLFireability-12 5918288 m, 551639 m/sec, 14968198 t fired, .
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 53 (type EXCL) for MAPK-PT-00040-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 72 (type EXCL) for 9 MAPK-PT-00040-CTLFireability-03
lola: time limit : 1158 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 AGEF EXCL 5/1158 14/32 MAPK-PT-00040-CTLFireability-03 3654666 m, 730933 m/sec, 8930344 t fired, .
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 AGEF EXCL 10/1158 28/32 MAPK-PT-00040-CTLFireability-03 7174901 m, 704047 m/sec, 17528882 t fired, .
Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 72 (type EXCL) for MAPK-PT-00040-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 50 (type EXCL) for 49 MAPK-PT-00040-CTLFireability-11
lola: time limit : 1729 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for MAPK-PT-00040-CTLFireability-11
lola: result : false
lola: markings : 6
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 58 MAPK-PT-00040-CTLFireability-14
lola: time limit : 3459 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for MAPK-PT-00040-CTLFireability-14
lola: result : true
lola: markings : 2859
lola: fired transitions : 9652
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-00: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-01: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-02: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-03: EFAG unknown AGGR
MAPK-PT-00040-CTLFireability-04: DISJ true findpath
MAPK-PT-00040-CTLFireability-05: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-06: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-07: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-08: DISJ true findpath
MAPK-PT-00040-CTLFireability-09: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-10: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-11: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-12: AGEF unknown AGGR
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-14: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL false CTL model checker
Time elapsed: 141 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPK-PT-00040"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is MAPK-PT-00040, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r118-tall-162075403400714"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MAPK-PT-00040.tgz
mv MAPK-PT-00040 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;