About the Execution of LoLA for LamportFastMutEx-PT-4
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1744.688 | 115828.00 | 117374.00 | 189.70 | TFFFFFFFFTTTTTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r118-tall-162075403300658.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is LamportFastMutEx-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r118-tall-162075403300658
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 51K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 285K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 89K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 476K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 6.9K Apr 26 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 36K Apr 26 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 8.5K Apr 26 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 39K Apr 26 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.7K Mar 27 06:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 29K Mar 27 06:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Mar 25 07:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 36K Mar 25 07:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.4K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.6K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 2 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 114K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-00
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-01
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-02
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-03
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-04
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-05
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-06
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-07
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-08
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-09
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-10
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-11
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-12
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-13
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-14
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620827002557
starting LoLA
BK_INPUT LamportFastMutEx-PT-4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA LamportFastMutEx-PT-4-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620827118385
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 50 transitions removed,33 places removed
lola: ASSUMEDDEADLOCKFREE
lola: LAUNCH task # 56 (type SKEL/SRCH) for 6 LamportFastMutEx-PT-4-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type SKEL/SRCH) for LamportFastMutEx-PT-4-CTLFireability-02
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 17 (type EXCL) for 16 LamportFastMutEx-PT-4-CTLFireability-04
lola: time limit : 119 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 17 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-04
lola: result : false
lola: markings : 7632
lola: fired transitions : 12480
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 LamportFastMutEx-PT-4-CTLFireability-12
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 41 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-12
lola: result : true
lola: markings : 3441
lola: fired transitions : 5181
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 LamportFastMutEx-PT-4-CTLFireability-11
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-4-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/239 5/32 LamportFastMutEx-PT-4-CTLFireability-11 1123568 m, 224713 m/sec, 4924663 t fired, .
Time elapsed: 7 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 38 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-11
lola: result : true
lola: markings : 1914783
lola: fired transitions : 9046051
lola: time used : 9.000000
lola: memory pages used : 8
lola: LAUNCH task # 54 (type EXCL) for 53 LamportFastMutEx-PT-4-CTLFireability-15
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-15
lola: result : true
lola: markings : 715
lola: fired transitions : 1026
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 46 LamportFastMutEx-PT-4-CTLFireability-14
lola: time limit : 276 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 1 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 1/276 1/32 LamportFastMutEx-PT-4-CTLFireability-14 176823 m, 35364 m/sec, 563506 t fired, .
Time elapsed: 12 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 1 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 6/276 5/32 LamportFastMutEx-PT-4-CTLFireability-14 1192404 m, 203116 m/sec, 5766492 t fired, .
Time elapsed: 17 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 49 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-14
lola: result : false
lola: markings : 1914784
lola: fired transitions : 9782485
lola: time used : 10.000000
lola: memory pages used : 8
lola: LAUNCH task # 44 (type EXCL) for 43 LamportFastMutEx-PT-4-CTLFireability-13
lola: time limit : 298 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 1/298 1/32 LamportFastMutEx-PT-4-CTLFireability-13 143531 m, 28706 m/sec, 652977 t fired, .
Time elapsed: 22 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 6/298 5/32 LamportFastMutEx-PT-4-CTLFireability-13 1073469 m, 185987 m/sec, 6475620 t fired, .
Time elapsed: 27 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 11/298 8/32 LamportFastMutEx-PT-4-CTLFireability-13 1881483 m, 161602 m/sec, 11839470 t fired, .
Time elapsed: 32 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 44 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-13
lola: result : true
lola: markings : 1892892
lola: fired transitions : 12116104
lola: time used : 11.000000
lola: memory pages used : 8
lola: LAUNCH task # 35 (type EXCL) for 34 LamportFastMutEx-PT-4-CTLFireability-10
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-10
lola: result : true
lola: markings : 26
lola: fired transitions : 105
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 LamportFastMutEx-PT-4-CTLFireability-08
lola: time limit : 356 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/356 5/32 LamportFastMutEx-PT-4-CTLFireability-08 1128639 m, 225727 m/sec, 6099002 t fired, .
Time elapsed: 37 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 29 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-08
lola: result : false
lola: markings : 1904505
lola: fired transitions : 10789081
lola: time used : 9.000000
lola: memory pages used : 8
lola: LAUNCH task # 26 (type EXCL) for 25 LamportFastMutEx-PT-4-CTLFireability-07
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-07
lola: result : false
lola: markings : 1844
lola: fired transitions : 4421
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 LamportFastMutEx-PT-4-CTLFireability-06
lola: time limit : 444 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 1/444 2/32 LamportFastMutEx-PT-4-CTLFireability-06 279200 m, 55840 m/sec, 1189258 t fired, .
Time elapsed: 42 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 1 0 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 6/444 6/32 LamportFastMutEx-PT-4-CTLFireability-06 1299499 m, 204059 m/sec, 7294196 t fired, .
Time elapsed: 47 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 23 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-06
lola: result : false
lola: markings : 1914784
lola: fired transitions : 11217297
lola: time used : 9.000000
lola: memory pages used : 8
lola: LAUNCH task # 20 (type EXCL) for 19 LamportFastMutEx-PT-4-CTLFireability-05
lola: time limit : 507 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-05
lola: result : false
lola: markings : 469
lola: fired transitions : 1036
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 6 LamportFastMutEx-PT-4-CTLFireability-02
lola: time limit : 591 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 0 1 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 2/591 2/32 LamportFastMutEx-PT-4-CTLFireability-02 267661 m, 53532 m/sec, 1341193 t fired, .
Time elapsed: 52 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 0 1 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 7/591 5/32 LamportFastMutEx-PT-4-CTLFireability-02 1046396 m, 155747 m/sec, 6630380 t fired, .
Time elapsed: 57 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: DISJ 0 0 1 0 3 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 12/591 8/32 LamportFastMutEx-PT-4-CTLFireability-02 1829733 m, 156667 m/sec, 11740162 t fired, .
Time elapsed: 62 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 9 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-02
lola: result : false
lola: markings : 1914776
lola: fired transitions : 12869265
lola: time used : 13.000000
lola: memory pages used : 8
lola: LAUNCH task # 4 (type EXCL) for 3 LamportFastMutEx-PT-4-CTLFireability-01
lola: time limit : 707 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 4/707 3/32 LamportFastMutEx-PT-4-CTLFireability-01 581851 m, 116370 m/sec, 3924370 t fired, .
Time elapsed: 67 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 9/707 6/32 LamportFastMutEx-PT-4-CTLFireability-01 1234083 m, 130446 m/sec, 9358296 t fired, .
Time elapsed: 72 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 14/707 8/32 LamportFastMutEx-PT-4-CTLFireability-01 1859500 m, 125083 m/sec, 14472597 t fired, .
Time elapsed: 77 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 4 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-01
lola: result : false
lola: markings : 1914784
lola: fired transitions : 15411182
lola: time used : 15.000000
lola: memory pages used : 8
lola: LAUNCH task # 32 (type EXCL) for 31 LamportFastMutEx-PT-4-CTLFireability-09
lola: time limit : 880 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 4/880 4/32 LamportFastMutEx-PT-4-CTLFireability-09 936943 m, 187388 m/sec, 5011133 t fired, .
Time elapsed: 82 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 32 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-09
lola: result : true
lola: markings : 1730712
lola: fired transitions : 10033631
lola: time used : 8.000000
lola: memory pages used : 8
lola: LAUNCH task # 51 (type EXCL) for 46 LamportFastMutEx-PT-4-CTLFireability-14
lola: time limit : 1171 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-09: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 0 1 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 1/1171 2/32 LamportFastMutEx-PT-4-CTLFireability-14 284382 m, 56876 m/sec, 1170234 t fired, .
Time elapsed: 87 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-09: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: DISJ 0 0 1 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 6/1171 7/32 LamportFastMutEx-PT-4-CTLFireability-14 1490081 m, 241139 m/sec, 7978561 t fired, .
Time elapsed: 92 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 51 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-14
lola: result : true
lola: markings : 1720831
lola: fired transitions : 9713861
lola: time used : 7.000000
lola: memory pages used : 8
lola: LAUNCH task # 1 (type EXCL) for 0 LamportFastMutEx-PT-4-CTLFireability-00
lola: time limit : 1753 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-09: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: DISJ true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 4/1753 3/32 LamportFastMutEx-PT-4-CTLFireability-00 691095 m, 138219 m/sec, 3677359 t fired, .
Time elapsed: 97 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-09: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: DISJ true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 9/1753 7/32 LamportFastMutEx-PT-4-CTLFireability-00 1615330 m, 184847 m/sec, 9455927 t fired, .
Time elapsed: 102 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 1 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-00
lola: result : true
lola: markings : 1867041
lola: fired transitions : 11450762
lola: time used : 11.000000
lola: memory pages used : 8
lola: LAUNCH task # 14 (type EXCL) for 13 LamportFastMutEx-PT-4-CTLFireability-03
lola: time limit : 3496 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-09: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: DISJ true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 3/3496 3/32 LamportFastMutEx-PT-4-CTLFireability-03 548937 m, 109787 m/sec, 2899387 t fired, .
Time elapsed: 107 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-09: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: DISJ true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 8/3496 6/32 LamportFastMutEx-PT-4-CTLFireability-03 1405376 m, 171287 m/sec, 8359096 t fired, .
Time elapsed: 112 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 14 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-03
lola: result : false
lola: markings : 1914784
lola: fired transitions : 11918535
lola: time used : 12.000000
lola: memory pages used : 8
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-08: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-09: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: DISJ true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
Time elapsed: 116 secs. Pages in use: 8
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is LamportFastMutEx-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r118-tall-162075403300658"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-4.tgz
mv LamportFastMutEx-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;