About the Execution of LoLA for LamportFastMutEx-COL-8
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
1109.907 | 335343.00 | 336904.00 | 557.80 | FTTTTFTFT??FFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r118-tall-162075403300634.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is LamportFastMutEx-COL-8, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r118-tall-162075403300634
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 412K
-rw-r--r-- 1 mcc users 19K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 144K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 26 07:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 26 07:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 26 07:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 26 07:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Mar 27 06:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 06:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Mar 25 07:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 25 07:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_pt
-rw-r--r-- 1 mcc users 2 May 5 16:51 instance
-rw-r--r-- 1 mcc users 5 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 44K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-00
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-01
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-02
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-03
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-04
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-05
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-06
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-07
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-08
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-09
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-10
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-11
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-12
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-13
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-14
FORMULA_NAME LamportFastMutEx-COL-8-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620825474918
starting LoLA
BK_INPUT LamportFastMutEx-COL-8
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA LamportFastMutEx-COL-8-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-8-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620825810261
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: TR BINDINGS
lola: TR BINDINGS DONE
lola: Places: 315, Transitions: 666
lola: @ trans T-setbi_24
lola: @ trans T-yne0_4
lola: @ trans T-fordo_12
lola: @ trans T-xeqi_10
lola: @ trans T-sety_9
lola: @ trans T-setbi_2
lola: @ trans T-awaity
lola: @ trans T-setbi_11
lola: @ trans T-ynei_15
lola: @ trans T-forod_13
lola: @ trans T-setbi_5
lola: @ trans T-xnei_10
lola: @ trans T-await_13
lola: @ trans T-yeq0_4
lola: @ trans T-yeqi_15
lola: @ trans T-sety0_23
lola: @ trans T-setx_3
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lola: result : true
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lola: CANCELED task # 4 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-01 (obsolete)
lola: FINISHED task # 17 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-05
lola: result : false
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lola: result : true
lola: FINISHED task # 23 (type SKEL/CNST) for LamportFastMutEx-COL-8-CTLFireability-07
lola: result : false
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lola: result : true
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lola: result : false
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lola: result : true
lola: CANCELED task # 16 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-05 (obsolete)
lola: FINISHED task # 16 (type CNST) for LamportFastMutEx-COL-8-CTLFireability-05
lola: result : false
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lola: result : true
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lola: rewrite Frontend/Parser/formula_rewrite.k:734
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 5/719 2/32 LamportFastMutEx-COL-8-CTLFireability-09 225101 m, 45020 m/sec, 1728950 t fired, .
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LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
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LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 10/719 3/32 LamportFastMutEx-COL-8-CTLFireability-09 461090 m, 47197 m/sec, 3596535 t fired, .
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LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
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LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EFEG EXCL 15/719 4/32 LamportFastMutEx-COL-8-CTLFireability-09 683181 m, 44418 m/sec, 5275631 t fired, .
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LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
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52 EFEG EXCL 20/719 5/32 LamportFastMutEx-COL-8-CTLFireability-09 877306 m, 38825 m/sec, 6880632 t fired, .
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LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
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52 EFEG EXCL 25/719 6/32 LamportFastMutEx-COL-8-CTLFireability-09 1050600 m, 34658 m/sec, 8328778 t fired, .
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LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 1 0 2 0 0 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
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52 EFEG EXCL 30/719 7/32 LamportFastMutEx-COL-8-CTLFireability-09 1216400 m, 33160 m/sec, 9811070 t fired, .
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LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
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LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 125/849 30/32 LamportFastMutEx-COL-8-CTLFireability-10 6346297 m, 49513 m/sec, 17166790 t fired, .
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LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 130/849 32/32 LamportFastMutEx-COL-8-CTLFireability-10 6599498 m, 50640 m/sec, 17891881 t fired, .
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lola: CANCELED task # 53 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-8-CTLFireability-02: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-8-CTLFireability-09: CONJ 0 0 0 0 2 0 1 0
LamportFastMutEx-COL-8-CTLFireability-10: AXAG 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-8-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 25 (type EXCL) for 24 LamportFastMutEx-COL-8-CTLFireability-08
lola: time limit : 1088 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 49 LamportFastMutEx-COL-8-CTLFireability-15
lola: time limit : 1632 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-15
lola: result : false
lola: markings : 256
lola: fired transitions : 1024
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 LamportFastMutEx-COL-8-CTLFireability-02
lola: time limit : 3264 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for LamportFastMutEx-COL-8-CTLFireability-02
lola: result : true
lola: markings : 15
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-8-CTLFireability-00: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-01: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-02: EG true state space / EG
LamportFastMutEx-COL-8-CTLFireability-03: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-04: INITIAL true preprocessing
LamportFastMutEx-COL-8-CTLFireability-05: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-06: INITIAL true skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-07: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-COL-8-CTLFireability-09: CONJ unknown CONJ
LamportFastMutEx-COL-8-CTLFireability-10: AXAG unknown AGGR
LamportFastMutEx-COL-8-CTLFireability-11: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-12: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-COL-8-CTLFireability-14: INITIAL false skeleton: preprocessing
LamportFastMutEx-COL-8-CTLFireability-15: F true state space / EG
Time elapsed: 336 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-8"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is LamportFastMutEx-COL-8, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r118-tall-162075403300634"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-8.tgz
mv LamportFastMutEx-COL-8 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;