About the Execution of LoLA for GlobalResAllocation-PT-05
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4749.892 | 3600000.00 | 5305389.00 | 8144.80 | FFFTFF?TTTFTFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r118-tall-162075402500070.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is GlobalResAllocation-PT-05, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r118-tall-162075402500070
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 408M
-rw-r--r-- 1 mcc users 91K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 399K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 61M May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 253M May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 17K Mar 28 16:13 LTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Mar 28 16:13 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7M Mar 28 16:13 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.7M Mar 28 16:13 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.2K Mar 23 11:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 33K Mar 23 11:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.3M Mar 22 20:59 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 10M Mar 22 20:59 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 5.3K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 11K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 70M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-00
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-01
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-02
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-03
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-04
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-05
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-06
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-07
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-08
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-09
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-10
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-11
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-12
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-13
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-14
FORMULA_NAME GlobalResAllocation-PT-05-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1620774290161
starting LoLA
BK_INPUT GlobalResAllocation-PT-05
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-PT-05-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 4.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: Created skeleton in 4.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: Created skeleton in 4.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF 0 0 0 0 1 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
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GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 16/239 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 23091 t fired, 1 attempts, .
63 EF STEQ 16/259 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 16/259 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 24311 m, 2381 m/sec, 40700 t fired, .
67 EF EXCL 15/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 296 m, 34 m/sec, 606 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 21/235 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 35195 t fired, 1 attempts, .
63 EF STEQ 21/255 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 21/255 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 37186 m, 2575 m/sec, 63575 t fired, .
67 EF EXCL 20/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 473 m, 35 m/sec, 998 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 26/230 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 47101 t fired, 1 attempts, .
63 EF STEQ 26/250 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 26/250 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 50190 m, 2600 m/sec, 87558 t fired, .
67 EF EXCL 25/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 646 m, 34 m/sec, 1387 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 31/225 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 59172 t fired, 1 attempts, .
63 EF STEQ 31/245 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 31/245 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 63239 m, 2609 m/sec, 112263 t fired, .
67 EF EXCL 30/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 815 m, 33 m/sec, 1811 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 36/220 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 71217 t fired, 1 attempts, .
63 EF STEQ 36/240 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 36/240 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 76413 m, 2634 m/sec, 137263 t fired, .
67 EF EXCL 35/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 993 m, 35 m/sec, 2170 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 41/215 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 83446 t fired, 1 attempts, .
63 EF STEQ 41/235 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 41/235 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 89691 m, 2655 m/sec, 163082 t fired, .
67 EF EXCL 40/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 1174 m, 36 m/sec, 2506 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 46/210 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 95568 t fired, 1 attempts, .
63 EF STEQ 46/230 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 46/230 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 102963 m, 2654 m/sec, 189211 t fired, .
67 EF EXCL 45/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 1351 m, 35 m/sec, 2892 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 51/205 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 107644 t fired, 1 attempts, .
63 EF STEQ 51/225 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 51/225 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 116205 m, 2648 m/sec, 215123 t fired, .
67 EF EXCL 50/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 1533 m, 36 m/sec, 3310 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 56/200 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 119772 t fired, 1 attempts, .
63 EF STEQ 56/220 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 56/220 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 129396 m, 2638 m/sec, 241654 t fired, .
67 EF EXCL 55/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 1699 m, 33 m/sec, 3692 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 61/195 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 131830 t fired, 1 attempts, .
63 EF STEQ 61/215 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 61/215 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 142654 m, 2651 m/sec, 269479 t fired, .
67 EF EXCL 60/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 1865 m, 33 m/sec, 4043 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 66/190 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 144003 t fired, 1 attempts, .
63 EF STEQ 66/210 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 66/210 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 156026 m, 2674 m/sec, 297479 t fired, .
67 EF EXCL 65/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 2046 m, 36 m/sec, 4379 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
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GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 71/185 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 156066 t fired, 1 attempts, .
63 EF STEQ 71/205 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 71/205 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 169335 m, 2661 m/sec, 325356 t fired, .
67 EF EXCL 70/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 2217 m, 34 m/sec, 4698 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 76/180 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 168348 t fired, 1 attempts, .
63 EF STEQ 76/200 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 76/200 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 182844 m, 2701 m/sec, 353018 t fired, .
67 EF EXCL 75/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 2399 m, 36 m/sec, 5027 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 81/175 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 180470 t fired, 1 attempts, .
63 EF STEQ 81/195 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 81/195 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 196299 m, 2691 m/sec, 381232 t fired, .
67 EF EXCL 80/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 2579 m, 36 m/sec, 5375 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 86/170 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 192644 t fired, 1 attempts, .
63 EF STEQ 86/190 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 86/190 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 209778 m, 2695 m/sec, 410139 t fired, .
67 EF EXCL 85/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 2753 m, 34 m/sec, 5709 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 91/165 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 204954 t fired, 1 attempts, .
63 EF STEQ 91/185 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 91/185 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 223297 m, 2703 m/sec, 439401 t fired, .
67 EF EXCL 90/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 2935 m, 36 m/sec, 6042 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 96/160 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 217275 t fired, 1 attempts, .
63 EF STEQ 96/180 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 96/180 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 236700 m, 2680 m/sec, 468876 t fired, .
67 EF EXCL 95/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 3116 m, 36 m/sec, 6392 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 101/155 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 229533 t fired, 1 attempts, .
63 EF STEQ 101/175 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 101/175 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 250086 m, 2677 m/sec, 497086 t fired, .
67 EF EXCL 100/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 3296 m, 36 m/sec, 6698 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 106/150 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 241884 t fired, 1 attempts, .
63 EF STEQ 106/170 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 106/170 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 263580 m, 2698 m/sec, 526977 t fired, .
67 EF EXCL 105/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 3476 m, 36 m/sec, 7068 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 111/145 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 254231 t fired, 1 attempts, .
63 EF STEQ 111/165 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 111/165 2/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 277111 m, 2706 m/sec, 557185 t fired, .
67 EF EXCL 110/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 3656 m, 36 m/sec, 7537 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 116/140 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 266531 t fired, 1 attempts, .
63 EF STEQ 116/160 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 116/160 2/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 290660 m, 2709 m/sec, 587666 t fired, .
67 EF EXCL 115/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 3828 m, 34 m/sec, 7962 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 121/135 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 278955 t fired, 1 attempts, .
63 EF STEQ 121/155 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 121/155 2/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 304195 m, 2707 m/sec, 617743 t fired, .
67 EF EXCL 120/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 4005 m, 35 m/sec, 8293 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 4 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF FNDP 126/130 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 291290 t fired, 1 attempts, .
63 EF STEQ 126/150 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 126/150 2/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 317781 m, 2717 m/sec, 648836 t fired, .
67 EF EXCL 125/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 4199 m, 38 m/sec, 8648 t fired, .
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lola: CANCELED task # 62 (type FNDP) for GlobalResAllocation-PT-05-ReachabilityCardinality-06 (local timeout)
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 3 0 1 1 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 EF STEQ 131/145 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 131/145 2/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 331444 m, 2732 m/sec, 679779 t fired, .
67 EF EXCL 130/352 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 4372 m, 34 m/sec, 9090 t fired, .
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lola: FINISHED task # 62 (type FNDP) for GlobalResAllocation-PT-05-ReachabilityCardinality-06
lola: result : unknown
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lola: FINISHED task # 130 (type FNDP) for GlobalResAllocation-PT-05-ReachabilityCardinality-01
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 3 0 2 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 EF STEQ 136/189 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 136/162 2/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 345071 m, 2725 m/sec, 710584 t fired, .
67 EF EXCL 135/391 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 4558 m, 37 m/sec, 9423 t fired, .
82 EF FNDP 5/283 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 14176 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 3 0 2 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 EF STEQ 141/184 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 141/157 2/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 358747 m, 2735 m/sec, 741923 t fired, .
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82 EF FNDP 10/278 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 31323 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 3 0 2 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 EF STEQ 146/179 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
66 EF SRCH 146/152 2/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 372432 m, 2737 m/sec, 773605 t fired, .
67 EF EXCL 145/391 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 4903 m, 32 m/sec, 10133 t fired, .
82 EF FNDP 15/273 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 45794 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 2 0 2 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 EF STEQ 151/174 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
67 EF EXCL 150/391 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 5061 m, 31 m/sec, 10418 t fired, .
82 EF FNDP 20/268 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 61007 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 2 0 2 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 EF STEQ 156/169 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
67 EF EXCL 155/391 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 5231 m, 34 m/sec, 10729 t fired, .
82 EF FNDP 25/288 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 76494 t fired, 1 attempts, .
94 EF FNDP 5/281 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-15 14109 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 2 0 2 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 EF STEQ 161/164 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 sara is running.
67 EF EXCL 160/391 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 5411 m, 36 m/sec, 11029 t fired, .
82 EF FNDP 30/283 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 92820 t fired, 1 attempts, .
94 EF FNDP 10/276 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-15 28296 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 2 2 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 165/391 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 5580 m, 33 m/sec, 11326 t fired, .
82 EF FNDP 35/278 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 108086 t fired, 1 attempts, .
94 EF FNDP 15/271 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-15 42364 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
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GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 170/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 5748 m, 33 m/sec, 11620 t fired, .
82 EF FNDP 40/389 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 124204 t fired, 1 attempts, .
85 EF FNDP 5/420 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 2901 t fired, 1 attempts, .
94 EF FNDP 20/360 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-15 56376 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 175/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 5926 m, 35 m/sec, 11934 t fired, .
82 EF FNDP 45/384 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 139503 t fired, 1 attempts, .
85 EF FNDP 10/415 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 5821 t fired, 1 attempts, .
94 EF FNDP 25/355 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-15 70566 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
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67 EF EXCL 180/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 6086 m, 32 m/sec, 12319 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
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67 EF EXCL 185/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 6237 m, 30 m/sec, 12678 t fired, .
82 EF FNDP 55/374 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 172183 t fired, 1 attempts, .
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67 EF EXCL 190/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 6402 m, 33 m/sec, 13035 t fired, .
82 EF FNDP 60/369 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 187810 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
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67 EF EXCL 195/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 6573 m, 34 m/sec, 13331 t fired, .
82 EF FNDP 65/364 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 203908 t fired, 1 attempts, .
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67 EF EXCL 200/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 6741 m, 33 m/sec, 13685 t fired, .
82 EF FNDP 70/359 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 219910 t fired, 1 attempts, .
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67 EF EXCL 205/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 6909 m, 33 m/sec, 14103 t fired, .
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67 EF EXCL 210/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 7087 m, 35 m/sec, 14440 t fired, .
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67 EF EXCL 215/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 7262 m, 35 m/sec, 14818 t fired, .
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67 EF EXCL 220/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 7434 m, 34 m/sec, 15122 t fired, .
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67 EF EXCL 225/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 7601 m, 33 m/sec, 15464 t fired, .
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67 EF EXCL 230/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 7768 m, 33 m/sec, 15785 t fired, .
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67 EF EXCL 235/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 7933 m, 33 m/sec, 16114 t fired, .
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67 EF EXCL 240/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 8101 m, 33 m/sec, 16487 t fired, .
82 EF FNDP 110/319 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 348936 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
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67 EF EXCL 245/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 8272 m, 34 m/sec, 16811 t fired, .
82 EF FNDP 115/314 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 364960 t fired, 1 attempts, .
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67 EF EXCL 250/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 8435 m, 32 m/sec, 17120 t fired, .
82 EF FNDP 120/309 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 380256 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
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67 EF EXCL 255/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 8601 m, 33 m/sec, 17467 t fired, .
82 EF FNDP 125/304 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 396544 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
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67 EF EXCL 260/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 8765 m, 32 m/sec, 17783 t fired, .
82 EF FNDP 130/299 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 413421 t fired, 1 attempts, .
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67 EF EXCL 265/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 8930 m, 33 m/sec, 18172 t fired, .
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67 EF EXCL 270/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 9102 m, 34 m/sec, 18519 t fired, .
82 EF FNDP 140/289 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 444591 t fired, 1 attempts, .
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67 EF EXCL 275/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 9262 m, 32 m/sec, 18839 t fired, .
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67 EF EXCL 280/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 9427 m, 33 m/sec, 19189 t fired, .
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67 EF EXCL 285/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 9590 m, 32 m/sec, 19604 t fired, .
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67 EF EXCL 290/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 9767 m, 35 m/sec, 19982 t fired, .
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67 EF EXCL 295/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 9923 m, 31 m/sec, 20331 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
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GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 300/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 10092 m, 33 m/sec, 20724 t fired, .
82 EF FNDP 170/259 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 541486 t fired, 1 attempts, .
85 EF FNDP 135/290 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 116679 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
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GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
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67 EF EXCL 305/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 10255 m, 32 m/sec, 21080 t fired, .
82 EF FNDP 175/254 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 557104 t fired, 1 attempts, .
85 EF FNDP 140/285 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 136013 t fired, 1 attempts, .
94 EF FNDP 155/225 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-15 434183 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
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GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
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67 EF EXCL 310/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 10420 m, 33 m/sec, 21424 t fired, .
82 EF FNDP 180/249 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 573242 t fired, 1 attempts, .
85 EF FNDP 145/280 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 154785 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 315/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 10587 m, 33 m/sec, 21753 t fired, .
82 EF FNDP 185/244 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 589171 t fired, 1 attempts, .
85 EF FNDP 150/275 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 172032 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
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67 EF EXCL 320/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 10755 m, 33 m/sec, 22106 t fired, .
82 EF FNDP 190/239 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 605685 t fired, 1 attempts, .
85 EF FNDP 155/270 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 187155 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
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GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
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67 EF EXCL 325/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 10925 m, 34 m/sec, 22502 t fired, .
82 EF FNDP 195/234 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 622463 t fired, 1 attempts, .
85 EF FNDP 160/265 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 202408 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 330/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 11095 m, 34 m/sec, 22867 t fired, .
82 EF FNDP 200/229 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 637907 t fired, 1 attempts, .
85 EF FNDP 165/260 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 217900 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
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GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 1 0 1 0 0 0
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67 EF EXCL 335/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 11269 m, 34 m/sec, 23288 t fired, .
82 EF FNDP 205/224 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 654125 t fired, 1 attempts, .
85 EF FNDP 170/255 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 233660 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
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GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
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67 EF EXCL 340/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 11442 m, 34 m/sec, 23709 t fired, .
82 EF FNDP 210/219 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 669693 t fired, 1 attempts, .
85 EF FNDP 175/250 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 249419 t fired, 1 attempts, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
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GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
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67 EF EXCL 345/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 11609 m, 33 m/sec, 24088 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
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GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
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67 EF EXCL 350/503 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 11775 m, 33 m/sec, 24469 t fired, .
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sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-105.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 0 0 2 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF 0 3 2 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 355/587 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 11931 m, 31 m/sec, 24873 t fired, .
85 EF FNDP 190/375 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 291197 t fired, 1 attempts, .
97 EF FNDP 5/529 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-14 13848 t fired, 1 attempts, .
105 EF STEQ 5/453 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-14 sara is running.
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lola: FINISHED task # 97 (type FNDP) for GlobalResAllocation-PT-05-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 14368
lola: tried executions : 2
lola: time used : 5.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-119.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG 0 3 2 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 4 0 0 2 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 360/705 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 12094 m, 32 m/sec, 25286 t fired, .
85 EF FNDP 195/482 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 302597 t fired, 1 attempts, .
118 EF FNDP 5/634 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-11 12458 t fired, 1 attempts, .
119 EF STEQ 5/634 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-11 sara is running.
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 118 (type FNDP) for GlobalResAllocation-PT-05-ReachabilityCardinality-11
lola: result : unknown
lola: fired transitions : 13382
lola: tried executions : 2
lola: time used : 6.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-92.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF 0 2 2 0 2 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 4 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 365/881 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 12272 m, 35 m/sec, 25641 t fired, .
85 EF FNDP 200/924 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 314042 t fired, 1 attempts, .
92 EF STEQ 4/791 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 sara is running.
98 EF SRCH 4/791 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-13 13168 m, 2633 m/sec, 17843 t fired, .
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lola: FINISHED task # 92 (type EQUN) for GlobalResAllocation-PT-05-ReachabilityCardinality-13
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lola: LAUNCH task # 100 (type EQUN) for 45 GlobalResAllocation-PT-05-ReachabilityCardinality-15
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lola: LAUNCH task # 102 (type SRCH) for 45 GlobalResAllocation-PT-05-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-100.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 4 1 0 1 0 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF 0 2 2 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 370/1175 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 12449 m, 35 m/sec, 26005 t fired, .
85 EF FNDP 205/1479 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 325564 t fired, 1 attempts, .
100 EF STEQ 4/1053 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-15 sara is running.
102 EF SRCH 4/1053 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-15 12523 m, 2504 m/sec, 18253 t fired, .
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lola: LAUNCH task # 112 (type SRCH) for 36 GlobalResAllocation-PT-05-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-108.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 1 1 0 3 1 0 0
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF 0 2 3 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 375/1763 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 12626 m, 35 m/sec, 26405 t fired, .
85 EF FNDP 210/3155 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 337197 t fired, 1 attempts, .
108 EF STEQ 4/1577 0/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 sara is running.
112 EF SRCH 4/1577 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-12 27152 m, 5430 m/sec, 187211 t fired, .
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sara: place or transition ordering is non-deterministic
lola: FINISHED task # 108 (type EQUN) for GlobalResAllocation-PT-05-ReachabilityCardinality-12
lola: result : false
lola: CANCELED task # 85 (type FNDP) for GlobalResAllocation-PT-05-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 112 (type SRCH) for GlobalResAllocation-PT-05-ReachabilityCardinality-12 (obsolete)
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lola: time limit : 32000000 sec
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type EXCL) for 18 GlobalResAllocation-PT-05-ReachabilityCardinality-06
lola: time limit : 3150 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type FNDP) for GlobalResAllocation-PT-05-ReachabilityCardinality-12
lola: result : unknown
lola: fired transitions : 340370
lola: tried executions : 2
lola: time used : 212.000000
lola: memory pages used : 0
lola: FINISHED task # 73 (type SRCH) for GlobalResAllocation-PT-05-ReachabilityCardinality-06
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 2 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF EXCL 4/3150 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 8659 m, -72754 m/sec, 13848 t fired, .
67 EF EXCL 380/1763 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 12814 m, 37 m/sec, 26804 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF EXCL 9/3150 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 21302 m, 2528 m/sec, 35458 t fired, .
67 EF EXCL 385/1763 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 13008 m, 38 m/sec, 27256 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF EXCL 14/3150 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 34098 m, 2559 m/sec, 57825 t fired, .
67 EF EXCL 390/1763 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 13197 m, 37 m/sec, 27599 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 2 0 4 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF EXCL 19/3150 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 47099 m, 2600 m/sec, 81827 t fired, .
67 EF EXCL 395/1763 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 13358 m, 32 m/sec, 28013 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
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66 EF EXCL 24/3150 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 60067 m, 2593 m/sec, 106326 t fired, .
67 EF EXCL 400/1763 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 13548 m, 38 m/sec, 28431 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
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GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
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66 EF EXCL 29/3150 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 73123 m, 2611 m/sec, 130969 t fired, .
67 EF EXCL 405/1763 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 13733 m, 37 m/sec, 28877 t fired, .
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66 EF EXCL 34/3150 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 86258 m, 2627 m/sec, 156321 t fired, .
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66 EF EXCL 39/3150 1/5 GlobalResAllocation-PT-05-ReachabilityCardinality-06 99495 m, 2647 m/sec, 182247 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 1 0 4 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 2370/3526 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 87192 m, 37 m/sec, 193727 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 1 0 4 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 EF EXCL 2375/3526 1/32 GlobalResAllocation-PT-05-ReachabilityCardinality-06 87387 m, 39 m/sec, 194196 t fired, .
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GlobalResAllocation-PT-05-ReachabilityCardinality-00: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-01: AG false findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-02: INITIAL false preprocessing
GlobalResAllocation-PT-05-ReachabilityCardinality-03: EF true tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-04: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-05: AG false tandem / insertion
GlobalResAllocation-PT-05-ReachabilityCardinality-07: EF true tandem / relaxed
GlobalResAllocation-PT-05-ReachabilityCardinality-08: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-09: EF true findpath
GlobalResAllocation-PT-05-ReachabilityCardinality-10: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-11: AG true state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-12: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-13: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-14: EF false state equation
GlobalResAllocation-PT-05-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-PT-05-ReachabilityCardinality-06: AG 0 0 1 0 4 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GlobalResAllocation-PT-05"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is GlobalResAllocation-PT-05, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r118-tall-162075402500070"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/GlobalResAllocation-PT-05.tgz
mv GlobalResAllocation-PT-05 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;