About the Execution of LoLA for GPPP-PT-C0010N0000000010
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
1639.512 | 468310.00 | 468292.00 | 1082.80 | FF??TFF?FTTF?TTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r099-smll-162075328900210.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2021-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is GPPP-PT-C0010N0000000010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r099-smll-162075328900210
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 384K
-rw-r--r-- 1 mcc users 8.6K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 19K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 102K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Mar 28 16:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 16:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 28 16:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 28 16:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Mar 23 11:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 23 11:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.2K Mar 22 19:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 21K Mar 22 19:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Mar 22 09:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 09:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 17 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 1 May 5 16:51 large_marking
-rw-r--r-- 1 mcc users 21K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-00
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-01
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-02
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-03
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-04
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-05
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-06
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-07
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-08
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-09
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-10
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-11
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-12
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-13
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-14
FORMULA_NAME GPPP-PT-C0010N0000000010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620831343877
starting LoLA
BK_INPUT GPPP-PT-C0010N0000000010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000010-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620831812187
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 14 (type EXCL) for 9 GPPP-PT-C0010N0000000010-CTLFireability-03
lola: time limit : 108 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 14 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-03
lola: result : false
lola: markings : 343
lola: fired transitions : 1142
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 GPPP-PT-C0010N0000000010-CTLFireability-01
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 4 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-01
lola: result : false
lola: markings : 552
lola: fired transitions : 1301
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 47 (type EXCL) for 46 GPPP-PT-C0010N0000000010-CTLFireability-10
lola: time limit : 134 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 64 (type FNDP) for 23 GPPP-PT-C0010N0000000010-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 23 GPPP-PT-C0010N0000000010-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 67 (type SRCH) for 23 GPPP-PT-C0010N0000000010-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 47 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-10
lola: result : true
lola: markings : 309
lola: fired transitions : 687
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 62 (type EXCL) for 61 GPPP-PT-C0010N0000000010-CTLFireability-15
lola: time limit : 146 sec
lola: memory limit: 32 pages
lola: FINISHED task # 67 (type SRCH) for GPPP-PT-C0010N0000000010-CTLFireability-05
lola: result : unknown
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 64 (type FNDP) for GPPP-PT-C0010N0000000010-CTLFireability-05
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 62 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-15
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 65 (type EQUN) for GPPP-PT-C0010N0000000010-CTLFireability-05 (obsolete)
lola: LAUNCH task # 59 (type EXCL) for 58 GPPP-PT-C0010N0000000010-CTLFireability-14
lola: time limit : 197 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 65 (type EQUN) for GPPP-PT-C0010N0000000010-CTLFireability-05
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 59 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-14
lola: result : true
lola: markings : 389
lola: fired transitions : 902
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 49 GPPP-PT-C0010N0000000010-CTLFireability-11
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 50 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-11
lola: result : false
lola: markings : 614
lola: fired transitions : 1373
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 GPPP-PT-C0010N0000000010-CTLFireability-08
lola: time limit : 305 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 41 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-08
lola: result : false
lola: markings : 2289
lola: fired transitions : 9808
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 68 (type EXCL) for 43 GPPP-PT-C0010N0000000010-CTLFireability-09
lola: time limit : 336 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-09
lola: result : false
lola: markings : 41
lola: fired transitions : 40
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 GPPP-PT-C0010N0000000010-CTLFireability-06
lola: time limit : 373 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-06
lola: result : false
lola: markings : 1312
lola: fired transitions : 3736
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 GPPP-PT-C0010N0000000010-CTLFireability-02
lola: time limit : 420 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/420 4/32 GPPP-PT-C0010N0000000010-CTLFireability-02 773467 m, 154693 m/sec, 6516083 t fired, .
Time elapsed: 243 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/420 7/32 GPPP-PT-C0010N0000000010-CTLFireability-02 1540270 m, 153360 m/sec, 13230605 t fired, .
Time elapsed: 248 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/420 10/32 GPPP-PT-C0010N0000000010-CTLFireability-02 2291310 m, 150208 m/sec, 19755004 t fired, .
Time elapsed: 253 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/420 13/32 GPPP-PT-C0010N0000000010-CTLFireability-02 3016687 m, 145075 m/sec, 26131290 t fired, .
Time elapsed: 258 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/420 16/32 GPPP-PT-C0010N0000000010-CTLFireability-02 3760970 m, 148856 m/sec, 32602061 t fired, .
Time elapsed: 263 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/420 19/32 GPPP-PT-C0010N0000000010-CTLFireability-02 4477551 m, 143316 m/sec, 38869503 t fired, .
Time elapsed: 268 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/420 22/32 GPPP-PT-C0010N0000000010-CTLFireability-02 5205950 m, 145679 m/sec, 45381406 t fired, .
Time elapsed: 273 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/420 25/32 GPPP-PT-C0010N0000000010-CTLFireability-02 5882674 m, 135344 m/sec, 51742662 t fired, .
Time elapsed: 278 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/420 28/32 GPPP-PT-C0010N0000000010-CTLFireability-02 6548660 m, 133197 m/sec, 57943796 t fired, .
Time elapsed: 283 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/420 31/32 GPPP-PT-C0010N0000000010-CTLFireability-02 7203964 m, 131060 m/sec, 64094261 t fired, .
Time elapsed: 288 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 1 0 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 293 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 GPPP-PT-C0010N0000000010-CTLFireability-00
lola: time limit : 472 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-00
lola: result : false
lola: markings : 129
lola: fired transitions : 140
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 9 GPPP-PT-C0010N0000000010-CTLFireability-03
lola: time limit : 551 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 5/551 4/32 GPPP-PT-C0010N0000000010-CTLFireability-03 836866 m, 167373 m/sec, 6522746 t fired, .
Time elapsed: 298 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 10/551 7/32 GPPP-PT-C0010N0000000010-CTLFireability-03 1612897 m, 155206 m/sec, 12839963 t fired, .
Time elapsed: 303 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 15/551 10/32 GPPP-PT-C0010N0000000010-CTLFireability-03 2374387 m, 152298 m/sec, 19024726 t fired, .
Time elapsed: 308 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 20/551 14/32 GPPP-PT-C0010N0000000010-CTLFireability-03 3125172 m, 150157 m/sec, 25126441 t fired, .
Time elapsed: 313 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 25/551 17/32 GPPP-PT-C0010N0000000010-CTLFireability-03 3872151 m, 149395 m/sec, 31212756 t fired, .
Time elapsed: 318 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 30/551 20/32 GPPP-PT-C0010N0000000010-CTLFireability-03 4608296 m, 147229 m/sec, 37181873 t fired, .
Time elapsed: 323 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 35/551 23/32 GPPP-PT-C0010N0000000010-CTLFireability-03 5327643 m, 143869 m/sec, 43212240 t fired, .
Time elapsed: 328 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 40/551 26/32 GPPP-PT-C0010N0000000010-CTLFireability-03 6014909 m, 137453 m/sec, 49208438 t fired, .
Time elapsed: 333 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 45/551 29/32 GPPP-PT-C0010N0000000010-CTLFireability-03 6680712 m, 133160 m/sec, 55014949 t fired, .
Time elapsed: 338 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 1 0 4 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 50/551 31/32 GPPP-PT-C0010N0000000010-CTLFireability-03 7346615 m, 133180 m/sec, 60753350 t fired, .
Time elapsed: 343 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 18 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 348 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 38 (type EXCL) for 37 GPPP-PT-C0010N0000000010-CTLFireability-07
lola: time limit : 650 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/650 4/32 GPPP-PT-C0010N0000000010-CTLFireability-07 751873 m, 150374 m/sec, 6385048 t fired, .
Time elapsed: 353 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/650 7/32 GPPP-PT-C0010N0000000010-CTLFireability-07 1517044 m, 153034 m/sec, 13207067 t fired, .
Time elapsed: 358 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/650 10/32 GPPP-PT-C0010N0000000010-CTLFireability-07 2263935 m, 149378 m/sec, 19873807 t fired, .
Time elapsed: 363 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/650 13/32 GPPP-PT-C0010N0000000010-CTLFireability-07 2987558 m, 144724 m/sec, 26372193 t fired, .
Time elapsed: 368 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 25/650 16/32 GPPP-PT-C0010N0000000010-CTLFireability-07 3726772 m, 147842 m/sec, 32949529 t fired, .
Time elapsed: 373 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 30/650 19/32 GPPP-PT-C0010N0000000010-CTLFireability-07 4442722 m, 143190 m/sec, 39386055 t fired, .
Time elapsed: 378 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 35/650 22/32 GPPP-PT-C0010N0000000010-CTLFireability-07 5179613 m, 147378 m/sec, 46074223 t fired, .
Time elapsed: 383 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 40/650 25/32 GPPP-PT-C0010N0000000010-CTLFireability-07 5857051 m, 135487 m/sec, 52631381 t fired, .
Time elapsed: 388 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 45/650 28/32 GPPP-PT-C0010N0000000010-CTLFireability-07 6510508 m, 130691 m/sec, 58963699 t fired, .
Time elapsed: 393 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 50/650 31/32 GPPP-PT-C0010N0000000010-CTLFireability-07 7177099 m, 133318 m/sec, 65396931 t fired, .
Time elapsed: 398 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 38 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 403 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 53 (type EXCL) for 52 GPPP-PT-C0010N0000000010-CTLFireability-12
lola: time limit : 799 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 5/799 3/32 GPPP-PT-C0010N0000000010-CTLFireability-12 646995 m, 129399 m/sec, 5753668 t fired, .
Time elapsed: 408 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 10/799 6/32 GPPP-PT-C0010N0000000010-CTLFireability-12 1360497 m, 142700 m/sec, 12101439 t fired, .
Time elapsed: 413 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 15/799 9/32 GPPP-PT-C0010N0000000010-CTLFireability-12 2062863 m, 140473 m/sec, 18343732 t fired, .
Time elapsed: 418 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 20/799 12/32 GPPP-PT-C0010N0000000010-CTLFireability-12 2735368 m, 134501 m/sec, 24356546 t fired, .
Time elapsed: 423 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 25/799 15/32 GPPP-PT-C0010N0000000010-CTLFireability-12 3420694 m, 137065 m/sec, 30417158 t fired, .
Time elapsed: 428 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 30/799 18/32 GPPP-PT-C0010N0000000010-CTLFireability-12 4052713 m, 126403 m/sec, 36046012 t fired, .
Time elapsed: 433 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 35/799 20/32 GPPP-PT-C0010N0000000010-CTLFireability-12 4711353 m, 131728 m/sec, 41931062 t fired, .
Time elapsed: 438 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 40/799 23/32 GPPP-PT-C0010N0000000010-CTLFireability-12 5373341 m, 132397 m/sec, 48179749 t fired, .
Time elapsed: 443 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 45/799 26/32 GPPP-PT-C0010N0000000010-CTLFireability-12 6002780 m, 125887 m/sec, 54242144 t fired, .
Time elapsed: 448 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 50/799 28/32 GPPP-PT-C0010N0000000010-CTLFireability-12 6616427 m, 122729 m/sec, 60151424 t fired, .
Time elapsed: 453 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 55/799 31/32 GPPP-PT-C0010N0000000010-CTLFireability-12 7223165 m, 121347 m/sec, 65992965 t fired, .
Time elapsed: 458 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 53 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ 0 1 0 0 7 0 0 1
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 463 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 23 GPPP-PT-C0010N0000000010-CTLFireability-05
lola: time limit : 1045 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-05
lola: result : false
lola: markings : 45
lola: fired transitions : 227
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 GPPP-PT-C0010N0000000010-CTLFireability-04
lola: time limit : 1568 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ 0 0 0 0 4 0 1 1
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 5/1568 5/32 GPPP-PT-C0010N0000000010-CTLFireability-04 1169020 m, 233804 m/sec, 3619335 t fired, .
Time elapsed: 468 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 21 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-04
lola: result : true
lola: markings : 1311110
lola: fired transitions : 4340667
lola: time used : 6.000000
lola: memory pages used : 6
lola: LAUNCH task # 56 (type EXCL) for 55 GPPP-PT-C0010N0000000010-CTLFireability-13
lola: time limit : 3131 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for GPPP-PT-C0010N0000000010-CTLFireability-13
lola: result : true
lola: markings : 39871
lola: fired transitions : 73899
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0010N0000000010-CTLFireability-00: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-02: CTL unknown AGGR
GPPP-PT-C0010N0000000010-CTLFireability-03: DISJ unknown DISJ
GPPP-PT-C0010N0000000010-CTLFireability-04: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-05: CONJ false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-06: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-07: CTL unknown AGGR
GPPP-PT-C0010N0000000010-CTLFireability-08: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-09: AXAF true state space /EXEG
GPPP-PT-C0010N0000000010-CTLFireability-10: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-12: CTL unknown AGGR
GPPP-PT-C0010N0000000010-CTLFireability-13: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0010N0000000010-CTLFireability-15: CTL true CTL model checker
Time elapsed: 469 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GPPP-PT-C0010N0000000010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is GPPP-PT-C0010N0000000010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r099-smll-162075328900210"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/GPPP-PT-C0010N0000000010.tgz
mv GPPP-PT-C0010N0000000010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;