About the Execution of LoLA for FamilyReunion-PT-L00010M0001C001P001G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3470.216 | 3600000.00 | 852291.00 | 8793.40 | T?FFF???FT?FF??? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r080-tall-162048871600941.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is FamilyReunion-PT-L00010M0001C001P001G001, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r080-tall-162048871600941
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.2M
-rw-r--r-- 1 mcc users 77K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 526K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 157K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 591K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 9.2K Mar 28 16:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 48K Mar 28 16:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 16K Mar 28 16:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 52K Mar 28 16:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.2K Mar 23 10:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 40K Mar 23 10:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Mar 22 18:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 48K Mar 22 18:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.6K Mar 22 09:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.0K Mar 22 09:11 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 24 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 552K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-00
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-01
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-02
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-03
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-04
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-05
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-06
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-07
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-08
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-09
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-10
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-11
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-12
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-13
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-14
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-15
=== Now, execution of the tool begins
BK_START 1620576294949
starting LoLA
BK_INPUT FamilyReunion-PT-L00010M0001C001P001G001
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 56 (type SKEL/SRCH) for 16 FamilyReunion-PT-L00010M0001C001P001G001-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type SKEL/SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-04
lola: result : false
lola: markings : 646
lola: fired transitions : 646
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 31 (type CNST) for 28 FamilyReunion-PT-L00010M0001C001P001G001-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 31 (type CNST) for FamilyReunion-PT-L00010M0001C001P001G001-08
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 60 (type EXCL) for 44 FamilyReunion-PT-L00010M0001C001P001G001-12
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 58 (type FNDP) for 44 FamilyReunion-PT-L00010M0001C001P001G001-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 44 FamilyReunion-PT-L00010M0001C001P001G001-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SRCH) for 44 FamilyReunion-PT-L00010M0001C001P001G001-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 60 (type EXCL) for FamilyReunion-PT-L00010M0001C001P001G001-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 58 (type FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-12 (obsolete)
lola: CANCELED task # 59 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-12 (obsolete)
lola: CANCELED task # 61 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-12 (obsolete)
lola: FINISHED task # 58 (type FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 61 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/LTLFireability-59.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 48 (type EXCL) for 47 FamilyReunion-PT-L00010M0001C001P001G001-13
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-12
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-08: CONJ false preprocessing
FamilyReunion-PT-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-13: LTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-14: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 LTL EXCL 4/239 1/32 FamilyReunion-PT-L00010M0001C001P001G001-13 98586 m, 19717 m/sec, 646121 t fired, .
Time elapsed: 12 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-08: CONJ false preprocessing
FamilyReunion-PT-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-13: LTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-14: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 LTL EXCL 9/239 2/32 FamilyReunion-PT-L00010M0001C001P001G001-13 208496 m, 21982 m/sec, 1456356 t fired, .
Time elapsed: 17 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-08: CONJ false preprocessing
FamilyReunion-PT-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-13: LTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-14: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 LTL EXCL 14/239 3/32 FamilyReunion-PT-L00010M0001C001P001G001-13 335280 m, 25356 m/sec, 2294818 t fired, .
Time elapsed: 22 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-08: CONJ false preprocessing
FamilyReunion-PT-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-13: LTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-14: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 LTL EXCL 19/239 4/32 FamilyReunion-PT-L00010M0001C001P001G001-13 470836 m, 27111 m/sec, 3097858 t fired, .
Time elapsed: 27 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-08: CONJ false preprocessing
FamilyReunion-PT-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-09: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-10: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-11: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-13: LTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-14: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 LTL EXCL 24/239 4/32 FamilyReunion-PT-L00010M0001C001P001G001-13 599970 m, 25826 m/sec, 3925227 t fired, .
Time elapsed: 32 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-08: CONJ false preprocessing
FamilyReunion-PT-L00010M0001C001P001G001-12: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-02: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-03: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-06: LTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-07: LTL 0 1 0 0 1 0 0 0
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54 LTL EXCL 20/483 14/32 FamilyReunion-PT-L00010M0001C001P001G001-15 1803576 m, 89517 m/sec, 2879641 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-12: AG false state space
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FamilyReunion-PT-L00010M0001C001P001G001-00: LTL true LTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-02: CONJ false LTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-03: LTL false LTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-04: LTL false LTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-08: CONJ false preprocessing
FamilyReunion-PT-L00010M0001C001P001G001-09: LTL true LTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-11: LTL false LTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-12: AG false state space
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FamilyReunion-PT-L00010M0001C001P001G001-01: LTL 0 0 0 0 1 0 1 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00010M0001C001P001G001"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is FamilyReunion-PT-L00010M0001C001P001G001, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r080-tall-162048871600941"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00010M0001C001P001G001.tgz
mv FamilyReunion-PT-L00010M0001C001P001G001 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;