MCC'2021- Execution of r061-tall-162038393100354

About the Execution of LoLA for DLCround-PT-08a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
15352.031	3600000.00	4877667.00	10123.30	?????F??TT?T?FFT	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.
Waiting for the VM to be
..................................
............
==================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCround-PT-08a,
Time confinement is 3600
Memory confinement is
Number of cores is 4
Run identifier is r061-tall-16
==================================

--------------------
preparation of the directory
/home/mcc/execution
total 848K
-rw-r--r-- 1 mcc users 13K May
-rw-r--r-- 1 mcc users 124K
-rw-r--r-- 1 mcc users 9.8K May
-rw-r--r-- 1 mcc users 87K
-rw-r--r-- 1 mcc users 4.2K May
-rw-r--r-- 1 mcc users 6.4K May
-rw-r--r-- 1 mcc users 3.3K
-rw-r--r-- 1 mcc users 25K
-rw-r--r-- 1 mcc users 1.9K
-rw-r--r-- 1 mcc users 16K
-rw-r--r-- 1 mcc users 3.2K
-rw-r--r-- 1 mcc users 16K
-rw-r--r-- 1 mcc users 2.5K
-rw-r--r-- 1 mcc users 14K
-rw-r--r-- 1 mcc users 1.6K
-rw-r--r-- 1 mcc users 3.6K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 479K May

--------------------
content from stdout:

=== Data for post analysis

The expected result is a
BOOL_VECTOR

here is the order used to
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi
FORMULA_NAME DLCround-PT-08a-CTLFi

=== Now, execution of the

BK_START 1620752697431

starting LoLA
BK_INPUT DLCround-PT-08a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/
current directory: /home/mcc/execu
CTLFireability

FORMULA DLCround-PT-08a-CTLFireability-15

FORMULA DLCround-PT-08a-CTLFireability-14

FORMULA DLCround-PT-08a-CTLFireability-05

FORMULA DLCround-PT-08a-CTLFireability-13

FORMULA DLCround-PT-08a-CTLFireability-09

FORMULA DLCround-PT-08a-CTLFireability-11

FORMULA DLCround-PT-08a-CTLFireability-08

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file
lola: reading net from
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file /home/mcc/
lola: Reading formula.
lola: Using XML format
lola: reading XML formula
lola: reading formula from
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: RELEASE
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Rule S: 0 transitions
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
FINISHED FORMULA: CATEGORY

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 45 secs.
# running tasks: 0 of 4 Visible:
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: LAUNCH task # 58
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 59
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 60
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 61
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: FINISHED task # 60
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: CANCELED task # 58
lola: CANCELED task # 59
lola: CANCELED task # 61
lola: LAUNCH task # 70
lola: time limit : 169 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 68
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 69
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 71
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: FINISHED task # 58
lola: result
lola: fired transitions :
lola: tried executions :
lola: time used :
lola: memory pages used :
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: FINISHED task # 70
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: CANCELED task # 68
lola: CANCELED task # 69
lola: CANCELED task # 71
lola: LAUNCH task # 64
lola: time limit : 177 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 62
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 63
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 65
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: FINISHED task # 71
lola: result
lola: time used :
lola: memory pages used :
lola: rewrite Frontend/Parser/fo
sara: try reading problem
sara: place or transition
lola: FINISHED task # 68
lola: result
lola: fired transitions :
lola: tried executions :
lola: time used :
lola: memory pages used :

sara: try reading problem
lola: Created skeleton
sara: place or transition
lola: FINISHED task # 61
lola: result
lola: time used :
lola: memory pages used :
lola: FINISHED task # 62
lola: result
lola: fired transitions :
lola: tried executions :
lola: time used :
lola: memory pages used :
lola: FINISHED task # 65
lola: result
lola: time used :
lola: memory pages used :
lola: CANCELED task # 63
lola: CANCELED task # 64
lola: LAUNCH task # 66
lola: time limit : 187 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: FINISHED task # 63
lola: result
lola: FINISHED task # 59
lola: result
sara: try reading problem
sara: place or transition

lola: FINISHED task # 66
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 20
lola: time limit : 209 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20
lola: result
lola: markings :
lola: time used :
lola: memory pages used :
lola: FINISHED task # 69
lola: result
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: LAUNCH task # 32
lola: time limit : 253 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: Created skeleton
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 2/253

Time elapsed: 50 secs.
# running tasks: 1 of 4 Visible:
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 7/273

Time elapsed: 55 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 12/273

Time elapsed: 60 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 17/273

Time elapsed: 65 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 22/273

Time elapsed: 70 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 27/273

Time elapsed: 75 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 32/273

Time elapsed: 80 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 37/273

Time elapsed: 85 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 42/273

Time elapsed: 90 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 47/273

Time elapsed: 95 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 52/273

Time elapsed: 100 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 57/273

Time elapsed: 105 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 62/273

Time elapsed: 110 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 67/273

Time elapsed: 115 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 72/273

Time elapsed: 120 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 77/273

Time elapsed: 125 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 82/273

Time elapsed: 130 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 87/273

Time elapsed: 135 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 92/273

Time elapsed: 140 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 97/273

Time elapsed: 145 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 102/273

Time elapsed: 150 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 107/273

Time elapsed: 155 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 112/273

Time elapsed: 160 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 117/273

Time elapsed: 165 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 122/273

Time elapsed: 170 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 128/273

Time elapsed: 176 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 133/273

Time elapsed: 181 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 138/273

Time elapsed: 186 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 143/273

Time elapsed: 191 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 148/273

Time elapsed: 196 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 153/273

Time elapsed: 201 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 158/273

Time elapsed: 206 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 163/273

Time elapsed: 211 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 168/273

Time elapsed: 216 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 173/273

Time elapsed: 221 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 178/273

Time elapsed: 226 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 183/273

Time elapsed: 231 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 188/273

Time elapsed: 236 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 193/273

Time elapsed: 241 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 198/273

Time elapsed: 246 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 203/273

Time elapsed: 251 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 208/273

Time elapsed: 256 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 213/273

Time elapsed: 261 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 218/273

Time elapsed: 266 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 223/273

Time elapsed: 271 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 228/273

Time elapsed: 276 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 233/273

Time elapsed: 281 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 238/273

Time elapsed: 286 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 243/273

Time elapsed: 291 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 248/273

Time elapsed: 296 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 253/273

Time elapsed: 301 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 258/273

Time elapsed: 306 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 263/273

Time elapsed: 311 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 268/273

Time elapsed: 316 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 273/273

Time elapsed: 321 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 32
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:
DLCround-PT-08a-CTLFireability-13:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 326 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 44
lola: time limit : 272 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 32
lola: time limit : 3274 sec
lola: memory limit: 5 pages
lola: FINISHED task # 44
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 5/272

Time elapsed: 331 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 10/272

Time elapsed: 336 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 15/272

Time elapsed: 341 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 20/272

Time elapsed: 346 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 25/272

Time elapsed: 351 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 30/272

Time elapsed: 356 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 35/272

Time elapsed: 361 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 40/272

Time elapsed: 366 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 45/272

Time elapsed: 371 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 50/272

Time elapsed: 376 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 55/272

Time elapsed: 381 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 60/272

Time elapsed: 386 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 65/272

Time elapsed: 391 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 70/272

Time elapsed: 396 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 75/272

Time elapsed: 401 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 80/272

Time elapsed: 406 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 85/272

Time elapsed: 411 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 90/272

Time elapsed: 416 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 95/272

Time elapsed: 421 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 100/272

Time elapsed: 426 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 105/272

Time elapsed: 431 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 110/272

Time elapsed: 436 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 115/272

Time elapsed: 441 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 120/272

Time elapsed: 446 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 125/272

Time elapsed: 451 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 130/272

Time elapsed: 456 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 135/272

Time elapsed: 461 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 140/272

Time elapsed: 466 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 145/272

Time elapsed: 471 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 150/272

Time elapsed: 476 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 155/272

Time elapsed: 481 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
32 CTL EXCL 160/272

Time elapsed: 486 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 32
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 491 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 41
lola: time limit : 282 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 5/282

Time elapsed: 496 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 10/282

Time elapsed: 501 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 15/282

Time elapsed: 506 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 20/282

Time elapsed: 511 secs.
# running tasks: 1 of 4 Visible:
lola: FINISHED task # 32
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 25/282

Time elapsed: 516 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 30/282

Time elapsed: 521 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 36/282

Time elapsed: 527 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 41/282

Time elapsed: 532 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 46/282

Time elapsed: 537 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 51/282

Time elapsed: 542 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 56/282

Time elapsed: 547 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 61/282

Time elapsed: 552 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 66/282

Time elapsed: 557 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 71/282

Time elapsed: 562 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 76/282

Time elapsed: 567 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 81/282

Time elapsed: 572 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 86/282

Time elapsed: 577 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 91/282

Time elapsed: 582 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 96/282

Time elapsed: 587 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 101/282

Time elapsed: 592 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 106/282

Time elapsed: 597 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 111/282

Time elapsed: 602 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 116/282

Time elapsed: 607 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 121/282

Time elapsed: 612 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 126/282

Time elapsed: 617 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 131/282

Time elapsed: 622 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 136/282

Time elapsed: 627 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 141/282

Time elapsed: 632 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 146/282

Time elapsed: 637 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 151/282

Time elapsed: 642 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 156/282

Time elapsed: 647 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 161/282

Time elapsed: 652 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 166/282

Time elapsed: 657 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 171/282

Time elapsed: 662 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 176/282

Time elapsed: 667 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 181/282

Time elapsed: 672 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 186/282

Time elapsed: 677 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 191/282

Time elapsed: 682 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 196/282

Time elapsed: 687 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 201/282

Time elapsed: 692 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 206/282

Time elapsed: 697 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 211/282

Time elapsed: 702 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 216/282

Time elapsed: 707 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 221/282

Time elapsed: 712 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 226/282

Time elapsed: 717 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 231/282

Time elapsed: 722 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 236/282

Time elapsed: 727 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 241/282

Time elapsed: 732 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 246/282

Time elapsed: 737 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 251/282

Time elapsed: 742 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 256/282

Time elapsed: 747 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 261/282

Time elapsed: 752 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 266/282

Time elapsed: 757 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 271/282

Time elapsed: 762 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 276/282

Time elapsed: 767 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 281/282

Time elapsed: 772 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 41
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 777 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 38
lola: time limit : 282 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 41
lola: time limit : 2823 sec
lola: memory limit: 5 pages
lola: FINISHED task # 38
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 5/282

Time elapsed: 782 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 10/282

Time elapsed: 787 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 15/282

Time elapsed: 792 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 20/282

Time elapsed: 797 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 25/282

Time elapsed: 802 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 30/282

Time elapsed: 807 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 35/282

Time elapsed: 812 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 40/282

Time elapsed: 817 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 45/282

Time elapsed: 822 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 50/282

Time elapsed: 827 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 55/282

Time elapsed: 832 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 60/282

Time elapsed: 837 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 65/282

Time elapsed: 842 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 70/282

Time elapsed: 847 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 75/282

Time elapsed: 852 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 80/282

Time elapsed: 857 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 85/282

Time elapsed: 862 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 90/282

Time elapsed: 867 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 95/282

Time elapsed: 872 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 100/282

Time elapsed: 877 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 105/282

Time elapsed: 882 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 110/282

Time elapsed: 887 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 115/282

Time elapsed: 892 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 120/282

Time elapsed: 897 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 125/282

Time elapsed: 902 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 130/282

Time elapsed: 907 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 135/282

Time elapsed: 912 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 140/282

Time elapsed: 917 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 145/282

Time elapsed: 922 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 150/282

Time elapsed: 927 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 155/282

Time elapsed: 932 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 160/282

Time elapsed: 937 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 165/282

Time elapsed: 942 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 170/282

Time elapsed: 947 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 175/282

Time elapsed: 952 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 180/282

Time elapsed: 957 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 185/282

Time elapsed: 962 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 190/282

Time elapsed: 967 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
41 CTL EXCL 195/282

Time elapsed: 972 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 41
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 977 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 35
lola: time limit : 291 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 5/291

Time elapsed: 982 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 10/291

Time elapsed: 987 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 15/291

Time elapsed: 992 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 20/291

Time elapsed: 997 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 25/291

Time elapsed: 1002 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 30/291

Time elapsed: 1007 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 35/291

Time elapsed: 1012 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 40/291

Time elapsed: 1017 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 45/291

Time elapsed: 1022 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 50/291

Time elapsed: 1027 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 55/291

Time elapsed: 1032 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 60/291

Time elapsed: 1037 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 65/291

Time elapsed: 1042 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 70/291

Time elapsed: 1047 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 75/291

Time elapsed: 1052 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 80/291

Time elapsed: 1057 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 85/291

Time elapsed: 1062 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 90/291

Time elapsed: 1067 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 95/291

Time elapsed: 1072 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 100/291

Time elapsed: 1077 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 105/291

Time elapsed: 1082 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 110/291

Time elapsed: 1087 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 115/291

Time elapsed: 1092 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 120/291

Time elapsed: 1097 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 125/291

Time elapsed: 1102 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 130/291

Time elapsed: 1107 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 135/291

Time elapsed: 1112 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 140/291

Time elapsed: 1117 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 145/291

Time elapsed: 1122 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 150/291

Time elapsed: 1127 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 155/291

Time elapsed: 1132 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 160/291

Time elapsed: 1137 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 165/291

Time elapsed: 1142 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 170/291

Time elapsed: 1147 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 175/291

Time elapsed: 1152 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 180/291

Time elapsed: 1157 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 185/291

Time elapsed: 1162 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 190/291

Time elapsed: 1167 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 195/291

Time elapsed: 1172 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 200/291

Time elapsed: 1177 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 205/291

Time elapsed: 1182 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 210/291

Time elapsed: 1187 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 215/291

Time elapsed: 1192 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 220/291

Time elapsed: 1197 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 225/291

Time elapsed: 1202 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 230/291

Time elapsed: 1207 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 235/291

Time elapsed: 1212 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 240/291

Time elapsed: 1217 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 245/291

Time elapsed: 1222 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 250/291

Time elapsed: 1227 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 255/291

Time elapsed: 1232 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 260/291

Time elapsed: 1237 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 265/291

Time elapsed: 1242 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 270/291

Time elapsed: 1247 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 275/291

Time elapsed: 1252 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 280/291

Time elapsed: 1257 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 285/291

Time elapsed: 1262 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 290/291

Time elapsed: 1267 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 35
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1272 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 29
lola: time limit : 291 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 35
lola: time limit : 2328 sec
lola: memory limit: 5 pages
lola: FINISHED task # 29
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 4/290

Time elapsed: 1277 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 9/290

Time elapsed: 1282 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 14/290

Time elapsed: 1287 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 19/290

Time elapsed: 1292 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 24/290

Time elapsed: 1297 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 29/290

Time elapsed: 1302 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 34/290

Time elapsed: 1307 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 39/290

Time elapsed: 1312 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 44/290

Time elapsed: 1317 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 49/290

Time elapsed: 1322 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 54/290

Time elapsed: 1327 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 59/290

Time elapsed: 1332 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 64/290

Time elapsed: 1337 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 69/290

Time elapsed: 1342 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 74/290

Time elapsed: 1347 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 79/290

Time elapsed: 1352 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 84/290

Time elapsed: 1357 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 89/290

Time elapsed: 1362 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 95/290

Time elapsed: 1368 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 100/290

Time elapsed: 1373 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 105/290

Time elapsed: 1378 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 110/290

Time elapsed: 1383 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 115/290

Time elapsed: 1388 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 120/290

Time elapsed: 1393 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 125/290

Time elapsed: 1398 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 130/290

Time elapsed: 1403 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 135/290

Time elapsed: 1408 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 140/290

Time elapsed: 1413 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 145/290

Time elapsed: 1418 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 150/290

Time elapsed: 1423 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 155/290

Time elapsed: 1428 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 160/290

Time elapsed: 1433 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 165/290

Time elapsed: 1438 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 170/290

Time elapsed: 1443 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 175/290

Time elapsed: 1448 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 180/290

Time elapsed: 1453 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 185/290

Time elapsed: 1458 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 190/290

Time elapsed: 1463 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 195/290

Time elapsed: 1468 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 200/290

Time elapsed: 1473 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 205/290

Time elapsed: 1478 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 210/290

Time elapsed: 1483 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 215/290

Time elapsed: 1488 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 220/290

Time elapsed: 1493 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 225/290

Time elapsed: 1498 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 230/290

Time elapsed: 1503 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 235/290

Time elapsed: 1508 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 240/290

Time elapsed: 1513 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 245/290

Time elapsed: 1518 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 250/290

Time elapsed: 1523 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 255/290

Time elapsed: 1528 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 260/290

Time elapsed: 1533 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 265/290

Time elapsed: 1538 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 270/290

Time elapsed: 1543 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 275/290

Time elapsed: 1548 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 280/290

Time elapsed: 1553 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 285/290

Time elapsed: 1558 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 290/290

Time elapsed: 1563 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 35
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 1568 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 26
lola: time limit : 290 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 35
lola: time limit : 2032 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 5/290
35 CTL EXCL 4/2032

Time elapsed: 1573 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 10/290
35 CTL EXCL 9/253

Time elapsed: 1578 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 15/290
35 CTL EXCL 14/253

Time elapsed: 1583 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 20/290
35 CTL EXCL 19/253

Time elapsed: 1588 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 25/290
35 CTL EXCL 24/253

Time elapsed: 1593 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 30/290
35 CTL EXCL 29/253

Time elapsed: 1598 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 35/290
35 CTL EXCL 34/253

Time elapsed: 1603 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 40/290
35 CTL EXCL 39/253

Time elapsed: 1608 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 45/290
35 CTL EXCL 44/253

Time elapsed: 1613 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 50/290
35 CTL EXCL 49/253

Time elapsed: 1618 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 55/290
35 CTL EXCL 54/253

Time elapsed: 1623 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 60/290
35 CTL EXCL 59/253

Time elapsed: 1628 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 65/290
35 CTL EXCL 64/253

Time elapsed: 1633 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 70/290
35 CTL EXCL 69/253

Time elapsed: 1638 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 75/290
35 CTL EXCL 74/253

Time elapsed: 1643 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 80/290
35 CTL EXCL 79/253

Time elapsed: 1648 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 85/290
35 CTL EXCL 84/253

Time elapsed: 1653 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 90/290
35 CTL EXCL 89/253

Time elapsed: 1658 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 95/290
35 CTL EXCL 94/253

Time elapsed: 1663 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 100/290
35 CTL EXCL 99/253

Time elapsed: 1668 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 105/290
35 CTL EXCL 104/253

Time elapsed: 1673 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 110/290
35 CTL EXCL 109/253

Time elapsed: 1678 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 115/290
35 CTL EXCL 114/253

Time elapsed: 1683 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 120/290
35 CTL EXCL 119/253

Time elapsed: 1688 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 125/290
35 CTL EXCL 124/253

Time elapsed: 1693 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 130/290
35 CTL EXCL 129/253

Time elapsed: 1698 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 135/290
35 CTL EXCL 134/253

Time elapsed: 1703 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 140/290
35 CTL EXCL 139/253

Time elapsed: 1708 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 145/290
35 CTL EXCL 144/253

Time elapsed: 1713 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 150/290
35 CTL EXCL 149/253

Time elapsed: 1718 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 155/290
35 CTL EXCL 154/253

Time elapsed: 1723 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 160/290
35 CTL EXCL 159/253

Time elapsed: 1728 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 165/290
35 CTL EXCL 164/253

Time elapsed: 1733 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 170/290
35 CTL EXCL 169/253

Time elapsed: 1738 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 176/290
35 CTL EXCL 175/253

Time elapsed: 1744 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 181/290
35 CTL EXCL 180/253

Time elapsed: 1749 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 186/290
35 CTL EXCL 185/253

Time elapsed: 1754 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 191/290
35 CTL EXCL 190/253

Time elapsed: 1759 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 196/290
35 CTL EXCL 195/253

Time elapsed: 1764 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 201/290
35 CTL EXCL 200/253

Time elapsed: 1769 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 206/290
35 CTL EXCL 205/253

Time elapsed: 1774 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 211/290
35 CTL EXCL 210/253

Time elapsed: 1779 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 216/290
35 CTL EXCL 215/253

Time elapsed: 1784 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 221/290
35 CTL EXCL 220/253

Time elapsed: 1789 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 226/290
35 CTL EXCL 225/253

Time elapsed: 1794 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 231/290
35 CTL EXCL 230/253

Time elapsed: 1799 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 236/290
35 CTL EXCL 235/253

Time elapsed: 1804 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 241/290
35 CTL EXCL 240/253

Time elapsed: 1809 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 246/290
35 CTL EXCL 245/253

Time elapsed: 1814 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 251/290
35 CTL EXCL 250/253

Time elapsed: 1819 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 35
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 256/290

Time elapsed: 1824 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 35
lola: time limit : 1776 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 261/290
35 CTL EXCL 4/1776

Time elapsed: 1829 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 266/290
35 CTL EXCL 9/221

Time elapsed: 1834 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 271/290
35 CTL EXCL 14/221

Time elapsed: 1839 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 276/290
35 CTL EXCL 19/221

Time elapsed: 1844 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 281/290
35 CTL EXCL 24/221

Time elapsed: 1849 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 286/290
35 CTL EXCL 29/221

Time elapsed: 1854 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 26
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 34/221

Time elapsed: 1859 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 26
lola: time limit : 1741 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 0/1741
35 CTL EXCL 39/253

Time elapsed: 1864 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 5/1741
35 CTL EXCL 44/221

Time elapsed: 1869 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 10/1741
35 CTL EXCL 49/221

Time elapsed: 1874 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 15/1741
35 CTL EXCL 54/221

Time elapsed: 1879 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 20/1741
35 CTL EXCL 59/221

Time elapsed: 1884 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 25/1741
35 CTL EXCL 64/221

Time elapsed: 1889 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 30/1741
35 CTL EXCL 69/221

Time elapsed: 1894 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 35/1741
35 CTL EXCL 74/221

Time elapsed: 1899 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 40/1741
35 CTL EXCL 79/221

Time elapsed: 1904 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 45/1741
35 CTL EXCL 84/221

Time elapsed: 1909 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 50/1741
35 CTL EXCL 89/221

Time elapsed: 1914 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 55/1741
35 CTL EXCL 94/221

Time elapsed: 1919 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 60/1741
35 CTL EXCL 99/221

Time elapsed: 1924 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 65/1741
35 CTL EXCL 104/221

Time elapsed: 1929 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 70/1741
35 CTL EXCL 109/221

Time elapsed: 1934 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 75/1741
35 CTL EXCL 114/221

Time elapsed: 1939 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 80/1741
35 CTL EXCL 119/221

Time elapsed: 1944 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 85/1741
35 CTL EXCL 124/221

Time elapsed: 1949 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 90/1741
35 CTL EXCL 129/221

Time elapsed: 1954 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 95/1741
35 CTL EXCL 134/221

Time elapsed: 1959 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 100/1741
35 CTL EXCL 139/221

Time elapsed: 1964 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 105/1741
35 CTL EXCL 144/221

Time elapsed: 1969 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 110/1741
35 CTL EXCL 149/221

Time elapsed: 1974 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 115/1741
35 CTL EXCL 154/221

Time elapsed: 1979 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 120/1741
35 CTL EXCL 159/221

Time elapsed: 1984 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 125/1741
35 CTL EXCL 164/221

Time elapsed: 1989 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 130/1741
35 CTL EXCL 169/221

Time elapsed: 1994 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 135/1741
35 CTL EXCL 174/221

Time elapsed: 1999 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 140/1741
35 CTL EXCL 179/221

Time elapsed: 2004 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 145/1741
35 CTL EXCL 184/221

Time elapsed: 2009 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 150/1741
35 CTL EXCL 189/221

Time elapsed: 2014 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 155/1741
35 CTL EXCL 194/221

Time elapsed: 2019 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 160/1741
35 CTL EXCL 199/221

Time elapsed: 2024 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 165/1741
35 CTL EXCL 204/221

Time elapsed: 2029 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 170/1741
35 CTL EXCL 209/221

Time elapsed: 2034 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 175/1741
35 CTL EXCL 214/221

Time elapsed: 2039 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 180/1741
35 CTL EXCL 219/221

Time elapsed: 2044 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 35
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 185/1741

Time elapsed: 2049 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 35
lola: time limit : 1551 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 221/248
35 CTL EXCL 0/1551

Time elapsed: 2085 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 226/248
35 CTL EXCL 5/189

Time elapsed: 2090 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 231/248
35 CTL EXCL 10/189

Time elapsed: 2095 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 236/248
35 CTL EXCL 15/189

Time elapsed: 2100 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 241/248
35 CTL EXCL 20/189

Time elapsed: 2105 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 246/248
35 CTL EXCL 25/189

Time elapsed: 2110 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 26
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 30/189

Time elapsed: 2115 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 26
lola: time limit : 1485 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 2/1485
35 CTL EXCL 35/216

Time elapsed: 2120 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 7/1485
35 CTL EXCL 40/189

Time elapsed: 2125 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 12/1485
35 CTL EXCL 45/189

Time elapsed: 2130 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 17/1485
35 CTL EXCL 50/189

Time elapsed: 2135 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 22/1485
35 CTL EXCL 55/189

Time elapsed: 2140 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 27/1485
35 CTL EXCL 60/189

Time elapsed: 2145 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 32/1485
35 CTL EXCL 65/189

Time elapsed: 2150 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 37/1485
35 CTL EXCL 70/189

Time elapsed: 2155 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 42/1485
35 CTL EXCL 75/189

Time elapsed: 2160 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 47/1485
35 CTL EXCL 80/189

Time elapsed: 2165 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 52/1485
35 CTL EXCL 85/189

Time elapsed: 2170 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 57/1485
35 CTL EXCL 90/189

Time elapsed: 2175 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 62/1485
35 CTL EXCL 95/189

Time elapsed: 2180 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 67/1485
35 CTL EXCL 100/189

Time elapsed: 2185 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 72/1485
35 CTL EXCL 105/189

Time elapsed: 2190 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 77/1485
35 CTL EXCL 110/189

Time elapsed: 2195 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 82/1485
35 CTL EXCL 115/189

Time elapsed: 2200 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 87/1485
35 CTL EXCL 120/189

Time elapsed: 2205 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 92/1485
35 CTL EXCL 125/189

Time elapsed: 2210 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 97/1485
35 CTL EXCL 130/189

Time elapsed: 2215 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 102/1485
35 CTL EXCL 135/189

Time elapsed: 2220 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 107/1485
35 CTL EXCL 140/189

Time elapsed: 2225 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 112/1485
35 CTL EXCL 145/189

Time elapsed: 2230 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 117/1485
35 CTL EXCL 150/189

Time elapsed: 2235 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 122/1485
35 CTL EXCL 155/189

Time elapsed: 2240 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 127/1485
35 CTL EXCL 160/189

Time elapsed: 2245 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 132/1485
35 CTL EXCL 165/189

Time elapsed: 2250 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 137/1485
35 CTL EXCL 170/189

Time elapsed: 2255 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 142/1485
35 CTL EXCL 175/189

Time elapsed: 2260 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 147/1485
35 CTL EXCL 180/189

Time elapsed: 2265 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 152/1485
35 CTL EXCL 185/189

Time elapsed: 2270 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 35
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 157/1485

Time elapsed: 2275 secs.
# running tasks: 2 of 4 Visible:
lola: LAUNCH task # 35
lola: time limit : 1325 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 186/211
35 CTL EXCL 1/1325

Time elapsed: 2304 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 191/211
35 CTL EXCL 6/162

Time elapsed: 2309 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 196/211
35 CTL EXCL 11/162

Time elapsed: 2314 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 201/211
35 CTL EXCL 16/162

Time elapsed: 2319 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 206/211
35 CTL EXCL 21/162

Time elapsed: 2324 secs.
# running tasks: 2 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:
DLCround-PT-08a-CTLFireability-10:
DLCround-PT-08a-CTLFireability-12:

TASK CATEGORY TYPE TIME/TLIMIT
26 CTL EXCL 211/211
35 CTL EXCL 26/162

Time elapsed: 2329 secs.
# running tasks: 2 of 4 Visible:
lola: CANCELED task # 26
FINISHED FORMULA: CATEGORY
DLCround-PT-08a-CTLFireability-05:
DLCround-PT-08a-CTLFireability-08:
DLCround-PT-08a-CTLFireability-09:
DLCround-PT-08a-CTLFireability-11:
DLCround-PT-08a-CTLFireability-13:
DLCround-PT-08a-CTLFireability-14:
DLCround-PT-08a-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-08a-CTLFireability-00:
DLCround-PT-08a-CTLFireability-01:
DLCround-PT-08a-CTLFireability-02:
DLCround-PT-08a-CTLFireability-03:
DLCround-PT-08a-CTLFireability-04:
DLCround-PT-08a-CTLFireability-06:
DLCround-PT-08a-CTLFireability-07:

========== file over 1MB
retrieve it from the run
r061-tall-162038393100354.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off ready (probing ssh) .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. =================================== examination is CTLFireability seconds 16384 MBytes 2038393100354 =================================== to be used: 5 16:58 CTLCardinality.txt May 10 09:42 CTLCardinality.xml 5 16:58 CTLFireability.txt May 10 09:42 CTLFireability.xml 6 14:48 GenericPropertiesDefinition.xml 6 14:48 GenericPropertiesVerdict.xml Mar 28 15:58 LTLCardinality.txt Mar 28 15:58 LTLCardinality.xml Mar 28 15:58 LTLFireability.txt Mar 28 15:58 LTLFireability.xml Mar 23 08:10 ReachabilityCardinality.txt Mar 23 08:10 ReachabilityCardinality.xml Mar 22 15:41 ReachabilityFireability.txt Mar 22 15:41 ReachabilityFireability.xml Mar 22 09:10 UpperBounds.txt Mar 22 09:10 UpperBounds.xml 6 May 5 16:51 equiv_col 4 May 5 16:51 instance 6 May 5 16:51 iscolored 5 16:51 model.pnml generated by BenchKit (invocation template) vector of booleans build the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 tool begins bin tion TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT (--pnmlnet) /home/mcc/execution/model.pnml place/transition net execution/model.pnml (--xmlformula) /home/mcc/execution/CTLFireability.xml rmula_rewrite.k:253 rmula_rewrite.k:250 rmula_rewrite.k:314 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:317 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:439 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:253 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:325 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:250 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:544 rmula_rewrite.k:553 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:553 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:340 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:325 rmula_rewrite.k:340 rmula_rewrite.k:299 rmula_rewrite.k:299 rmula_rewrite.k:397 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:253 rmula_rewrite.k:253 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:299 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:544 rmula_rewrite.k:388 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:445 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:460 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. removed,0 places removed in 1.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. in 2.000000 secs. VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CONJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 DISJ 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 16 in 1.000000 secs. in 1.000000 secs. in 0.000000 secs. in 0.000000 secs. in 0.000000 secs. rmula_rewrite.k:721 rmula_rewrite.k:788 rmula_rewrite.k:721 rmula_rewrite.k:788 rmula_rewrite.k:721 rmula_rewrite.k:788 (type SKEL/FNDP) for 46 DLCround-PT-08a-CTLFireability-14 sec (type SKEL/EQUN) for 46 DLCround-PT-08a-CTLFireability-14 sec (type SKEL/SRCH) for 46 DLCround-PT-08a-CTLFireability-14 sec (type SKEL/SRCH) for 46 DLCround-PT-08a-CTLFireability-14 sec rmula_rewrite.k:711 rmula_rewrite.k:711 rmula_rewrite.k:711 rmula_rewrite.k:749 rmula_rewrite.k:788 rmula_rewrite.k:721 rmula_rewrite.k:788 rmula_rewrite.k:721 rmula_rewrite.k:788 rmula_rewrite.k:721 rmula_rewrite.k:788 (type SKEL/SRCH) for DLCround-PT-08a-CTLFireability-14 : true 3 2 0.000000 1 (type FNDP) for DLCround-PT-08a-CTLFireability-14 (obsolete) (type EQUN) for DLCround-PT-08a-CTLFireability-14 (obsolete) (type SRCH) for DLCround-PT-08a-CTLFireability-14 (obsolete) (type EXCL) for 46 DLCround-PT-08a-CTLFireability-14 (type FNDP) for 46 DLCround-PT-08a-CTLFireability-14 sec (type EQUN) for 46 DLCround-PT-08a-CTLFireability-14 sec (type SRCH) for 46 DLCround-PT-08a-CTLFireability-14 sec (type SKEL/FNDP) for DLCround-PT-08a-CTLFireability-14 : true 1 1 0.000000 0 rmula_rewrite.k:721 rmula_rewrite.k:788 rmula_rewrite.k:721 rmula_rewrite.k:788 (type EXCL) for DLCround-PT-08a-CTLFireability-14 : true 3 2 0.000000 1 (type FNDP) for DLCround-PT-08a-CTLFireability-14 (obsolete) (type EQUN) for DLCround-PT-08a-CTLFireability-14 (obsolete) (type SRCH) for DLCround-PT-08a-CTLFireability-14 (obsolete) (type EXCL) for 53 DLCround-PT-08a-CTLFireability-15 (type FNDP) for 53 DLCround-PT-08a-CTLFireability-15 sec (type EQUN) for 53 DLCround-PT-08a-CTLFireability-15 sec (type SRCH) for 53 DLCround-PT-08a-CTLFireability-15 sec (type SRCH) for DLCround-PT-08a-CTLFireability-14 : unknown 0.000000 1 rmula_rewrite.k:711 file /home/mcc/execution/CTLFireability-59.sara. ordering is non-deterministic (type FNDP) for DLCround-PT-08a-CTLFireability-14 : true 1 1 1.000000 0 file /home/mcc/execution/CTLFireability-63.sara. in 1.000000 secs. ordering is non-deterministic (type SKEL/SRCH) for DLCround-PT-08a-CTLFireability-14 : unknown 1.000000 1 (type FNDP) for DLCround-PT-08a-CTLFireability-15 : true 1 1 1.000000 0 (type SRCH) for DLCround-PT-08a-CTLFireability-15 : unknown 1.000000 1 (type EQUN) for DLCround-PT-08a-CTLFireability-15 (obsolete) (type EXCL) for DLCround-PT-08a-CTLFireability-15 (obsolete) (type EXCL) for 46 DLCround-PT-08a-CTLFireability-14 (type EXCL) for DLCround-PT-08a-CTLFireability-15 : true 3 2 1.000000 1 (type EQUN) for DLCround-PT-08a-CTLFireability-15 : unknown (type SKEL/EQUN) for DLCround-PT-08a-CTLFireability-14 : true file /home/mcc/execution/CTLFireability-69.sara. ordering is non-deterministic (type EXCL) for DLCround-PT-08a-CTLFireability-14 : true 1 1 0.000000 1 (type EXCL) for 15 DLCround-PT-08a-CTLFireability-05 (type EXCL) for DLCround-PT-08a-CTLFireability-05 : false 1 0.000000 1 (type EQUN) for DLCround-PT-08a-CTLFireability-14 : true in 0.000000 secs. rmula_rewrite.k:813 rmula_rewrite.k:809 rmula_rewrite.k:807 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:812 rmula_rewrite.k:814 rmula_rewrite.k:813 (type EXCL) for 31 DLCround-PT-08a-CTLFireability-09 rmula_rewrite.k:808 rmula_rewrite.k:812 rmula_rewrite.k:812 rmula_rewrite.k:810 rmula_rewrite.k:811 rmula_rewrite.k:808 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:809 rmula_rewrite.k:806 rmula_rewrite.k:813 rmula_rewrite.k:809 rmula_rewrite.k:814 rmula_rewrite.k:812 rmula_rewrite.k:811 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:813 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:810 rmula_rewrite.k:808 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:815 rmula_rewrite.k:808 rmula_rewrite.k:806 rmula_rewrite.k:806 rmula_rewrite.k:815 rmula_rewrite.k:807 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:811 rmula_rewrite.k:814 rmula_rewrite.k:809 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:813 in 1.000000 secs. VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 1 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-09 16398 m, 3279 m/sec, 324436 t fired, . Pages in use: 3 16 rmula_rewrite.k:813 rmula_rewrite.k:808 rmula_rewrite.k:809 rmula_rewrite.k:807 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:806 rmula_rewrite.k:813 rmula_rewrite.k:812 rmula_rewrite.k:813 rmula_rewrite.k:808 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:809 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:814 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:814 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:812 rmula_rewrite.k:814 rmula_rewrite.k:807 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:809 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-09 56897 m, 8099 m/sec, 1120666 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-09 93572 m, 7335 m/sec, 1827175 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-09 128010 m, 6887 m/sec, 2524247 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-09 165622 m, 7522 m/sec, 3269649 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-09 200210 m, 6917 m/sec, 3970811 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-09 250961 m, 10150 m/sec, 4976719 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-09 296064 m, 9020 m/sec, 5868556 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-09 321559 m, 5099 m/sec, 6359594 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-09 362472 m, 8182 m/sec, 7178622 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-09 404367 m, 8379 m/sec, 8010626 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-09 430416 m, 5209 m/sec, 8545486 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-09 470078 m, 7932 m/sec, 9346600 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-09 518972 m, 9778 m/sec, 10300180 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-09 562977 m, 8801 m/sec, 11190272 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-09 601034 m, 7611 m/sec, 11986720 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-09 646690 m, 9131 m/sec, 12897702 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-09 678515 m, 6365 m/sec, 13539328 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-09 722574 m, 8811 m/sec, 14406589 t fired, . Pages in use: 3 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-09 758356 m, 7156 m/sec, 15139013 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-09 785473 m, 5423 m/sec, 15696148 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-09 814206 m, 5746 m/sec, 16288049 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-09 847934 m, 6745 m/sec, 16963128 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-09 871920 m, 4797 m/sec, 17435486 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-09 922679 m, 10151 m/sec, 18424131 t fired, . Pages in use: 4 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-09 977107 m, 10885 m/sec, 19507246 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-09 1016572 m, 7893 m/sec, 20285836 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-09 1067067 m, 10099 m/sec, 21305114 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-09 1109526 m, 8491 m/sec, 22143745 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-09 1159775 m, 10049 m/sec, 23113526 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-09 1194194 m, 6883 m/sec, 23798988 t fired, . Pages in use: 5 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-09 1231613 m, 7483 m/sec, 24554052 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-09 1254431 m, 4563 m/sec, 25017934 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-09 1287225 m, 6558 m/sec, 25661885 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-09 1335154 m, 9585 m/sec, 26601169 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-09 1372421 m, 7453 m/sec, 27344047 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-09 1413785 m, 8272 m/sec, 28165660 t fired, . Pages in use: 6 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-09 1454955 m, 8234 m/sec, 28986031 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-09 1481396 m, 5288 m/sec, 29534626 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-09 1520622 m, 7845 m/sec, 30316786 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-09 1557836 m, 7442 m/sec, 31051981 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-09 1617764 m, 11985 m/sec, 32250754 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-09 1654334 m, 7314 m/sec, 33008855 t fired, . Pages in use: 7 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-09 1696954 m, 8524 m/sec, 33870652 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-09 1728384 m, 6286 m/sec, 34515920 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-09 1774671 m, 9257 m/sec, 35409895 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-09 1820772 m, 9220 m/sec, 36356360 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-09 1854288 m, 6703 m/sec, 37028176 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-09 1889292 m, 7000 m/sec, 37752325 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-09 1925424 m, 7226 m/sec, 38411235 t fired, . Pages in use: 8 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-08a-CTLFireability-09 1975320 m, 9979 m/sec, 39255493 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-08a-CTLFireability-09 2012359 m, 7407 m/sec, 39891522 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-08a-CTLFireability-09 2048874 m, 7303 m/sec, 40523356 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-08a-CTLFireability-09 2084983 m, 7221 m/sec, 41152901 t fired, . Pages in use: 9 16 VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-08a-CTLFireability-09 2140310 m, 11065 m/sec, 42110849 t fired, . Pages in use: 9 16 (type EXCL) for DLCround-PT-08a-CTLFireability-09 (local timeout) VALUE PRODUCED BY CONJ false state space / EG DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 10 16 (type EXCL) for 43 DLCround-PT-08a-CTLFireability-13 (type EXCL) for 31 DLCround-PT-08a-CTLFireability-09 (type EXCL) for DLCround-PT-08a-CTLFireability-13 : false 7 17 0.000000 1 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-09 42431 m, -419575 m/sec, 849103 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-09 89895 m, 9492 m/sec, 1758104 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-09 131705 m, 8362 m/sec, 2595239 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-09 160824 m, 5823 m/sec, 3167947 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-09 205484 m, 8932 m/sec, 4075209 t fired, . Pages in use: 12 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-09 234846 m, 5872 m/sec, 4651283 t fired, . Pages in use: 13 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-09 266694 m, 6369 m/sec, 5282989 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-09 302170 m, 7095 m/sec, 5977380 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-09 351024 m, 9770 m/sec, 6951928 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-09 386683 m, 7131 m/sec, 7667537 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-09 422163 m, 7096 m/sec, 8383736 t fired, . Pages in use: 14 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-09 460314 m, 7630 m/sec, 9144532 t fired, . Pages in use: 15 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-09 497171 m, 7371 m/sec, 9879939 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-09 529974 m, 6560 m/sec, 10522945 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-09 572962 m, 8597 m/sec, 11388306 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-09 615404 m, 8488 m/sec, 12284199 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-09 653210 m, 7561 m/sec, 13029346 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-09 697182 m, 8794 m/sec, 13901466 t fired, . Pages in use: 16 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-09 738378 m, 8239 m/sec, 14724202 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-09 775594 m, 7443 m/sec, 15487754 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-09 809113 m, 6703 m/sec, 16170925 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-09 846042 m, 7385 m/sec, 16923543 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-09 857727 m, 2337 m/sec, 17160802 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-09 900360 m, 8526 m/sec, 18011203 t fired, . Pages in use: 18 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-09 940456 m, 8019 m/sec, 18765450 t fired, . Pages in use: 19 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-09 979707 m, 7850 m/sec, 19555533 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-09 1010733 m, 6205 m/sec, 20166783 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-09 1044537 m, 6760 m/sec, 20853509 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-09 1087477 m, 8588 m/sec, 21714791 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-09 1122707 m, 7046 m/sec, 22386173 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-09 1159849 m, 7428 m/sec, 23115660 t fired, . Pages in use: 20 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-09 1199864 m, 8003 m/sec, 23911297 t fired, . Pages in use: 21 16 (type EXCL) for DLCround-PT-08a-CTLFireability-09 (memory limit exceeded) VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 21 16 (type EXCL) for 40 DLCround-PT-08a-CTLFireability-12 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-12 42020 m, 8404 m/sec, 850802 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-12 81941 m, 7984 m/sec, 1615336 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-12 121928 m, 7997 m/sec, 2411015 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-12 156403 m, 6895 m/sec, 3209152 t fired, . Pages in use: 21 16 (type EXCL) for DLCround-PT-08a-CTLFireability-09 : true 1207634 24059052 187.000000 0 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-12 185501 m, 5819 m/sec, 3880745 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-12 234219 m, 9743 m/sec, 4950978 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-12 279691 m, 9094 m/sec, 6028916 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-12 326200 m, 9301 m/sec, 7125443 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-12 361888 m, 7137 m/sec, 7970143 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-12 400505 m, 7723 m/sec, 8860406 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-12 433099 m, 6518 m/sec, 9632312 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-12 460842 m, 5548 m/sec, 10287975 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-12 489512 m, 5734 m/sec, 10947146 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-12 520219 m, 6141 m/sec, 11666260 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-12 549789 m, 5914 m/sec, 12365987 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-12 581473 m, 6336 m/sec, 13104631 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-12 618319 m, 7369 m/sec, 13937713 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-12 646819 m, 5700 m/sec, 14617884 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-12 678744 m, 6385 m/sec, 15406978 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-12 706877 m, 5626 m/sec, 16042327 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-12 738517 m, 6328 m/sec, 16777075 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-12 775250 m, 7346 m/sec, 17636046 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-12 806719 m, 6293 m/sec, 18380161 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-12 842702 m, 7196 m/sec, 19197288 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-12 868660 m, 5191 m/sec, 19823637 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-12 893448 m, 4957 m/sec, 20403401 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-12 921128 m, 5536 m/sec, 21082357 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-12 956155 m, 7005 m/sec, 21911661 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-12 999488 m, 8666 m/sec, 22869001 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-12 1039419 m, 7986 m/sec, 23740524 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-12 1058830 m, 3882 m/sec, 24221649 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-12 1085207 m, 5275 m/sec, 24811939 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-12 1117202 m, 6399 m/sec, 25557217 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-12 1150118 m, 6583 m/sec, 26270387 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-12 1175255 m, 5027 m/sec, 26855726 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-08a-CTLFireability-12 1208449 m, 6638 m/sec, 27654515 t fired, . Pages in use: 21 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-12 1230612 m, 4432 m/sec, 28196025 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-12 1259458 m, 5769 m/sec, 28857008 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-12 1301140 m, 8336 m/sec, 29808283 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-12 1332279 m, 6227 m/sec, 30529859 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-12 1371606 m, 7865 m/sec, 31464465 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-12 1417042 m, 9087 m/sec, 32543710 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-08a-CTLFireability-12 1453253 m, 7242 m/sec, 33416099 t fired, . Pages in use: 22 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-12 1481416 m, 5632 m/sec, 34060354 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-12 1510856 m, 5888 m/sec, 34748206 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-12 1535260 m, 4880 m/sec, 35317619 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-12 1562207 m, 5389 m/sec, 35934130 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-12 1591482 m, 5855 m/sec, 36624653 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-12 1621851 m, 6073 m/sec, 37339037 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-12 1643177 m, 4265 m/sec, 37870916 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-08a-CTLFireability-12 1678956 m, 7155 m/sec, 38674310 t fired, . Pages in use: 23 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-12 1705445 m, 5297 m/sec, 39319143 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-12 1728486 m, 4608 m/sec, 39864043 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-12 1748592 m, 4021 m/sec, 40335148 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-12 1772483 m, 4778 m/sec, 40876224 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-08a-CTLFireability-12 1806912 m, 6885 m/sec, 41637393 t fired, . Pages in use: 24 16 (type EXCL) for DLCround-PT-08a-CTLFireability-12 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 24 16 (type EXCL) for 37 DLCround-PT-08a-CTLFireability-11 (type EXCL) for 40 DLCround-PT-08a-CTLFireability-12 (type EXCL) for DLCround-PT-08a-CTLFireability-11 : true 15 82 0.000000 1 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-12 46414 m, -352099 m/sec, 933012 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-12 80458 m, 6808 m/sec, 1588922 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-12 119231 m, 7754 m/sec, 2361607 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-12 152214 m, 6596 m/sec, 3107044 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-12 188601 m, 7277 m/sec, 3953102 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-12 231832 m, 8646 m/sec, 4899824 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-12 254447 m, 4523 m/sec, 5455261 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-12 287533 m, 6617 m/sec, 6219857 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-12 312604 m, 5014 m/sec, 6830856 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-12 343016 m, 6082 m/sec, 7535269 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-12 368845 m, 5165 m/sec, 8133542 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-12 402401 m, 6711 m/sec, 8902240 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-12 429682 m, 5456 m/sec, 9548303 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-12 455489 m, 5161 m/sec, 10153907 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 485409 m, 5984 m/sec, 10860690 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 506298 m, 4177 m/sec, 11342050 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 529770 m, 4694 m/sec, 11884586 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 557989 m, 5643 m/sec, 12552486 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 578615 m, 4125 m/sec, 13035451 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 604367 m, 5150 m/sec, 13616666 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 632391 m, 5604 m/sec, 14256834 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 659570 m, 5435 m/sec, 14916713 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 685765 m, 5239 m/sec, 15568326 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-12 709396 m, 4726 m/sec, 16105033 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-12 745662 m, 7253 m/sec, 16934961 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-12 765542 m, 3976 m/sec, 17424240 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-12 802978 m, 7487 m/sec, 18297419 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-12 832140 m, 5832 m/sec, 18939523 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-12 868167 m, 7205 m/sec, 19811451 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-12 905492 m, 7465 m/sec, 20696707 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-12 940778 m, 7057 m/sec, 21545224 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-12 975527 m, 6949 m/sec, 22374002 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-12 1011579 m, 7210 m/sec, 23119789 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-12 1035622 m, 4808 m/sec, 23654591 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-12 1065243 m, 5924 m/sec, 24365300 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-12 1105101 m, 7971 m/sec, 25279677 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-12 1134332 m, 5846 m/sec, 25947665 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-12 1163117 m, 5757 m/sec, 26570062 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/5 DLCround-PT-08a-CTLFireability-12 1190691 m, 5514 m/sec, 27219384 t fired, . Pages in use: 24 16 (type EXCL) for DLCround-PT-08a-CTLFireability-12 (memory limit exceeded) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 24 16 (type EXCL) for 34 DLCround-PT-08a-CTLFireability-10 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 12975 m, 2595 m/sec, 450114 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 25512 m, 2507 m/sec, 899153 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 38864 m, 2670 m/sec, 1383955 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 54584 m, 3144 m/sec, 1955311 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 67636 m, 2610 m/sec, 2427362 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 81536 m, 2780 m/sec, 2947412 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 95520 m, 2796 m/sec, 3482185 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 110164 m, 2928 m/sec, 4023665 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 121799 m, 2327 m/sec, 4462761 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 134007 m, 2441 m/sec, 4909996 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 152102 m, 3619 m/sec, 5607996 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 169301 m, 3439 m/sec, 6216861 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 185993 m, 3338 m/sec, 6816881 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 203728 m, 3547 m/sec, 7454863 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 214827 m, 2219 m/sec, 7859909 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-10 232383 m, 3511 m/sec, 8501810 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 249778 m, 3479 m/sec, 9133104 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 260887 m, 2221 m/sec, 9548620 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 275062 m, 2835 m/sec, 10066895 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 289931 m, 2973 m/sec, 10610835 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 307408 m, 3495 m/sec, 11243708 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 320478 m, 2614 m/sec, 11697714 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 334900 m, 2884 m/sec, 12206960 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 352217 m, 3463 m/sec, 12833143 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 363630 m, 2282 m/sec, 13244862 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 376176 m, 2509 m/sec, 13708427 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 391930 m, 3150 m/sec, 14290433 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 409490 m, 3512 m/sec, 14965978 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 426680 m, 3438 m/sec, 15582038 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 440300 m, 2724 m/sec, 16093132 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 455167 m, 2973 m/sec, 16654981 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-08a-CTLFireability-10 468683 m, 2703 m/sec, 17149522 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 490264 m, 4316 m/sec, 17950654 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 513222 m, 4591 m/sec, 18774939 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 527864 m, 2928 m/sec, 19301900 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 542206 m, 2868 m/sec, 19829693 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 556493 m, 2857 m/sec, 20349497 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 571128 m, 2927 m/sec, 20876955 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 582016 m, 2177 m/sec, 21277764 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 600246 m, 3646 m/sec, 21949426 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 617403 m, 3431 m/sec, 22579246 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 635374 m, 3594 m/sec, 23237303 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 646464 m, 2218 m/sec, 23643658 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 658548 m, 2416 m/sec, 24088156 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 671924 m, 2675 m/sec, 24579373 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 687391 m, 3093 m/sec, 25132129 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 700607 m, 2643 m/sec, 25624730 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-08a-CTLFireability-10 715552 m, 2989 m/sec, 26151671 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 729985 m, 2886 m/sec, 26672834 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 747818 m, 3566 m/sec, 27332703 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 761551 m, 2746 m/sec, 27822544 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 774301 m, 2550 m/sec, 28292654 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 791056 m, 3351 m/sec, 28909349 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 812211 m, 4231 m/sec, 29693569 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 827901 m, 3138 m/sec, 30266919 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 846453 m, 3710 m/sec, 30949966 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 857393 m, 2188 m/sec, 31346771 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-08a-CTLFireability-10 872533 m, 3028 m/sec, 31905807 t fired, . Pages in use: 24 16 (type EXCL) for DLCround-PT-08a-CTLFireability-10 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 24 16 (type EXCL) for 28 DLCround-PT-08a-CTLFireability-08 (type EXCL) for 34 DLCround-PT-08a-CTLFireability-10 (type EXCL) for DLCround-PT-08a-CTLFireability-08 : true 5 6 1.000000 1 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 9282 m, -172650 m/sec, 318377 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 24016 m, 2946 m/sec, 843180 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 37227 m, 2642 m/sec, 1325366 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 53878 m, 3330 m/sec, 1928416 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 65150 m, 2254 m/sec, 2330960 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 79171 m, 2804 m/sec, 2860336 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 95351 m, 3236 m/sec, 3475045 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 107441 m, 2418 m/sec, 3921060 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 121400 m, 2791 m/sec, 4447713 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 134411 m, 2602 m/sec, 4924497 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 157987 m, 4715 m/sec, 5826119 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 175503 m, 3503 m/sec, 6442533 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 195703 m, 4040 m/sec, 7169415 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 214455 m, 3750 m/sec, 7845294 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 234058 m, 3920 m/sec, 8560164 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 249441 m, 3076 m/sec, 9121163 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 265065 m, 3124 m/sec, 9699231 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 281176 m, 3222 m/sec, 10291459 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 293967 m, 2558 m/sec, 10759601 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 309267 m, 3060 m/sec, 11311165 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 323206 m, 2787 m/sec, 11794962 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 338838 m, 3126 m/sec, 12349200 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 357650 m, 3762 m/sec, 13031869 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 368131 m, 2096 m/sec, 13403838 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 385060 m, 3385 m/sec, 14032204 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 402483 m, 3484 m/sec, 14691829 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 414901 m, 2483 m/sec, 15169004 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 428085 m, 2636 m/sec, 15631968 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 441137 m, 2610 m/sec, 16126236 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 452759 m, 2324 m/sec, 16564619 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 469811 m, 3410 m/sec, 17193897 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/5 DLCround-PT-08a-CTLFireability-10 483074 m, 2652 m/sec, 17689977 t fired, . Pages in use: 24 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 500062 m, 3397 m/sec, 18293421 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 513298 m, 2647 m/sec, 18777515 t fired, . Pages in use: 25 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 526647 m, 2669 m/sec, 19258654 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 545059 m, 3682 m/sec, 19937535 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 564042 m, 3796 m/sec, 20621250 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 581105 m, 3412 m/sec, 21244177 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 593980 m, 2575 m/sec, 21717953 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 610518 m, 3307 m/sec, 22324167 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 623351 m, 2566 m/sec, 22798498 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 639036 m, 3137 m/sec, 23373112 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 653773 m, 2947 m/sec, 23908042 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 668352 m, 2915 m/sec, 24445977 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 683104 m, 2950 m/sec, 24976554 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 693111 m, 2001 m/sec, 25347173 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 707651 m, 2908 m/sec, 25875278 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/5 DLCround-PT-08a-CTLFireability-10 723636 m, 3197 m/sec, 26445944 t fired, . Pages in use: 26 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 734467 m, 2166 m/sec, 26839345 t fired, . Pages in use: 27 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 748954 m, 2897 m/sec, 27375489 t fired, . Pages in use: 27 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 759594 m, 2128 m/sec, 27755645 t fired, . Pages in use: 27 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 770973 m, 2275 m/sec, 28168329 t fired, . Pages in use: 27 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 788943 m, 3594 m/sec, 28830055 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 800771 m, 2365 m/sec, 29270963 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 814524 m, 2750 m/sec, 29779050 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 826608 m, 2416 m/sec, 30219345 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 839577 m, 2593 m/sec, 30687117 t fired, . Pages in use: 28 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/5 DLCround-PT-08a-CTLFireability-10 853323 m, 2749 m/sec, 31198507 t fired, . Pages in use: 28 16 (type EXCL) for DLCround-PT-08a-CTLFireability-10 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 28 16 (type EXCL) for 25 DLCround-PT-08a-CTLFireability-07 (type EXCL) for 34 DLCround-PT-08a-CTLFireability-10 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 6547 m, 1309 m/sec, 140008 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 9343 m, -168796 m/sec, 320796 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 17700 m, 2230 m/sec, 438370 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 26151 m, 3361 m/sec, 921456 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 25224 m, 1504 m/sec, 721628 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 39176 m, 2605 m/sec, 1395455 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 31957 m, 1346 m/sec, 965838 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 49643 m, 2093 m/sec, 1768895 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 39070 m, 1422 m/sec, 1298993 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 63120 m, 2695 m/sec, 2258755 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 43761 m, 938 m/sec, 1529221 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 71293 m, 1634 m/sec, 2563766 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 48979 m, 1043 m/sec, 1652908 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 79602 m, 1661 m/sec, 2875014 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 54507 m, 1105 m/sec, 1770515 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 90484 m, 2176 m/sec, 3290647 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 57572 m, 613 m/sec, 1893903 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 94555 m, 814 m/sec, 3445027 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 60734 m, 632 m/sec, 1988622 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 98606 m, 810 m/sec, 3599890 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 64588 m, 770 m/sec, 2136236 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 104113 m, 1101 m/sec, 3801835 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 68141 m, 710 m/sec, 2285938 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 108757 m, 928 m/sec, 3969997 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 71837 m, 739 m/sec, 2491228 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 115768 m, 1402 m/sec, 4240057 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 75888 m, 810 m/sec, 2677568 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 122843 m, 1415 m/sec, 4500537 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 79881 m, 798 m/sec, 2783363 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 126766 m, 784 m/sec, 4643011 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 84081 m, 840 m/sec, 2940108 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 132704 m, 1187 m/sec, 4857158 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 88175 m, 818 m/sec, 3034686 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 140302 m, 1519 m/sec, 5150290 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 92234 m, 811 m/sec, 3133835 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 145478 m, 1035 m/sec, 5349263 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 96320 m, 817 m/sec, 3258321 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 151864 m, 1277 m/sec, 5599068 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 99320 m, 600 m/sec, 3372708 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 155921 m, 811 m/sec, 5750686 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 103447 m, 825 m/sec, 3518189 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 162522 m, 1320 m/sec, 5979935 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 107733 m, 857 m/sec, 3652150 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 169715 m, 1438 m/sec, 6232336 t fired, . Pages in use: 31 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 111745 m, 802 m/sec, 3786660 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 175793 m, 1215 m/sec, 6452646 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 115981 m, 847 m/sec, 3973181 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 182947 m, 1430 m/sec, 6710159 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 119053 m, 614 m/sec, 4095850 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 186522 m, 715 m/sec, 6839019 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 122539 m, 697 m/sec, 4187870 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 190742 m, 844 m/sec, 6983671 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 126039 m, 700 m/sec, 4349181 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 196649 m, 1181 m/sec, 7204203 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 129418 m, 675 m/sec, 4530789 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 201648 m, 999 m/sec, 7383669 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 133032 m, 722 m/sec, 4707784 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 208112 m, 1292 m/sec, 7617640 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 138222 m, 1038 m/sec, 4907818 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 216672 m, 1712 m/sec, 7935039 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 142897 m, 935 m/sec, 5074574 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 226038 m, 1873 m/sec, 8269960 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 147019 m, 824 m/sec, 5295528 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 234522 m, 1696 m/sec, 8577290 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 150171 m, 630 m/sec, 5439268 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 239696 m, 1034 m/sec, 8764969 t fired, . Pages in use: 32 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 153240 m, 613 m/sec, 5597754 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 245581 m, 1177 m/sec, 8981921 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 155857 m, 523 m/sec, 5703590 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 250378 m, 959 m/sec, 9154374 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 159245 m, 677 m/sec, 5887014 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 256772 m, 1278 m/sec, 9393135 t fired, . Pages in use: 33 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 162824 m, 715 m/sec, 6072213 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 263449 m, 1335 m/sec, 9640082 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 165945 m, 624 m/sec, 6182776 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 269357 m, 1181 m/sec, 9855323 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 170630 m, 937 m/sec, 6429794 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 278112 m, 1751 m/sec, 10177748 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 175015 m, 877 m/sec, 6639976 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 286555 m, 1688 m/sec, 10488808 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 178003 m, 597 m/sec, 6782446 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 291734 m, 1035 m/sec, 10677125 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 180314 m, 462 m/sec, 6929214 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 295531 m, 759 m/sec, 10817488 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 184042 m, 745 m/sec, 7188214 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 306372 m, 2168 m/sec, 11205303 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 187940 m, 779 m/sec, 7373969 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 314379 m, 1601 m/sec, 11486465 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 190989 m, 609 m/sec, 7530537 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 320041 m, 1132 m/sec, 11682324 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 194535 m, 709 m/sec, 7700272 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 325650 m, 1121 m/sec, 11882948 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 198945 m, 882 m/sec, 7901157 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 334202 m, 1710 m/sec, 12181881 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 202826 m, 776 m/sec, 8106572 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 342387 m, 1637 m/sec, 12474172 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 207194 m, 873 m/sec, 8325746 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 351425 m, 1807 m/sec, 12803675 t fired, . Pages in use: 34 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 210977 m, 756 m/sec, 8538267 t fired, . 2/5 DLCround-PT-08a-CTLFireability-10 360105 m, 1736 m/sec, 13121654 t fired, . Pages in use: 34 16 (type EXCL) for DLCround-PT-08a-CTLFireability-10 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 215283 m, 861 m/sec, 8682582 t fired, . Pages in use: 34 16 (type EXCL) for 34 DLCround-PT-08a-CTLFireability-10 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 219067 m, 756 m/sec, 8932162 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 5279 m, -70965 m/sec, 181045 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 222109 m, 608 m/sec, 9060634 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 9005 m, 745 m/sec, 309011 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 224543 m, 486 m/sec, 9196426 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 13360 m, 871 m/sec, 465071 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 228101 m, 711 m/sec, 9351967 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 19722 m, 1272 m/sec, 691217 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 231296 m, 639 m/sec, 9478391 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 25102 m, 1076 m/sec, 883949 t fired, . Pages in use: 36 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-08a-CTLFireability-07 234072 m, 555 m/sec, 9615782 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 29451 m, 869 m/sec, 1037882 t fired, . Pages in use: 36 16 (type EXCL) for DLCround-PT-08a-CTLFireability-07 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 37584 m, 1626 m/sec, 1337559 t fired, . Pages in use: 36 16 (type EXCL) for 25 DLCround-PT-08a-CTLFireability-07 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 DLCround-PT-08a-CTLFireability-07 -- 1/5 DLCround-PT-08a-CTLFireability-10 44019 m, 1287 m/sec, 1569233 t fired, . Pages in use: 37 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 4042 m, -46006 m/sec, 62232 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 48418 m, 879 m/sec, 1721164 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 7150 m, 621 m/sec, 157793 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 51379 m, 592 m/sec, 1835530 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 10632 m, 696 m/sec, 236431 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 54069 m, 538 m/sec, 1935585 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 14170 m, 707 m/sec, 321564 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 56688 m, 523 m/sec, 2030971 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 17331 m, 632 m/sec, 426576 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 59530 m, 568 m/sec, 2129506 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 20842 m, 702 m/sec, 546405 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 64111 m, 916 m/sec, 2293777 t fired, . Pages in use: 38 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 24176 m, 666 m/sec, 675871 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 67600 m, 697 m/sec, 2425941 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 27127 m, 590 m/sec, 778288 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 70354 m, 550 m/sec, 2529196 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 30489 m, 672 m/sec, 896893 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 74314 m, 792 m/sec, 2680905 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 33324 m, 567 m/sec, 1026315 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 77428 m, 622 m/sec, 2796931 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 36345 m, 604 m/sec, 1148437 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 80772 m, 668 m/sec, 2917117 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 38731 m, 477 m/sec, 1275345 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 84556 m, 756 m/sec, 3057286 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 40865 m, 426 m/sec, 1402418 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 87487 m, 586 m/sec, 3169321 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 43399 m, 506 m/sec, 1514983 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 89710 m, 444 m/sec, 3260808 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 46648 m, 649 m/sec, 1608296 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 92274 m, 512 m/sec, 3357538 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 50218 m, 714 m/sec, 1681643 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 94476 m, 440 m/sec, 3442336 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 53822 m, 720 m/sec, 1759126 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 97816 m, 668 m/sec, 3571702 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 56058 m, 447 m/sec, 1859646 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 100082 m, 453 m/sec, 3654787 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 59627 m, 713 m/sec, 1954069 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 102808 m, 545 m/sec, 3752995 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 62840 m, 642 m/sec, 2051628 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 105991 m, 636 m/sec, 3868199 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 65253 m, 482 m/sec, 2184541 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 108701 m, 542 m/sec, 3967937 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 68186 m, 586 m/sec, 2288440 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 111337 m, 527 m/sec, 4069053 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 71011 m, 565 m/sec, 2443756 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 114550 m, 642 m/sec, 4193654 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 73529 m, 503 m/sec, 2576334 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 117656 m, 621 m/sec, 4310347 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 76825 m, 659 m/sec, 2721239 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 120671 m, 603 m/sec, 4421200 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 80224 m, 679 m/sec, 2790230 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 124265 m, 718 m/sec, 4553897 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 83474 m, 650 m/sec, 2922445 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 127204 m, 587 m/sec, 4658510 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 85738 m, 452 m/sec, 2980404 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 128974 m, 354 m/sec, 4722128 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 89159 m, 684 m/sec, 3056063 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 132324 m, 670 m/sec, 4842921 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 92421 m, 652 m/sec, 3137853 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 134287 m, 392 m/sec, 4920249 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 95184 m, 552 m/sec, 3237481 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 137398 m, 622 m/sec, 5044108 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 98145 m, 592 m/sec, 3324214 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 140005 m, 521 m/sec, 5139478 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 100739 m, 518 m/sec, 3416473 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 142272 m, 453 m/sec, 5224772 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 103357 m, 523 m/sec, 3515454 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 144553 m, 456 m/sec, 5312315 t fired, . Pages in use: 39 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 105966 m, 521 m/sec, 3593324 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 146454 m, 380 m/sec, 5386228 t fired, . Pages in use: 40 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 109343 m, 675 m/sec, 3709010 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 148972 m, 503 m/sec, 5485664 t fired, . Pages in use: 40 16 (type EXCL) for DLCround-PT-08a-CTLFireability-10 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 112074 m, 546 m/sec, 3798913 t fired, . Pages in use: 40 16 (type EXCL) for 34 DLCround-PT-08a-CTLFireability-10 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 131582 m, 3901 m/sec, 4646183 t fired, . 0/5 DLCround-PT-08a-CTLFireability-10 -- Pages in use: 41 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 133380 m, 359 m/sec, 4721987 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 2683 m, -29257 m/sec, 91779 t fired, . Pages in use: 42 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 135433 m, 410 m/sec, 4806590 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 5082 m, 479 m/sec, 174151 t fired, . Pages in use: 42 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 138251 m, 563 m/sec, 4908780 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 7425 m, 468 m/sec, 253624 t fired, . Pages in use: 42 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 140679 m, 485 m/sec, 4991271 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 9899 m, 494 m/sec, 340927 t fired, . Pages in use: 42 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 142956 m, 455 m/sec, 5077296 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 11967 m, 413 m/sec, 415931 t fired, . Pages in use: 42 16 (type EXCL) for DLCround-PT-08a-CTLFireability-07 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-10 14030 m, 412 m/sec, 488498 t fired, . Pages in use: 42 16 (type EXCL) for 25 DLCround-PT-08a-CTLFireability-07 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 1712 m, -28248 m/sec, 20584 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 17090 m, 612 m/sec, 598152 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 4490 m, 555 m/sec, 73209 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 19217 m, 425 m/sec, 672909 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 6978 m, 497 m/sec, 151913 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 21270 m, 410 m/sec, 744764 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 9631 m, 530 m/sec, 219975 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 23576 m, 461 m/sec, 828001 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 12494 m, 572 m/sec, 282700 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 26909 m, 666 m/sec, 948201 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 14679 m, 437 m/sec, 339161 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 28468 m, 311 m/sec, 1001220 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 16816 m, 427 m/sec, 407850 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 30082 m, 322 m/sec, 1061646 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 18854 m, 407 m/sec, 484159 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 31928 m, 369 m/sec, 1132742 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 20768 m, 382 m/sec, 543827 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 33536 m, 321 m/sec, 1192735 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 23259 m, 498 m/sec, 639267 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 35546 m, 402 m/sec, 1262499 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 25791 m, 506 m/sec, 740187 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 37736 m, 438 m/sec, 1343516 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 28188 m, 479 m/sec, 813464 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 39446 m, 342 m/sec, 1406167 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 30398 m, 442 m/sec, 893711 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 41322 m, 375 m/sec, 1473966 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 32243 m, 369 m/sec, 979262 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 43370 m, 409 m/sec, 1547107 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 34317 m, 414 m/sec, 1065469 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 45305 m, 387 m/sec, 1614472 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 36465 m, 429 m/sec, 1152682 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 47223 m, 383 m/sec, 1681481 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 38467 m, 400 m/sec, 1258810 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 49464 m, 448 m/sec, 1761895 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 40199 m, 346 m/sec, 1358179 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 51482 m, 403 m/sec, 1839273 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 42094 m, 379 m/sec, 1447205 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 53457 m, 395 m/sec, 1912491 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 43855 m, 352 m/sec, 1535997 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 55439 m, 396 m/sec, 1987790 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 46670 m, 563 m/sec, 1608722 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 57576 m, 427 m/sec, 2061335 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 49611 m, 588 m/sec, 1668728 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 59522 m, 389 m/sec, 2129060 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 52461 m, 570 m/sec, 1728904 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 61550 m, 405 m/sec, 2204210 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 55363 m, 580 m/sec, 1827317 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 64333 m, 556 m/sec, 2301197 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 57640 m, 455 m/sec, 1895547 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 66072 m, 347 m/sec, 2366302 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 59978 m, 467 m/sec, 1965123 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 67744 m, 334 m/sec, 2431993 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 62339 m, 472 m/sec, 2037586 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 69431 m, 337 m/sec, 2497043 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 64633 m, 458 m/sec, 2139769 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 71651 m, 444 m/sec, 2577298 t fired, . Pages in use: 44 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 66694 m, 412 m/sec, 2233868 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 73582 m, 386 m/sec, 2649714 t fired, . Pages in use: 45 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 68559 m, 373 m/sec, 2312025 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 75354 m, 354 m/sec, 2721021 t fired, . Pages in use: 45 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 70432 m, 374 m/sec, 2408961 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 77290 m, 387 m/sec, 2792052 t fired, . Pages in use: 45 16 (type EXCL) for DLCround-PT-08a-CTLFireability-10 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 71679 m, 249 m/sec, 2484383 t fired, . Pages in use: 45 16 (type EXCL) for 34 DLCround-PT-08a-CTLFireability-10 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 81681 m, 2000 m/sec, 2837141 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 44 m, -15449 m/sec, 693 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 82825 m, 228 m/sec, 2898370 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 1719 m, 335 m/sec, 60030 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 85068 m, 448 m/sec, 2963713 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 3829 m, 422 m/sec, 131770 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 87453 m, 477 m/sec, 3017469 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 5725 m, 379 m/sec, 196391 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 89455 m, 400 m/sec, 3062535 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 7514 m, 357 m/sec, 256628 t fired, . Pages in use: 47 16 VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/5 DLCround-PT-08a-CTLFireability-07 91101 m, 329 m/sec, 3103809 t fired, . 1/5 DLCround-PT-08a-CTLFireability-10 9039 m, 305 m/sec, 310122 t fired, . Pages in use: 47 16 (type EXCL) for DLCround-PT-08a-CTLFireability-07 (local timeout) VALUE PRODUCED BY CONJ false state space / EG CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker DISJ false DISJ EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 1 0 0 has been truncated ====== archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-08a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCround-PT-08a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393100354"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-08a.tgz
mv DLCround-PT-08a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;