About the Execution of LoLA for DLCround-PT-07a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16246.476 | 1526894.00 | 3974378.00 | 5071.60 | ?????T???TTT?TTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r061-tall-162038393100338.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCround-PT-07a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038393100338
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 792K
-rw-r--r-- 1 mcc users 14K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 139K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.1K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 83K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Mar 28 15:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 28 15:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 28 15:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 28 15:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Mar 23 08:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 23 08:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Mar 22 15:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 22 15:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 4 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 398K May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-07a-CTLFireability-00
FORMULA_NAME DLCround-PT-07a-CTLFireability-01
FORMULA_NAME DLCround-PT-07a-CTLFireability-02
FORMULA_NAME DLCround-PT-07a-CTLFireability-03
FORMULA_NAME DLCround-PT-07a-CTLFireability-04
FORMULA_NAME DLCround-PT-07a-CTLFireability-05
FORMULA_NAME DLCround-PT-07a-CTLFireability-06
FORMULA_NAME DLCround-PT-07a-CTLFireability-07
FORMULA_NAME DLCround-PT-07a-CTLFireability-08
FORMULA_NAME DLCround-PT-07a-CTLFireability-09
FORMULA_NAME DLCround-PT-07a-CTLFireability-10
FORMULA_NAME DLCround-PT-07a-CTLFireability-11
FORMULA_NAME DLCround-PT-07a-CTLFireability-12
FORMULA_NAME DLCround-PT-07a-CTLFireability-13
FORMULA_NAME DLCround-PT-07a-CTLFireability-14
FORMULA_NAME DLCround-PT-07a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1620739642497
starting LoLA
BK_INPUT DLCround-PT-07a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCround-PT-07a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620741169391
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 26 (type EXCL) for 25 DLCround-PT-07a-CTLFireability-07
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 1 0 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 1 0 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 1 0 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 1 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 2/198 1/32 DLCround-PT-07a-CTLFireability-07 7459 m, 1491 m/sec, 416352 t fired, .
Time elapsed: 21 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 7/210 1/32 DLCround-PT-07a-CTLFireability-07 42599 m, 7028 m/sec, 2335887 t fired, .
Time elapsed: 26 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 12/210 1/32 DLCround-PT-07a-CTLFireability-07 76632 m, 6806 m/sec, 4284888 t fired, .
Time elapsed: 31 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 17/210 1/32 DLCround-PT-07a-CTLFireability-07 108032 m, 6280 m/sec, 6077907 t fired, .
Time elapsed: 36 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 22/210 1/32 DLCround-PT-07a-CTLFireability-07 143369 m, 7067 m/sec, 8093980 t fired, .
Time elapsed: 41 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 27/210 1/32 DLCround-PT-07a-CTLFireability-07 180848 m, 7495 m/sec, 10178392 t fired, .
Time elapsed: 46 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 32/210 1/32 DLCround-PT-07a-CTLFireability-07 219580 m, 7746 m/sec, 12315046 t fired, .
Time elapsed: 51 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 37/210 2/32 DLCround-PT-07a-CTLFireability-07 251341 m, 6352 m/sec, 14074983 t fired, .
Time elapsed: 56 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 42/210 2/32 DLCround-PT-07a-CTLFireability-07 286716 m, 7075 m/sec, 16034437 t fired, .
Time elapsed: 61 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 47/210 2/32 DLCround-PT-07a-CTLFireability-07 319014 m, 6459 m/sec, 17833584 t fired, .
Time elapsed: 66 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 52/210 2/32 DLCround-PT-07a-CTLFireability-07 355764 m, 7350 m/sec, 19906164 t fired, .
Time elapsed: 71 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 57/210 2/32 DLCround-PT-07a-CTLFireability-07 390085 m, 6864 m/sec, 21813056 t fired, .
Time elapsed: 76 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 62/210 2/32 DLCround-PT-07a-CTLFireability-07 424437 m, 6870 m/sec, 23764112 t fired, .
Time elapsed: 81 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 67/210 2/32 DLCround-PT-07a-CTLFireability-07 458880 m, 6888 m/sec, 25646613 t fired, .
Time elapsed: 86 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 72/210 3/32 DLCround-PT-07a-CTLFireability-07 492289 m, 6681 m/sec, 27583913 t fired, .
Time elapsed: 91 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 77/210 3/32 DLCround-PT-07a-CTLFireability-07 530932 m, 7728 m/sec, 29737157 t fired, .
Time elapsed: 96 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 82/210 3/32 DLCround-PT-07a-CTLFireability-07 565696 m, 6952 m/sec, 31618266 t fired, .
Time elapsed: 101 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 87/210 3/32 DLCround-PT-07a-CTLFireability-07 596441 m, 6149 m/sec, 33326612 t fired, .
Time elapsed: 106 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 92/210 3/32 DLCround-PT-07a-CTLFireability-07 630481 m, 6808 m/sec, 35193510 t fired, .
Time elapsed: 111 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 97/210 3/32 DLCround-PT-07a-CTLFireability-07 659206 m, 5745 m/sec, 36821702 t fired, .
Time elapsed: 116 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 102/210 3/32 DLCround-PT-07a-CTLFireability-07 697760 m, 7710 m/sec, 38968442 t fired, .
Time elapsed: 121 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 107/210 3/32 DLCround-PT-07a-CTLFireability-07 729909 m, 6429 m/sec, 40747913 t fired, .
Time elapsed: 126 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 112/210 4/32 DLCround-PT-07a-CTLFireability-07 761239 m, 6266 m/sec, 42472996 t fired, .
Time elapsed: 131 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 117/210 4/32 DLCround-PT-07a-CTLFireability-07 794237 m, 6599 m/sec, 44381990 t fired, .
Time elapsed: 136 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 122/210 4/32 DLCround-PT-07a-CTLFireability-07 825707 m, 6294 m/sec, 46102655 t fired, .
Time elapsed: 141 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 127/210 4/32 DLCround-PT-07a-CTLFireability-07 854960 m, 5850 m/sec, 47766812 t fired, .
Time elapsed: 146 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 132/210 4/32 DLCround-PT-07a-CTLFireability-07 886764 m, 6360 m/sec, 49613605 t fired, .
Time elapsed: 151 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 137/210 4/32 DLCround-PT-07a-CTLFireability-07 918996 m, 6446 m/sec, 51355241 t fired, .
Time elapsed: 156 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 142/210 4/32 DLCround-PT-07a-CTLFireability-07 950346 m, 6270 m/sec, 53106587 t fired, .
Time elapsed: 161 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 147/210 5/32 DLCround-PT-07a-CTLFireability-07 986095 m, 7149 m/sec, 55059273 t fired, .
Time elapsed: 166 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 152/210 5/32 DLCround-PT-07a-CTLFireability-07 1018675 m, 6516 m/sec, 56852869 t fired, .
Time elapsed: 171 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 157/210 5/32 DLCround-PT-07a-CTLFireability-07 1048517 m, 5968 m/sec, 58518725 t fired, .
Time elapsed: 176 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 162/210 5/32 DLCround-PT-07a-CTLFireability-07 1081645 m, 6625 m/sec, 60414849 t fired, .
Time elapsed: 181 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 167/210 5/32 DLCround-PT-07a-CTLFireability-07 1115043 m, 6679 m/sec, 62352814 t fired, .
Time elapsed: 186 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 172/210 5/32 DLCround-PT-07a-CTLFireability-07 1145825 m, 6156 m/sec, 64093132 t fired, .
Time elapsed: 191 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 177/210 5/32 DLCround-PT-07a-CTLFireability-07 1178853 m, 6605 m/sec, 66013028 t fired, .
Time elapsed: 196 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 182/210 5/32 DLCround-PT-07a-CTLFireability-07 1210996 m, 6428 m/sec, 67859656 t fired, .
Time elapsed: 201 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 187/210 6/32 DLCround-PT-07a-CTLFireability-07 1243882 m, 6577 m/sec, 69881607 t fired, .
Time elapsed: 206 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 192/210 6/32 DLCround-PT-07a-CTLFireability-07 1275542 m, 6332 m/sec, 71626294 t fired, .
Time elapsed: 211 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 197/210 6/32 DLCround-PT-07a-CTLFireability-07 1308883 m, 6668 m/sec, 73491982 t fired, .
Time elapsed: 216 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 202/210 6/32 DLCround-PT-07a-CTLFireability-07 1337342 m, 5691 m/sec, 75086016 t fired, .
Time elapsed: 221 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 207/210 6/32 DLCround-PT-07a-CTLFireability-07 1365205 m, 5572 m/sec, 76674212 t fired, .
Time elapsed: 226 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 26 (type EXCL) for DLCround-PT-07a-CTLFireability-07 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 1 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 231 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 50 (type EXCL) for 49 DLCround-PT-07a-CTLFireability-15
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 26 (type EXCL) for 25 DLCround-PT-07a-CTLFireability-07
lola: time limit : 3369 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type EXCL) for DLCround-PT-07a-CTLFireability-15
lola: result : false
lola: markings : 2
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/210 1/5 DLCround-PT-07a-CTLFireability-07 36254 m, -265790 m/sec, 1979035 t fired, .
Time elapsed: 236 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/210 1/5 DLCround-PT-07a-CTLFireability-07 67130 m, 6175 m/sec, 3753340 t fired, .
Time elapsed: 241 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 15/210 1/5 DLCround-PT-07a-CTLFireability-07 104447 m, 7463 m/sec, 5869880 t fired, .
Time elapsed: 246 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 20/210 1/5 DLCround-PT-07a-CTLFireability-07 137142 m, 6539 m/sec, 7730111 t fired, .
Time elapsed: 251 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 25/210 1/5 DLCround-PT-07a-CTLFireability-07 169782 m, 6528 m/sec, 9554471 t fired, .
Time elapsed: 256 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 30/210 1/5 DLCround-PT-07a-CTLFireability-07 205575 m, 7158 m/sec, 11541205 t fired, .
Time elapsed: 261 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 35/210 1/5 DLCround-PT-07a-CTLFireability-07 243507 m, 7586 m/sec, 13679343 t fired, .
Time elapsed: 266 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 40/210 2/5 DLCround-PT-07a-CTLFireability-07 277444 m, 6787 m/sec, 15522610 t fired, .
Time elapsed: 271 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 45/210 2/5 DLCround-PT-07a-CTLFireability-07 310656 m, 6642 m/sec, 17358881 t fired, .
Time elapsed: 276 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 50/210 2/5 DLCround-PT-07a-CTLFireability-07 344044 m, 6677 m/sec, 19263121 t fired, .
Time elapsed: 281 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 55/210 2/5 DLCround-PT-07a-CTLFireability-07 377530 m, 6697 m/sec, 21098989 t fired, .
Time elapsed: 286 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 60/210 2/5 DLCround-PT-07a-CTLFireability-07 410654 m, 6624 m/sec, 22978353 t fired, .
Time elapsed: 291 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 65/210 2/5 DLCround-PT-07a-CTLFireability-07 441302 m, 6129 m/sec, 24671541 t fired, .
Time elapsed: 296 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 70/210 2/5 DLCround-PT-07a-CTLFireability-07 469726 m, 5684 m/sec, 26296882 t fired, .
Time elapsed: 301 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 75/210 3/5 DLCround-PT-07a-CTLFireability-07 502255 m, 6505 m/sec, 28141290 t fired, .
Time elapsed: 306 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 80/210 3/5 DLCround-PT-07a-CTLFireability-07 536783 m, 6905 m/sec, 30052244 t fired, .
Time elapsed: 311 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 85/210 3/5 DLCround-PT-07a-CTLFireability-07 572017 m, 7046 m/sec, 31948347 t fired, .
Time elapsed: 316 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 90/210 3/5 DLCround-PT-07a-CTLFireability-07 611801 m, 7956 m/sec, 34182307 t fired, .
Time elapsed: 321 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 95/210 3/5 DLCround-PT-07a-CTLFireability-07 643519 m, 6343 m/sec, 35936345 t fired, .
Time elapsed: 326 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 100/210 3/5 DLCround-PT-07a-CTLFireability-07 670146 m, 5325 m/sec, 37428195 t fired, .
Time elapsed: 331 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 105/210 3/5 DLCround-PT-07a-CTLFireability-07 702019 m, 6374 m/sec, 39201947 t fired, .
Time elapsed: 336 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 110/210 4/5 DLCround-PT-07a-CTLFireability-07 737169 m, 7030 m/sec, 41125211 t fired, .
Time elapsed: 341 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 115/210 4/5 DLCround-PT-07a-CTLFireability-07 769617 m, 6489 m/sec, 42948963 t fired, .
Time elapsed: 346 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 120/210 4/5 DLCround-PT-07a-CTLFireability-07 801879 m, 6452 m/sec, 44814406 t fired, .
Time elapsed: 351 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 125/210 4/5 DLCround-PT-07a-CTLFireability-07 836216 m, 6867 m/sec, 46676814 t fired, .
Time elapsed: 356 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 130/210 4/5 DLCround-PT-07a-CTLFireability-07 866542 m, 6065 m/sec, 48441986 t fired, .
Time elapsed: 361 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 135/210 4/5 DLCround-PT-07a-CTLFireability-07 901550 m, 7001 m/sec, 50421922 t fired, .
Time elapsed: 366 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 140/210 4/5 DLCround-PT-07a-CTLFireability-07 932158 m, 6121 m/sec, 52078706 t fired, .
Time elapsed: 371 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 145/210 4/5 DLCround-PT-07a-CTLFireability-07 961123 m, 5793 m/sec, 53722015 t fired, .
Time elapsed: 376 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 150/210 5/5 DLCround-PT-07a-CTLFireability-07 993325 m, 6440 m/sec, 55462910 t fired, .
Time elapsed: 381 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 155/210 5/5 DLCround-PT-07a-CTLFireability-07 1026106 m, 6556 m/sec, 57280312 t fired, .
Time elapsed: 386 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 160/210 5/5 DLCround-PT-07a-CTLFireability-07 1058518 m, 6482 m/sec, 59079429 t fired, .
Time elapsed: 391 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 165/210 5/5 DLCround-PT-07a-CTLFireability-07 1088147 m, 5925 m/sec, 60806459 t fired, .
Time elapsed: 396 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 170/210 5/5 DLCround-PT-07a-CTLFireability-07 1117697 m, 5910 m/sec, 62518844 t fired, .
Time elapsed: 401 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 175/210 5/5 DLCround-PT-07a-CTLFireability-07 1151277 m, 6716 m/sec, 64396722 t fired, .
Time elapsed: 406 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 180/210 5/5 DLCround-PT-07a-CTLFireability-07 1182497 m, 6244 m/sec, 66224572 t fired, .
Time elapsed: 411 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 185/210 5/5 DLCround-PT-07a-CTLFireability-07 1210891 m, 5678 m/sec, 67854891 t fired, .
Time elapsed: 416 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 26 (type EXCL) for DLCround-PT-07a-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 421 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 47 (type EXCL) for 46 DLCround-PT-07a-CTLFireability-14
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for DLCround-PT-07a-CTLFireability-14
lola: result : true
lola: markings : 4
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 DLCround-PT-07a-CTLFireability-13
lola: time limit : 227 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for DLCround-PT-07a-CTLFireability-13
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-07a-CTLFireability-12
lola: time limit : 244 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/244 1/32 DLCround-PT-07a-CTLFireability-12 69813 m, 13962 m/sec, 1456162 t fired, .
Time elapsed: 426 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/244 1/32 DLCround-PT-07a-CTLFireability-12 144898 m, 15017 m/sec, 3063254 t fired, .
Time elapsed: 431 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/244 1/32 DLCround-PT-07a-CTLFireability-12 226103 m, 16241 m/sec, 4816195 t fired, .
Time elapsed: 436 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/244 2/32 DLCround-PT-07a-CTLFireability-12 275163 m, 9812 m/sec, 6342290 t fired, .
Time elapsed: 441 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/244 2/32 DLCround-PT-07a-CTLFireability-12 360608 m, 17089 m/sec, 8018210 t fired, .
Time elapsed: 446 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/244 2/32 DLCround-PT-07a-CTLFireability-12 438141 m, 15506 m/sec, 9526600 t fired, .
Time elapsed: 451 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 35/244 2/32 DLCround-PT-07a-CTLFireability-12 471303 m, 6632 m/sec, 11228673 t fired, .
Time elapsed: 456 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 40/244 3/32 DLCround-PT-07a-CTLFireability-12 494994 m, 4738 m/sec, 13078091 t fired, .
Time elapsed: 461 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 45/244 3/32 DLCround-PT-07a-CTLFireability-12 525205 m, 6042 m/sec, 14587322 t fired, .
Time elapsed: 466 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 50/244 3/32 DLCround-PT-07a-CTLFireability-12 586996 m, 12358 m/sec, 16265418 t fired, .
Time elapsed: 471 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 55/244 3/32 DLCround-PT-07a-CTLFireability-12 642696 m, 11140 m/sec, 17840693 t fired, .
Time elapsed: 476 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 60/244 3/32 DLCround-PT-07a-CTLFireability-12 699769 m, 11414 m/sec, 19290212 t fired, .
Time elapsed: 481 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 65/244 4/32 DLCround-PT-07a-CTLFireability-12 766866 m, 13419 m/sec, 20971596 t fired, .
Time elapsed: 486 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 70/244 4/32 DLCround-PT-07a-CTLFireability-12 840495 m, 14725 m/sec, 22563699 t fired, .
Time elapsed: 491 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 75/244 4/32 DLCround-PT-07a-CTLFireability-12 882272 m, 8355 m/sec, 24201381 t fired, .
Time elapsed: 496 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 80/244 4/32 DLCround-PT-07a-CTLFireability-12 948141 m, 13173 m/sec, 25871409 t fired, .
Time elapsed: 501 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 85/244 5/32 DLCround-PT-07a-CTLFireability-12 1019938 m, 14359 m/sec, 27529803 t fired, .
Time elapsed: 506 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 90/244 5/32 DLCround-PT-07a-CTLFireability-12 1120812 m, 20174 m/sec, 29487567 t fired, .
Time elapsed: 511 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 95/244 5/32 DLCround-PT-07a-CTLFireability-12 1208702 m, 17578 m/sec, 31220960 t fired, .
Time elapsed: 516 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 100/244 6/32 DLCround-PT-07a-CTLFireability-12 1270175 m, 12294 m/sec, 32572238 t fired, .
Time elapsed: 521 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 105/244 6/32 DLCround-PT-07a-CTLFireability-12 1289411 m, 3847 m/sec, 34354284 t fired, .
Time elapsed: 526 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 110/244 6/32 DLCround-PT-07a-CTLFireability-12 1309715 m, 4060 m/sec, 36024051 t fired, .
Time elapsed: 531 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 115/244 6/32 DLCround-PT-07a-CTLFireability-12 1346561 m, 7369 m/sec, 37723125 t fired, .
Time elapsed: 536 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 120/244 6/32 DLCround-PT-07a-CTLFireability-12 1384926 m, 7673 m/sec, 39153984 t fired, .
Time elapsed: 541 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 125/244 6/32 DLCround-PT-07a-CTLFireability-12 1437030 m, 10420 m/sec, 40630664 t fired, .
Time elapsed: 546 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 130/244 7/32 DLCround-PT-07a-CTLFireability-12 1499331 m, 12460 m/sec, 42282899 t fired, .
Time elapsed: 551 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 135/244 7/32 DLCround-PT-07a-CTLFireability-12 1571159 m, 14365 m/sec, 43969756 t fired, .
Time elapsed: 556 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 140/244 7/32 DLCround-PT-07a-CTLFireability-12 1620752 m, 9918 m/sec, 45496841 t fired, .
Time elapsed: 561 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 145/244 7/32 DLCround-PT-07a-CTLFireability-12 1688016 m, 13452 m/sec, 47189139 t fired, .
Time elapsed: 566 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 150/244 8/32 DLCround-PT-07a-CTLFireability-12 1737270 m, 9850 m/sec, 48476499 t fired, .
Time elapsed: 571 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 155/244 8/32 DLCround-PT-07a-CTLFireability-12 1820721 m, 16690 m/sec, 50090873 t fired, .
Time elapsed: 576 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 160/244 8/32 DLCround-PT-07a-CTLFireability-12 1852762 m, 6408 m/sec, 51629964 t fired, .
Time elapsed: 581 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 165/244 8/32 DLCround-PT-07a-CTLFireability-12 1894158 m, 8279 m/sec, 53217509 t fired, .
Time elapsed: 586 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 170/244 9/32 DLCround-PT-07a-CTLFireability-12 1964615 m, 14091 m/sec, 54948283 t fired, .
Time elapsed: 591 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 175/244 9/32 DLCround-PT-07a-CTLFireability-12 2029575 m, 12992 m/sec, 56456022 t fired, .
Time elapsed: 596 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 180/244 9/32 DLCround-PT-07a-CTLFireability-12 2093356 m, 12756 m/sec, 57926549 t fired, .
Time elapsed: 601 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 185/244 9/32 DLCround-PT-07a-CTLFireability-12 2154084 m, 12145 m/sec, 59393944 t fired, .
Time elapsed: 606 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 190/244 10/32 DLCround-PT-07a-CTLFireability-12 2217162 m, 12615 m/sec, 61140783 t fired, .
Time elapsed: 611 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 195/244 10/32 DLCround-PT-07a-CTLFireability-12 2281770 m, 12921 m/sec, 62643998 t fired, .
Time elapsed: 616 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 200/244 10/32 DLCround-PT-07a-CTLFireability-12 2328112 m, 9268 m/sec, 64276864 t fired, .
Time elapsed: 621 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 205/244 10/32 DLCround-PT-07a-CTLFireability-12 2377534 m, 9884 m/sec, 65736340 t fired, .
Time elapsed: 626 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 210/244 11/32 DLCround-PT-07a-CTLFireability-12 2425570 m, 9607 m/sec, 67060406 t fired, .
Time elapsed: 631 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 215/244 11/32 DLCround-PT-07a-CTLFireability-12 2484047 m, 11695 m/sec, 68526956 t fired, .
Time elapsed: 636 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 220/244 11/32 DLCround-PT-07a-CTLFireability-12 2535727 m, 10336 m/sec, 69805128 t fired, .
Time elapsed: 641 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 225/244 11/32 DLCround-PT-07a-CTLFireability-12 2600297 m, 12914 m/sec, 71392197 t fired, .
Time elapsed: 646 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 230/244 11/32 DLCround-PT-07a-CTLFireability-12 2664290 m, 12798 m/sec, 72914162 t fired, .
Time elapsed: 651 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 235/244 12/32 DLCround-PT-07a-CTLFireability-12 2733856 m, 13913 m/sec, 74549356 t fired, .
Time elapsed: 656 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 240/244 12/32 DLCround-PT-07a-CTLFireability-12 2792010 m, 11630 m/sec, 75992427 t fired, .
Time elapsed: 661 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 41 (type EXCL) for DLCround-PT-07a-CTLFireability-12 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 1 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 666 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 38 (type EXCL) for 37 DLCround-PT-07a-CTLFireability-11
lola: time limit : 244 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-07a-CTLFireability-12
lola: time limit : 2934 sec
lola: memory limit: 5 pages
lola: FINISHED task # 38 (type EXCL) for DLCround-PT-07a-CTLFireability-11
lola: result : true
lola: markings : 12
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/244 1/5 DLCround-PT-07a-CTLFireability-12 73631 m, -543675 m/sec, 1539599 t fired, .
Time elapsed: 671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/244 1/5 DLCround-PT-07a-CTLFireability-12 141538 m, 13581 m/sec, 2984658 t fired, .
Time elapsed: 676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/244 1/5 DLCround-PT-07a-CTLFireability-12 213047 m, 14301 m/sec, 4468429 t fired, .
Time elapsed: 681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/244 2/5 DLCround-PT-07a-CTLFireability-12 247235 m, 6837 m/sec, 5808337 t fired, .
Time elapsed: 686 secs. Pages in use: 33
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/244 2/5 DLCround-PT-07a-CTLFireability-12 322543 m, 15061 m/sec, 7263810 t fired, .
Time elapsed: 691 secs. Pages in use: 34
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/244 2/5 DLCround-PT-07a-CTLFireability-12 397642 m, 15019 m/sec, 8715553 t fired, .
Time elapsed: 696 secs. Pages in use: 34
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 35/244 2/5 DLCround-PT-07a-CTLFireability-12 458760 m, 12223 m/sec, 10115655 t fired, .
Time elapsed: 701 secs. Pages in use: 34
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 40/244 2/5 DLCround-PT-07a-CTLFireability-12 474594 m, 3166 m/sec, 11522951 t fired, .
Time elapsed: 706 secs. Pages in use: 35
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 45/244 3/5 DLCround-PT-07a-CTLFireability-12 495631 m, 4207 m/sec, 13132747 t fired, .
Time elapsed: 711 secs. Pages in use: 36
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 50/244 3/5 DLCround-PT-07a-CTLFireability-12 531355 m, 7144 m/sec, 14814670 t fired, .
Time elapsed: 716 secs. Pages in use: 37
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 55/244 3/5 DLCround-PT-07a-CTLFireability-12 577859 m, 9300 m/sec, 16019624 t fired, .
Time elapsed: 721 secs. Pages in use: 37
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 60/244 3/5 DLCround-PT-07a-CTLFireability-12 628410 m, 10110 m/sec, 17425238 t fired, .
Time elapsed: 726 secs. Pages in use: 37
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 65/244 3/5 DLCround-PT-07a-CTLFireability-12 686133 m, 11544 m/sec, 18955381 t fired, .
Time elapsed: 731 secs. Pages in use: 37
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 70/244 4/5 DLCround-PT-07a-CTLFireability-12 743626 m, 11498 m/sec, 20371894 t fired, .
Time elapsed: 736 secs. Pages in use: 39
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 75/244 4/5 DLCround-PT-07a-CTLFireability-12 795884 m, 10451 m/sec, 21677003 t fired, .
Time elapsed: 741 secs. Pages in use: 39
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 80/244 4/5 DLCround-PT-07a-CTLFireability-12 848566 m, 10536 m/sec, 23157502 t fired, .
Time elapsed: 746 secs. Pages in use: 39
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 85/244 4/5 DLCround-PT-07a-CTLFireability-12 899508 m, 10188 m/sec, 24672020 t fired, .
Time elapsed: 751 secs. Pages in use: 40
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 90/244 4/5 DLCround-PT-07a-CTLFireability-12 950068 m, 10112 m/sec, 25919112 t fired, .
Time elapsed: 756 secs. Pages in use: 41
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 95/244 5/5 DLCround-PT-07a-CTLFireability-12 1006846 m, 11355 m/sec, 27265135 t fired, .
Time elapsed: 761 secs. Pages in use: 42
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 100/244 5/5 DLCround-PT-07a-CTLFireability-12 1087693 m, 16169 m/sec, 28825220 t fired, .
Time elapsed: 766 secs. Pages in use: 42
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 105/244 5/5 DLCround-PT-07a-CTLFireability-12 1163114 m, 15084 m/sec, 30347603 t fired, .
Time elapsed: 771 secs. Pages in use: 42
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 41 (type EXCL) for DLCround-PT-07a-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 776 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 35 (type EXCL) for 34 DLCround-PT-07a-CTLFireability-10
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for DLCround-PT-07a-CTLFireability-10
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 DLCround-PT-07a-CTLFireability-09
lola: time limit : 282 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/282 1/32 DLCround-PT-07a-CTLFireability-09 35797 m, 7159 m/sec, 1389469 t fired, .
Time elapsed: 781 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/282 1/32 DLCround-PT-07a-CTLFireability-09 69554 m, 6751 m/sec, 2731049 t fired, .
Time elapsed: 786 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/282 1/32 DLCround-PT-07a-CTLFireability-09 106810 m, 7451 m/sec, 4093981 t fired, .
Time elapsed: 791 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/282 1/32 DLCround-PT-07a-CTLFireability-09 140558 m, 6749 m/sec, 5297569 t fired, .
Time elapsed: 796 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/282 1/32 DLCround-PT-07a-CTLFireability-09 177159 m, 7320 m/sec, 6596953 t fired, .
Time elapsed: 801 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 30/282 1/32 DLCround-PT-07a-CTLFireability-09 209650 m, 6498 m/sec, 7774916 t fired, .
Time elapsed: 806 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 35/282 1/32 DLCround-PT-07a-CTLFireability-09 240442 m, 6158 m/sec, 8998778 t fired, .
Time elapsed: 811 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 40/282 2/32 DLCround-PT-07a-CTLFireability-09 274638 m, 6839 m/sec, 10371872 t fired, .
Time elapsed: 816 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 45/282 2/32 DLCround-PT-07a-CTLFireability-09 303427 m, 5757 m/sec, 11526101 t fired, .
Time elapsed: 821 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 50/282 2/32 DLCround-PT-07a-CTLFireability-09 330788 m, 5472 m/sec, 12637894 t fired, .
Time elapsed: 826 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 32 (type EXCL) for DLCround-PT-07a-CTLFireability-09
lola: result : true
lola: markings : 333190
lola: fired transitions : 12734874
lola: time used : 52.000000
lola: memory pages used : 2
lola: LAUNCH task # 29 (type EXCL) for 28 DLCround-PT-07a-CTLFireability-08
lola: time limit : 308 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 3/308 1/32 DLCround-PT-07a-CTLFireability-08 44326 m, 8865 m/sec, 1342662 t fired, .
Time elapsed: 831 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 8/308 1/32 DLCround-PT-07a-CTLFireability-08 95354 m, 10205 m/sec, 2931054 t fired, .
Time elapsed: 836 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 13/308 1/32 DLCround-PT-07a-CTLFireability-08 141338 m, 9196 m/sec, 4319089 t fired, .
Time elapsed: 841 secs. Pages in use: 43
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 18/308 1/32 DLCround-PT-07a-CTLFireability-08 198102 m, 11352 m/sec, 6059711 t fired, .
Time elapsed: 846 secs. Pages in use: 44
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 23/308 2/32 DLCround-PT-07a-CTLFireability-08 254426 m, 11264 m/sec, 7773245 t fired, .
Time elapsed: 851 secs. Pages in use: 45
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 28/308 2/32 DLCround-PT-07a-CTLFireability-08 309229 m, 10960 m/sec, 9396498 t fired, .
Time elapsed: 856 secs. Pages in use: 45
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 33/308 2/32 DLCround-PT-07a-CTLFireability-08 358495 m, 9853 m/sec, 10834265 t fired, .
Time elapsed: 861 secs. Pages in use: 45
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 38/308 2/32 DLCround-PT-07a-CTLFireability-08 421911 m, 12683 m/sec, 12769162 t fired, .
Time elapsed: 866 secs. Pages in use: 46
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 43/308 2/32 DLCround-PT-07a-CTLFireability-08 471747 m, 9967 m/sec, 14312165 t fired, .
Time elapsed: 871 secs. Pages in use: 46
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 48/308 3/32 DLCround-PT-07a-CTLFireability-08 528072 m, 11265 m/sec, 16001853 t fired, .
Time elapsed: 876 secs. Pages in use: 47
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 53/308 3/32 DLCround-PT-07a-CTLFireability-08 572292 m, 8844 m/sec, 17336248 t fired, .
Time elapsed: 881 secs. Pages in use: 47
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 58/308 3/32 DLCround-PT-07a-CTLFireability-08 623174 m, 10176 m/sec, 18804802 t fired, .
Time elapsed: 886 secs. Pages in use: 49
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 63/308 3/32 DLCround-PT-07a-CTLFireability-08 673977 m, 10160 m/sec, 20307617 t fired, .
Time elapsed: 891 secs. Pages in use: 49
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 68/308 4/32 DLCround-PT-07a-CTLFireability-08 726982 m, 10601 m/sec, 21803524 t fired, .
Time elapsed: 896 secs. Pages in use: 50
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 73/308 4/32 DLCround-PT-07a-CTLFireability-08 777622 m, 10128 m/sec, 23258337 t fired, .
Time elapsed: 901 secs. Pages in use: 50
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 78/308 4/32 DLCround-PT-07a-CTLFireability-08 829415 m, 10358 m/sec, 24780169 t fired, .
Time elapsed: 906 secs. Pages in use: 51
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 83/308 4/32 DLCround-PT-07a-CTLFireability-08 878821 m, 9881 m/sec, 26201126 t fired, .
Time elapsed: 911 secs. Pages in use: 51
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 89/308 4/32 DLCround-PT-07a-CTLFireability-08 933423 m, 10920 m/sec, 27658445 t fired, .
Time elapsed: 917 secs. Pages in use: 51
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 94/308 5/32 DLCround-PT-07a-CTLFireability-08 986513 m, 10618 m/sec, 29237675 t fired, .
Time elapsed: 922 secs. Pages in use: 52
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 99/308 5/32 DLCround-PT-07a-CTLFireability-08 1029246 m, 8546 m/sec, 30552765 t fired, .
Time elapsed: 927 secs. Pages in use: 54
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 104/308 5/32 DLCround-PT-07a-CTLFireability-08 1079354 m, 10021 m/sec, 31977636 t fired, .
Time elapsed: 932 secs. Pages in use: 54
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 109/308 5/32 DLCround-PT-07a-CTLFireability-08 1123002 m, 8729 m/sec, 33279544 t fired, .
Time elapsed: 937 secs. Pages in use: 54
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 114/308 5/32 DLCround-PT-07a-CTLFireability-08 1171508 m, 9701 m/sec, 34647057 t fired, .
Time elapsed: 942 secs. Pages in use: 54
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 119/308 6/32 DLCround-PT-07a-CTLFireability-08 1219009 m, 9500 m/sec, 36053518 t fired, .
Time elapsed: 947 secs. Pages in use: 55
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 124/308 6/32 DLCround-PT-07a-CTLFireability-08 1264124 m, 9023 m/sec, 37375328 t fired, .
Time elapsed: 952 secs. Pages in use: 56
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 129/308 6/32 DLCround-PT-07a-CTLFireability-08 1310492 m, 9273 m/sec, 38674427 t fired, .
Time elapsed: 957 secs. Pages in use: 56
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 134/308 6/32 DLCround-PT-07a-CTLFireability-08 1355802 m, 9062 m/sec, 40033360 t fired, .
Time elapsed: 962 secs. Pages in use: 56
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 139/308 6/32 DLCround-PT-07a-CTLFireability-08 1407900 m, 10419 m/sec, 41483641 t fired, .
Time elapsed: 967 secs. Pages in use: 57
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 144/308 7/32 DLCround-PT-07a-CTLFireability-08 1462666 m, 10953 m/sec, 43065195 t fired, .
Time elapsed: 972 secs. Pages in use: 59
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 149/308 7/32 DLCround-PT-07a-CTLFireability-08 1510567 m, 9580 m/sec, 44527939 t fired, .
Time elapsed: 977 secs. Pages in use: 59
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 154/308 7/32 DLCround-PT-07a-CTLFireability-08 1560936 m, 10073 m/sec, 46058679 t fired, .
Time elapsed: 982 secs. Pages in use: 59
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 159/308 7/32 DLCround-PT-07a-CTLFireability-08 1606532 m, 9119 m/sec, 47371835 t fired, .
Time elapsed: 987 secs. Pages in use: 59
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 164/308 7/32 DLCround-PT-07a-CTLFireability-08 1655349 m, 9763 m/sec, 48731279 t fired, .
Time elapsed: 992 secs. Pages in use: 60
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 169/308 8/32 DLCround-PT-07a-CTLFireability-08 1708806 m, 10691 m/sec, 50284164 t fired, .
Time elapsed: 997 secs. Pages in use: 61
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 174/308 8/32 DLCround-PT-07a-CTLFireability-08 1755926 m, 9424 m/sec, 51686312 t fired, .
Time elapsed: 1002 secs. Pages in use: 61
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 179/308 8/32 DLCround-PT-07a-CTLFireability-08 1812043 m, 11223 m/sec, 53289766 t fired, .
Time elapsed: 1007 secs. Pages in use: 61
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 184/308 8/32 DLCround-PT-07a-CTLFireability-08 1854242 m, 8439 m/sec, 54436384 t fired, .
Time elapsed: 1012 secs. Pages in use: 63
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 189/308 8/32 DLCround-PT-07a-CTLFireability-08 1896419 m, 8435 m/sec, 55705416 t fired, .
Time elapsed: 1017 secs. Pages in use: 63
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 194/308 9/32 DLCround-PT-07a-CTLFireability-08 1942445 m, 9205 m/sec, 57036525 t fired, .
Time elapsed: 1022 secs. Pages in use: 64
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 199/308 9/32 DLCround-PT-07a-CTLFireability-08 1991231 m, 9757 m/sec, 58530145 t fired, .
Time elapsed: 1027 secs. Pages in use: 64
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 204/308 9/32 DLCround-PT-07a-CTLFireability-08 2038318 m, 9417 m/sec, 59833090 t fired, .
Time elapsed: 1032 secs. Pages in use: 64
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 209/308 9/32 DLCround-PT-07a-CTLFireability-08 2083276 m, 8991 m/sec, 61170534 t fired, .
Time elapsed: 1037 secs. Pages in use: 65
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 214/308 9/32 DLCround-PT-07a-CTLFireability-08 2131607 m, 9666 m/sec, 62605194 t fired, .
Time elapsed: 1042 secs. Pages in use: 65
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 219/308 10/32 DLCround-PT-07a-CTLFireability-08 2178564 m, 9391 m/sec, 64073035 t fired, .
Time elapsed: 1047 secs. Pages in use: 66
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 224/308 10/32 DLCround-PT-07a-CTLFireability-08 2229047 m, 10096 m/sec, 65628939 t fired, .
Time elapsed: 1052 secs. Pages in use: 66
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 229/308 10/32 DLCround-PT-07a-CTLFireability-08 2279054 m, 10001 m/sec, 67102570 t fired, .
Time elapsed: 1057 secs. Pages in use: 68
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 234/308 10/32 DLCround-PT-07a-CTLFireability-08 2339506 m, 12090 m/sec, 68908887 t fired, .
Time elapsed: 1062 secs. Pages in use: 68
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 239/308 10/32 DLCround-PT-07a-CTLFireability-08 2391284 m, 10355 m/sec, 70411514 t fired, .
Time elapsed: 1067 secs. Pages in use: 68
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 244/308 11/32 DLCround-PT-07a-CTLFireability-08 2441035 m, 9950 m/sec, 71870078 t fired, .
Time elapsed: 1072 secs. Pages in use: 69
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 249/308 11/32 DLCround-PT-07a-CTLFireability-08 2488782 m, 9549 m/sec, 73198067 t fired, .
Time elapsed: 1077 secs. Pages in use: 70
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 254/308 11/32 DLCround-PT-07a-CTLFireability-08 2539425 m, 10128 m/sec, 74661557 t fired, .
Time elapsed: 1082 secs. Pages in use: 70
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 259/308 11/32 DLCround-PT-07a-CTLFireability-08 2590060 m, 10127 m/sec, 76164053 t fired, .
Time elapsed: 1087 secs. Pages in use: 70
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 264/308 11/32 DLCround-PT-07a-CTLFireability-08 2642329 m, 10453 m/sec, 77622270 t fired, .
Time elapsed: 1092 secs. Pages in use: 70
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 269/308 12/32 DLCround-PT-07a-CTLFireability-08 2686971 m, 8928 m/sec, 78926696 t fired, .
Time elapsed: 1097 secs. Pages in use: 72
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 274/308 12/32 DLCround-PT-07a-CTLFireability-08 2730878 m, 8781 m/sec, 80251462 t fired, .
Time elapsed: 1102 secs. Pages in use: 73
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 279/308 12/32 DLCround-PT-07a-CTLFireability-08 2780173 m, 9859 m/sec, 81725116 t fired, .
Time elapsed: 1107 secs. Pages in use: 73
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 284/308 12/32 DLCround-PT-07a-CTLFireability-08 2830896 m, 10144 m/sec, 83221533 t fired, .
Time elapsed: 1112 secs. Pages in use: 73
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 289/308 12/32 DLCround-PT-07a-CTLFireability-08 2885128 m, 10846 m/sec, 84715353 t fired, .
Time elapsed: 1117 secs. Pages in use: 74
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 294/308 13/32 DLCround-PT-07a-CTLFireability-08 2945603 m, 12095 m/sec, 86377568 t fired, .
Time elapsed: 1122 secs. Pages in use: 75
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 299/308 13/32 DLCround-PT-07a-CTLFireability-08 2993123 m, 9504 m/sec, 87726070 t fired, .
Time elapsed: 1127 secs. Pages in use: 75
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 304/308 13/32 DLCround-PT-07a-CTLFireability-08 3047216 m, 10818 m/sec, 89282720 t fired, .
Time elapsed: 1132 secs. Pages in use: 75
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 29 (type EXCL) for DLCround-PT-07a-CTLFireability-08 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 1 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1137 secs. Pages in use: 75
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 DLCround-PT-07a-CTLFireability-05
lola: time limit : 307 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 29 (type EXCL) for 28 DLCround-PT-07a-CTLFireability-08
lola: time limit : 2463 sec
lola: memory limit: 5 pages
lola: FINISHED task # 20 (type EXCL) for DLCround-PT-07a-CTLFireability-05
lola: result : true
lola: markings : 4
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/307 1/5 DLCround-PT-07a-CTLFireability-08 48118 m, -599819 m/sec, 1457248 t fired, .
Time elapsed: 1142 secs. Pages in use: 79
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/307 1/5 DLCround-PT-07a-CTLFireability-08 103758 m, 11128 m/sec, 3189997 t fired, .
Time elapsed: 1147 secs. Pages in use: 79
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/307 1/5 DLCround-PT-07a-CTLFireability-08 145786 m, 8405 m/sec, 4448679 t fired, .
Time elapsed: 1152 secs. Pages in use: 79
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 20/307 1/5 DLCround-PT-07a-CTLFireability-08 190808 m, 9004 m/sec, 5841581 t fired, .
Time elapsed: 1157 secs. Pages in use: 79
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 25/307 1/5 DLCround-PT-07a-CTLFireability-08 227157 m, 7269 m/sec, 6961303 t fired, .
Time elapsed: 1162 secs. Pages in use: 80
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 30/307 2/5 DLCround-PT-07a-CTLFireability-08 268918 m, 8352 m/sec, 8172814 t fired, .
Time elapsed: 1167 secs. Pages in use: 82
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 35/307 2/5 DLCround-PT-07a-CTLFireability-08 317866 m, 9789 m/sec, 9647571 t fired, .
Time elapsed: 1172 secs. Pages in use: 82
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 40/307 2/5 DLCround-PT-07a-CTLFireability-08 360924 m, 8611 m/sec, 10904371 t fired, .
Time elapsed: 1177 secs. Pages in use: 82
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 45/307 2/5 DLCround-PT-07a-CTLFireability-08 409198 m, 9654 m/sec, 12375710 t fired, .
Time elapsed: 1182 secs. Pages in use: 82
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 50/307 2/5 DLCround-PT-07a-CTLFireability-08 447149 m, 7590 m/sec, 13543988 t fired, .
Time elapsed: 1187 secs. Pages in use: 83
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 55/307 3/5 DLCround-PT-07a-CTLFireability-08 492436 m, 9057 m/sec, 14942770 t fired, .
Time elapsed: 1192 secs. Pages in use: 86
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 60/307 3/5 DLCround-PT-07a-CTLFireability-08 543374 m, 10187 m/sec, 16419264 t fired, .
Time elapsed: 1197 secs. Pages in use: 86
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 65/307 3/5 DLCround-PT-07a-CTLFireability-08 584991 m, 8323 m/sec, 17704927 t fired, .
Time elapsed: 1202 secs. Pages in use: 87
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 70/307 3/5 DLCround-PT-07a-CTLFireability-08 630301 m, 9062 m/sec, 19030117 t fired, .
Time elapsed: 1207 secs. Pages in use: 87
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 75/307 3/5 DLCround-PT-07a-CTLFireability-08 672068 m, 8353 m/sec, 20250065 t fired, .
Time elapsed: 1212 secs. Pages in use: 87
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 80/307 3/5 DLCround-PT-07a-CTLFireability-08 711679 m, 7922 m/sec, 21374212 t fired, .
Time elapsed: 1217 secs. Pages in use: 87
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 85/307 4/5 DLCround-PT-07a-CTLFireability-08 750806 m, 7825 m/sec, 22519652 t fired, .
Time elapsed: 1222 secs. Pages in use: 90
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 90/307 4/5 DLCround-PT-07a-CTLFireability-08 793956 m, 8630 m/sec, 23732493 t fired, .
Time elapsed: 1227 secs. Pages in use: 90
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 95/307 4/5 DLCround-PT-07a-CTLFireability-08 831808 m, 7570 m/sec, 24845896 t fired, .
Time elapsed: 1232 secs. Pages in use: 90
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 100/307 4/5 DLCround-PT-07a-CTLFireability-08 879574 m, 9553 m/sec, 26220606 t fired, .
Time elapsed: 1237 secs. Pages in use: 90
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 105/307 4/5 DLCround-PT-07a-CTLFireability-08 929531 m, 9991 m/sec, 27559635 t fired, .
Time elapsed: 1242 secs. Pages in use: 90
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 110/307 5/5 DLCround-PT-07a-CTLFireability-08 972697 m, 8633 m/sec, 28831484 t fired, .
Time elapsed: 1247 secs. Pages in use: 93
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 115/307 5/5 DLCround-PT-07a-CTLFireability-08 1017865 m, 9033 m/sec, 30209920 t fired, .
Time elapsed: 1252 secs. Pages in use: 93
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 120/307 5/5 DLCround-PT-07a-CTLFireability-08 1061979 m, 8822 m/sec, 31495208 t fired, .
Time elapsed: 1257 secs. Pages in use: 94
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 125/307 5/5 DLCround-PT-07a-CTLFireability-08 1101607 m, 7925 m/sec, 32626109 t fired, .
Time elapsed: 1262 secs. Pages in use: 94
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 130/307 5/5 DLCround-PT-07a-CTLFireability-08 1149308 m, 9540 m/sec, 34013182 t fired, .
Time elapsed: 1267 secs. Pages in use: 94
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 135/307 5/5 DLCround-PT-07a-CTLFireability-08 1195659 m, 9270 m/sec, 35345617 t fired, .
Time elapsed: 1272 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 29 (type EXCL) for DLCround-PT-07a-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1277 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 9 (type EXCL) for 6 DLCround-PT-07a-CTLFireability-02
lola: time limit : 331 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 5/331 1/32 DLCround-PT-07a-CTLFireability-02 40948 m, 8189 m/sec, 1350009 t fired, .
Time elapsed: 1282 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 10/331 1/32 DLCround-PT-07a-CTLFireability-02 64394 m, 4689 m/sec, 2470877 t fired, .
Time elapsed: 1287 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 15/331 1/32 DLCround-PT-07a-CTLFireability-02 91536 m, 5428 m/sec, 3682873 t fired, .
Time elapsed: 1292 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 20/331 1/32 DLCround-PT-07a-CTLFireability-02 123657 m, 6424 m/sec, 4868243 t fired, .
Time elapsed: 1297 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 25/331 1/32 DLCround-PT-07a-CTLFireability-02 149987 m, 5266 m/sec, 5839161 t fired, .
Time elapsed: 1302 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 30/331 1/32 DLCround-PT-07a-CTLFireability-02 176851 m, 5372 m/sec, 6809210 t fired, .
Time elapsed: 1307 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 35/331 1/32 DLCround-PT-07a-CTLFireability-02 204742 m, 5578 m/sec, 7839327 t fired, .
Time elapsed: 1312 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 40/331 1/32 DLCround-PT-07a-CTLFireability-02 239485 m, 6948 m/sec, 8867931 t fired, .
Time elapsed: 1317 secs. Pages in use: 95
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 45/331 2/32 DLCround-PT-07a-CTLFireability-02 262398 m, 4582 m/sec, 9957667 t fired, .
Time elapsed: 1322 secs. Pages in use: 96
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 50/331 2/32 DLCround-PT-07a-CTLFireability-02 286901 m, 4900 m/sec, 11113263 t fired, .
Time elapsed: 1327 secs. Pages in use: 96
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 55/331 2/32 DLCround-PT-07a-CTLFireability-02 308196 m, 4259 m/sec, 12052198 t fired, .
Time elapsed: 1332 secs. Pages in use: 97
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 60/331 2/32 DLCround-PT-07a-CTLFireability-02 332566 m, 4874 m/sec, 13117513 t fired, .
Time elapsed: 1337 secs. Pages in use: 98
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 65/331 2/32 DLCround-PT-07a-CTLFireability-02 358364 m, 5159 m/sec, 14138877 t fired, .
Time elapsed: 1342 secs. Pages in use: 98
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 70/331 2/32 DLCround-PT-07a-CTLFireability-02 394890 m, 7305 m/sec, 15294273 t fired, .
Time elapsed: 1347 secs. Pages in use: 98
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 75/331 2/32 DLCround-PT-07a-CTLFireability-02 417182 m, 4458 m/sec, 16378064 t fired, .
Time elapsed: 1352 secs. Pages in use: 99
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 80/331 2/32 DLCround-PT-07a-CTLFireability-02 439812 m, 4526 m/sec, 17426307 t fired, .
Time elapsed: 1357 secs. Pages in use: 99
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 85/331 2/32 DLCround-PT-07a-CTLFireability-02 457688 m, 3575 m/sec, 18274063 t fired, .
Time elapsed: 1362 secs. Pages in use: 100
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 90/331 3/32 DLCround-PT-07a-CTLFireability-02 484479 m, 5358 m/sec, 19470406 t fired, .
Time elapsed: 1367 secs. Pages in use: 102
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 95/331 3/32 DLCround-PT-07a-CTLFireability-02 508952 m, 4894 m/sec, 20560897 t fired, .
Time elapsed: 1372 secs. Pages in use: 102
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 100/331 3/32 DLCround-PT-07a-CTLFireability-02 533877 m, 4985 m/sec, 21642844 t fired, .
Time elapsed: 1377 secs. Pages in use: 102
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 105/331 3/32 DLCround-PT-07a-CTLFireability-02 564137 m, 6052 m/sec, 22750052 t fired, .
Time elapsed: 1382 secs. Pages in use: 102
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 110/331 3/32 DLCround-PT-07a-CTLFireability-02 599387 m, 7050 m/sec, 23923406 t fired, .
Time elapsed: 1387 secs. Pages in use: 102
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 115/331 3/32 DLCround-PT-07a-CTLFireability-02 635368 m, 7196 m/sec, 25081491 t fired, .
Time elapsed: 1392 secs. Pages in use: 104
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 120/331 3/32 DLCround-PT-07a-CTLFireability-02 658952 m, 4716 m/sec, 26190409 t fired, .
Time elapsed: 1397 secs. Pages in use: 104
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 125/331 3/32 DLCround-PT-07a-CTLFireability-02 681958 m, 4601 m/sec, 27214955 t fired, .
Time elapsed: 1402 secs. Pages in use: 105
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 131/331 3/32 DLCround-PT-07a-CTLFireability-02 705587 m, 4725 m/sec, 28271089 t fired, .
Time elapsed: 1408 secs. Pages in use: 105
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 136/331 3/32 DLCround-PT-07a-CTLFireability-02 724839 m, 3850 m/sec, 29140770 t fired, .
Time elapsed: 1413 secs. Pages in use: 105
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 141/331 4/32 DLCround-PT-07a-CTLFireability-02 748377 m, 4707 m/sec, 30162513 t fired, .
Time elapsed: 1418 secs. Pages in use: 107
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 146/331 4/32 DLCround-PT-07a-CTLFireability-02 777284 m, 5781 m/sec, 31269999 t fired, .
Time elapsed: 1423 secs. Pages in use: 108
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 151/331 4/32 DLCround-PT-07a-CTLFireability-02 801804 m, 4904 m/sec, 32307348 t fired, .
Time elapsed: 1428 secs. Pages in use: 108
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 156/331 4/32 DLCround-PT-07a-CTLFireability-02 829339 m, 5507 m/sec, 33537020 t fired, .
Time elapsed: 1433 secs. Pages in use: 108
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 161/331 4/32 DLCround-PT-07a-CTLFireability-02 852099 m, 4552 m/sec, 34474642 t fired, .
Time elapsed: 1438 secs. Pages in use: 108
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 166/331 4/32 DLCround-PT-07a-CTLFireability-02 876839 m, 4948 m/sec, 35520573 t fired, .
Time elapsed: 1443 secs. Pages in use: 109
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 171/331 4/32 DLCround-PT-07a-CTLFireability-02 901443 m, 4920 m/sec, 36540619 t fired, .
Time elapsed: 1448 secs. Pages in use: 109
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 176/331 4/32 DLCround-PT-07a-CTLFireability-02 927649 m, 5241 m/sec, 37719453 t fired, .
Time elapsed: 1453 secs. Pages in use: 111
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 181/331 4/32 DLCround-PT-07a-CTLFireability-02 950637 m, 4597 m/sec, 38700178 t fired, .
Time elapsed: 1458 secs. Pages in use: 111
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 186/331 5/32 DLCround-PT-07a-CTLFireability-02 972849 m, 4442 m/sec, 39717078 t fired, .
Time elapsed: 1463 secs. Pages in use: 112
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 191/331 5/32 DLCround-PT-07a-CTLFireability-02 994372 m, 4304 m/sec, 40639712 t fired, .
Time elapsed: 1468 secs. Pages in use: 112
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 196/331 5/32 DLCround-PT-07a-CTLFireability-02 1016794 m, 4484 m/sec, 41603377 t fired, .
Time elapsed: 1473 secs. Pages in use: 113
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 201/331 5/32 DLCround-PT-07a-CTLFireability-02 1039653 m, 4571 m/sec, 42646681 t fired, .
Time elapsed: 1478 secs. Pages in use: 113
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 206/331 5/32 DLCround-PT-07a-CTLFireability-02 1062887 m, 4646 m/sec, 43698396 t fired, .
Time elapsed: 1483 secs. Pages in use: 114
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 211/331 5/32 DLCround-PT-07a-CTLFireability-02 1084763 m, 4375 m/sec, 44709086 t fired, .
Time elapsed: 1488 secs. Pages in use: 114
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 216/331 5/32 DLCround-PT-07a-CTLFireability-02 1111369 m, 5321 m/sec, 45756612 t fired, .
Time elapsed: 1493 secs. Pages in use: 114
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 221/331 5/32 DLCround-PT-07a-CTLFireability-02 1131482 m, 4022 m/sec, 46660482 t fired, .
Time elapsed: 1498 secs. Pages in use: 115
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 226/331 5/32 DLCround-PT-07a-CTLFireability-02 1153010 m, 4305 m/sec, 47645397 t fired, .
Time elapsed: 1503 secs. Pages in use: 116
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 231/331 5/32 DLCround-PT-07a-CTLFireability-02 1176148 m, 4627 m/sec, 48706476 t fired, .
Time elapsed: 1508 secs. Pages in use: 117
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 236/331 5/32 DLCround-PT-07a-CTLFireability-02 1198109 m, 4392 m/sec, 49739694 t fired, .
Time elapsed: 1513 secs. Pages in use: 117
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07a-CTLFireability-05: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-10: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-13: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-07a-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCround-PT-07a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-07a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCround-PT-07a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 241/331 6/32 DLCround-PT-07a-CTLFireability-02 1219065 m, 4191 m/sec, 50696629 t fired, .
Time elapsed: 1518 secs. Pages in use: 118
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 425 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-07a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCround-PT-07a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038393100338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-07a.tgz
mv DLCround-PT-07a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;