About the Execution of LoLA for DLCflexbar-PT-5b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2581.071 | 297899.00 | 373685.00 | 944.80 | TFTFTTFFTFTFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r061-tall-162038392900222.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCflexbar-PT-5b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038392900222
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.8M
-rw-r--r-- 1 mcc users 16K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 135K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.2K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 75K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Mar 23 03:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 23 03:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 22 13:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 22 13:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 6.5M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-00
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-01
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-02
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-03
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-04
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-05
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-06
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-07
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-08
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-09
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-10
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-11
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-12
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-13
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-14
FORMULA_NAME DLCflexbar-PT-5b-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1620439212019
starting LoLA
BK_INPUT DLCflexbar-PT-5b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5b-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1620439509918
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-09: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 183 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 6.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-09: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 188 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 6.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-09: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 193 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 5.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-09: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 198 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 6.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-09: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 203 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 6.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-04: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-05: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-09: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 208 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 6.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG 0 0 0 0 1 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 54 (type EXCL) for 21 DLCflexbar-PT-5b-ReachabilityCardinality-07
lola: time limit : 220 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type FNDP) for 21 DLCflexbar-PT-5b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type EQUN) for 21 DLCflexbar-PT-5b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SRCH) for 21 DLCflexbar-PT-5b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 53 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-07
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 50 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-07
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 51 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 54 (type EXCL) for DLCflexbar-PT-5b-ReachabilityCardinality-07 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 79 (type EXCL) for 42 DLCflexbar-PT-5b-ReachabilityCardinality-14
lola: time limit : 472 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 91 (type FNDP) for 33 DLCflexbar-PT-5b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
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lola: LAUNCH task # 92 (type EQUN) for 33 DLCflexbar-PT-5b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type SRCH) for 33 DLCflexbar-PT-5b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 91 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-11
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 92 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 94 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-11 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type FNDP) for 27 DLCflexbar-PT-5b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type EQUN) for 27 DLCflexbar-PT-5b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 104 (type SRCH) for 27 DLCflexbar-PT-5b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-51.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 104 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-09
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 64 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 82 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-82.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-92.sara.
sara: place or transition ordering is non-deterministic
lola: LAUNCH task # 111 (type SRCH) for 45 DLCflexbar-PT-5b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 125 (type SRCH) for 45 DLCflexbar-PT-5b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
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lola: LAUNCH task # 129 (type FNDP) for 3 DLCflexbar-PT-5b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 79 (type EXCL) for DLCflexbar-PT-5b-ReachabilityCardinality-14
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 110 (type EXCL) for 12 DLCflexbar-PT-5b-ReachabilityCardinality-04
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: FINISHED task # 111 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-15
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 125 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 103 (type FNDP) for 36 DLCflexbar-PT-5b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 115 (type FNDP) for 24 DLCflexbar-PT-5b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 64 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-09
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 103 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 129 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 51 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-07
lola: result : true
lola: LAUNCH task # 84 (type FNDP) for 30 DLCflexbar-PT-5b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type EQUN) for 30 DLCflexbar-PT-5b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 115 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 82 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-09
lola: result : true
lola: FINISHED task # 92 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-11
lola: result : true
lola: FINISHED task # 125 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 122 (type FNDP) for 6 DLCflexbar-PT-5b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 122 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 124 (type FNDP) for 18 DLCflexbar-PT-5b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-113.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 124 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-06
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 57 (type FNDP) for 9 DLCflexbar-PT-5b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 57 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-03
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 81 (type FNDP) for 39 DLCflexbar-PT-5b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 81 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 97 (type FNDP) for 15 DLCflexbar-PT-5b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 113 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-10
lola: result : false
lola: CANCELED task # 84 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 98 (type EQUN) for 15 DLCflexbar-PT-5b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type SRCH) for 15 DLCflexbar-PT-5b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 84 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 192357
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-98.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 100 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-05
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 97 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 98 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 74 (type FNDP) for 12 DLCflexbar-PT-5b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type EQUN) for 12 DLCflexbar-PT-5b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 109 (type SRCH) for 12 DLCflexbar-PT-5b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 98 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-05
lola: result : unknown
lola: FINISHED task # 97 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 2935
lola: tried executions : 1469
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 74 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-04
lola: result : true
lola: fired transitions : 6
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 106 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 109 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 110 (type EXCL) for DLCflexbar-PT-5b-ReachabilityCardinality-04 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-106.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF true findpath
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-04: EF true findpath
DLCflexbar-PT-5b-ReachabilityCardinality-05: AG true tandem / insertion
DLCflexbar-PT-5b-ReachabilityCardinality-06: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-07: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-08: EF true findpath
DLCflexbar-PT-5b-ReachabilityCardinality-09: AG false tandem / insertion
DLCflexbar-PT-5b-ReachabilityCardinality-10: AG true state equation
DLCflexbar-PT-5b-ReachabilityCardinality-11: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-12: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-13: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-14: AG false tandem / relaxed
DLCflexbar-PT-5b-ReachabilityCardinality-15: EF true tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 293 secs. Pages in use: 3
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 153 (type EXCL) for 0 DLCflexbar-PT-5b-ReachabilityCardinality-00
lola: time limit : 3303 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 149 (type FNDP) for 0 DLCflexbar-PT-5b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 150 (type EQUN) for 0 DLCflexbar-PT-5b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 152 (type SRCH) for 0 DLCflexbar-PT-5b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 153 (type EXCL) for DLCflexbar-PT-5b-ReachabilityCardinality-00
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 149 (type FNDP) for DLCflexbar-PT-5b-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 150 (type EQUN) for DLCflexbar-PT-5b-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 152 (type SRCH) for DLCflexbar-PT-5b-ReachabilityCardinality-00 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-5b-ReachabilityCardinality-00: EF true tandem / relaxed
DLCflexbar-PT-5b-ReachabilityCardinality-01: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-02: EF true findpath
DLCflexbar-PT-5b-ReachabilityCardinality-03: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-04: EF true findpath
DLCflexbar-PT-5b-ReachabilityCardinality-05: AG true tandem / insertion
DLCflexbar-PT-5b-ReachabilityCardinality-06: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-07: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-08: EF true findpath
DLCflexbar-PT-5b-ReachabilityCardinality-09: AG false tandem / insertion
DLCflexbar-PT-5b-ReachabilityCardinality-10: AG true state equation
DLCflexbar-PT-5b-ReachabilityCardinality-11: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-12: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-13: AG false findpath
DLCflexbar-PT-5b-ReachabilityCardinality-14: AG false tandem / relaxed
DLCflexbar-PT-5b-ReachabilityCardinality-15: EF true tandem / insertion
Time elapsed: 297 secs. Pages in use: 3
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-150.sara.
sara: place or transition ordering is non-deterministic
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038392900222"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5b.tgz
mv DLCflexbar-PT-5b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;