About the Execution of LoLA for DLCflexbar-PT-5a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5813.527 | 3600000.00 | 520992.00 | 8762.00 | FFTFFFFFFTFFFF?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r061-tall-162038392900213.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCflexbar-PT-5a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038392900213
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.1M
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 107K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.9K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Mar 23 03:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 23 03:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 22 13:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 22 13:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 2.8M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5a-00
FORMULA_NAME DLCflexbar-PT-5a-01
FORMULA_NAME DLCflexbar-PT-5a-02
FORMULA_NAME DLCflexbar-PT-5a-03
FORMULA_NAME DLCflexbar-PT-5a-04
FORMULA_NAME DLCflexbar-PT-5a-05
FORMULA_NAME DLCflexbar-PT-5a-06
FORMULA_NAME DLCflexbar-PT-5a-07
FORMULA_NAME DLCflexbar-PT-5a-08
FORMULA_NAME DLCflexbar-PT-5a-09
FORMULA_NAME DLCflexbar-PT-5a-10
FORMULA_NAME DLCflexbar-PT-5a-11
FORMULA_NAME DLCflexbar-PT-5a-12
FORMULA_NAME DLCflexbar-PT-5a-13
FORMULA_NAME DLCflexbar-PT-5a-14
FORMULA_NAME DLCflexbar-PT-5a-15
=== Now, execution of the tool begins
BK_START 1620436992282
starting LoLA
BK_INPUT DLCflexbar-PT-5a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability
FORMULA DLCflexbar-PT-5a-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:493
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 68 (type SKEL/SRCH) for 12 DLCflexbar-PT-5a-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type SKEL/SRCH) for DLCflexbar-PT-5a-04
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 49 (type CNST) for 48 DLCflexbar-PT-5a-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 54 (type CNST) for 51 DLCflexbar-PT-5a-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 49 (type CNST) for DLCflexbar-PT-5a-12
lola: result : false
lola: FINISHED task # 54 (type CNST) for DLCflexbar-PT-5a-13
lola: result : false
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 69 (type SKEL/SRCH) for 12 DLCflexbar-PT-5a-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 72 (type SKEL/FNDP) for 26 DLCflexbar-PT-5a-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SKEL/EQUN) for 26 DLCflexbar-PT-5a-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SKEL/SRCH) for 26 DLCflexbar-PT-5a-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 74 (type SKEL/SRCH) for DLCflexbar-PT-5a-06
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 72 (type FNDP) for DLCflexbar-PT-5a-06 (obsolete)
lola: CANCELED task # 73 (type EQUN) for DLCflexbar-PT-5a-06 (obsolete)
sara: try reading problem file /home/mcc/execution/LTLFireability-73.sara.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 73 (type SKEL/EQUN) for DLCflexbar-PT-5a-06
lola: result : true
lola: FINISHED task # 72 (type SKEL/FNDP) for DLCflexbar-PT-5a-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: FINISHED task # 69 (type SKEL/SRCH) for DLCflexbar-PT-5a-04
lola: result : false
lola: markings : 121068
lola: fired transitions : 786405
lola: time used : 2.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5a-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-06: AG 0 0 0 0 3 0 0 1
DLCflexbar-PT-5a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5a-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 9 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 79 (type EXCL) for 26 DLCflexbar-PT-5a-06
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 77 (type FNDP) for 26 DLCflexbar-PT-5a-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type EQUN) for 26 DLCflexbar-PT-5a-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type SRCH) for 26 DLCflexbar-PT-5a-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 79 (type EXCL) for DLCflexbar-PT-5a-06
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 77 (type FNDP) for DLCflexbar-PT-5a-06 (obsolete)
lola: CANCELED task # 78 (type EQUN) for DLCflexbar-PT-5a-06 (obsolete)
lola: CANCELED task # 80 (type SRCH) for DLCflexbar-PT-5a-06 (obsolete)
lola: FINISHED task # 80 (type SRCH) for DLCflexbar-PT-5a-06
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 77 (type FNDP) for DLCflexbar-PT-5a-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/LTLFireability-78.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 78 (type EQUN) for DLCflexbar-PT-5a-06
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-5a-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5a-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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63 LTL EXCL 73/325 4/32 DLCflexbar-PT-5a-14 389783 m, 5434 m/sec, 42900379 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 78/325 4/32 DLCflexbar-PT-5a-14 416603 m, 5364 m/sec, 45820915 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 83/325 4/32 DLCflexbar-PT-5a-14 443543 m, 5388 m/sec, 48745919 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 88/325 4/32 DLCflexbar-PT-5a-14 470173 m, 5326 m/sec, 51660007 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 93/325 5/32 DLCflexbar-PT-5a-14 497431 m, 5451 m/sec, 54579073 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 98/325 5/32 DLCflexbar-PT-5a-14 524403 m, 5394 m/sec, 57500298 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 103/325 5/32 DLCflexbar-PT-5a-14 551643 m, 5448 m/sec, 60414110 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 108/325 5/32 DLCflexbar-PT-5a-14 578546 m, 5380 m/sec, 63321010 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 113/325 6/32 DLCflexbar-PT-5a-14 605387 m, 5368 m/sec, 66230571 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 118/325 6/32 DLCflexbar-PT-5a-14 632353 m, 5393 m/sec, 69140580 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 123/325 6/32 DLCflexbar-PT-5a-14 659329 m, 5395 m/sec, 72052187 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 128/325 6/32 DLCflexbar-PT-5a-14 686311 m, 5396 m/sec, 74965160 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 133/325 6/32 DLCflexbar-PT-5a-14 712956 m, 5329 m/sec, 77877278 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
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63 LTL EXCL 158/325 8/32 DLCflexbar-PT-5a-14 846067 m, 5338 m/sec, 92430581 t fired, .
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 238/325 11/32 DLCflexbar-PT-5a-14 1270068 m, 5304 m/sec, 138762214 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 243/325 11/32 DLCflexbar-PT-5a-14 1296301 m, 5246 m/sec, 141672989 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 248/325 12/32 DLCflexbar-PT-5a-14 1322601 m, 5260 m/sec, 144566901 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 258/325 12/32 DLCflexbar-PT-5a-14 1375451 m, 5272 m/sec, 150341426 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 318/325 15/32 DLCflexbar-PT-5a-14 1692754 m, 5311 m/sec, 184968376 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 323/325 15/32 DLCflexbar-PT-5a-14 1719387 m, 5326 m/sec, 187846740 t fired, .
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lola: CANCELED task # 63 (type EXCL) for DLCflexbar-PT-5a-14 (local timeout)
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 0 0 1 1 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 46 (type EXCL) for 45 DLCflexbar-PT-5a-11
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 63 (type EXCL) for 62 DLCflexbar-PT-5a-14
lola: time limit : 3256 sec
lola: memory limit: 5 pages
lola: FINISHED task # 46 (type EXCL) for DLCflexbar-PT-5a-11
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
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DLCflexbar-PT-5a-00: LTL false LTL model checker
DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 5/325 1/5 DLCflexbar-PT-5a-14 26932 m, -338491 m/sec, 3047452 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 10/325 1/5 DLCflexbar-PT-5a-14 53863 m, 5386 m/sec, 6048921 t fired, .
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DLCflexbar-PT-5a-00: LTL false LTL model checker
DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 15/325 1/5 DLCflexbar-PT-5a-14 80983 m, 5424 m/sec, 9032782 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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63 LTL EXCL 20/325 1/5 DLCflexbar-PT-5a-14 108079 m, 5419 m/sec, 11997235 t fired, .
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DLCflexbar-PT-5a-00: LTL false LTL model checker
DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 25/325 2/5 DLCflexbar-PT-5a-14 135037 m, 5391 m/sec, 14960623 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 30/325 2/5 DLCflexbar-PT-5a-14 162007 m, 5394 m/sec, 17917849 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 35/325 2/5 DLCflexbar-PT-5a-14 189075 m, 5413 m/sec, 20862954 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 40/325 2/5 DLCflexbar-PT-5a-14 215770 m, 5339 m/sec, 23804119 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 45/325 3/5 DLCflexbar-PT-5a-14 242410 m, 5328 m/sec, 26745854 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 50/325 3/5 DLCflexbar-PT-5a-14 269267 m, 5371 m/sec, 29668819 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 55/325 3/5 DLCflexbar-PT-5a-14 296013 m, 5349 m/sec, 32607076 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 60/325 3/5 DLCflexbar-PT-5a-14 322021 m, 5201 m/sec, 35542247 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 LTL EXCL 65/325 3/5 DLCflexbar-PT-5a-14 348651 m, 5326 m/sec, 38465132 t fired, .
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-03: LTL false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
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DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-5a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: CONJ 0 2 0 0 2 0 0 0
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DLCflexbar-PT-5a-14: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
DLCflexbar-PT-5a-15: LTL false LTL model checker
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DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-08: CONJ false LTL model checker
DLCflexbar-PT-5a-09: F true state space / EG
DLCflexbar-PT-5a-10: LTL false LTL model checker
DLCflexbar-PT-5a-11: LTL false LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: CONJ false preprocessing
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DLCflexbar-PT-5a-08: CONJ false LTL model checker
DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-04: CONJ false LTL model checker
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DLCflexbar-PT-5a-06: AG false state space
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DLCflexbar-PT-5a-08: CONJ false LTL model checker
DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-04: CONJ false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-08: CONJ false LTL model checker
DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-04: CONJ false LTL model checker
DLCflexbar-PT-5a-05: LTL false LTL model checker
DLCflexbar-PT-5a-06: AG false state space
DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-08: CONJ false LTL model checker
DLCflexbar-PT-5a-09: F true state space / EG
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DLCflexbar-PT-5a-11: LTL false LTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038392900213"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5a.tgz
mv DLCflexbar-PT-5a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;