About the Execution of LoLA for DLCflexbar-PT-5a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 13498.023 | 3600000.00 | 1112801.00 | 9334.00 | TFTFTTFF?FFTFFF? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r061-tall-162038392900212.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCflexbar-PT-5a, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038392900212
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.1M
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 107K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.9K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Mar 23 03:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 23 03:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 22 13:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 22 13:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 2.8M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5a-00
FORMULA_NAME DLCflexbar-PT-5a-01
FORMULA_NAME DLCflexbar-PT-5a-02
FORMULA_NAME DLCflexbar-PT-5a-03
FORMULA_NAME DLCflexbar-PT-5a-04
FORMULA_NAME DLCflexbar-PT-5a-05
FORMULA_NAME DLCflexbar-PT-5a-06
FORMULA_NAME DLCflexbar-PT-5a-07
FORMULA_NAME DLCflexbar-PT-5a-08
FORMULA_NAME DLCflexbar-PT-5a-09
FORMULA_NAME DLCflexbar-PT-5a-10
FORMULA_NAME DLCflexbar-PT-5a-11
FORMULA_NAME DLCflexbar-PT-5a-12
FORMULA_NAME DLCflexbar-PT-5a-13
FORMULA_NAME DLCflexbar-PT-5a-14
FORMULA_NAME DLCflexbar-PT-5a-15
=== Now, execution of the tool begins
BK_START 1620436875049
starting LoLA
BK_INPUT DLCflexbar-PT-5a
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLCardinality
FORMULA DLCflexbar-PT-5a-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-5a-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 60 (type SKEL/SRCH) for 28 DLCflexbar-PT-5a-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 1.000000 secs.
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 23 (type CNST) for 22 DLCflexbar-PT-5a-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 41 (type CNST) for 38 DLCflexbar-PT-5a-10
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 23 (type CNST) for DLCflexbar-PT-5a-06
lola: result : false
lola: FINISHED task # 41 (type CNST) for DLCflexbar-PT-5a-10
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 20 (type CNST) for 19 DLCflexbar-PT-5a-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 49 (type CNST) for 48 DLCflexbar-PT-5a-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 20 (type CNST) for DLCflexbar-PT-5a-05
lola: result : true
lola: FINISHED task # 49 (type CNST) for DLCflexbar-PT-5a-12
lola: result : false
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 61 (type SKEL/SRCH) for 45 DLCflexbar-PT-5a-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 61 (type SKEL/SRCH) for DLCflexbar-PT-5a-11
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: Created skeleton in 1.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 64 (type SKEL/FNDP) for 51 DLCflexbar-PT-5a-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type SKEL/EQUN) for 51 DLCflexbar-PT-5a-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type SKEL/SRCH) for 51 DLCflexbar-PT-5a-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 66 (type SKEL/SRCH) for DLCflexbar-PT-5a-13
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 64 (type FNDP) for DLCflexbar-PT-5a-13 (obsolete)
lola: CANCELED task # 65 (type EQUN) for DLCflexbar-PT-5a-13 (obsolete)
sara: try reading problem file /home/mcc/execution/LTLCardinality-65.sara.
lola: Created skeleton in 0.000000 secs.
sara: place or transition ordering is non-deterministic
lola: NOTDEADLOCKFREE
lola: FINISHED task # 64 (type SKEL/FNDP) for DLCflexbar-PT-5a-13
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 65 (type SKEL/EQUN) for DLCflexbar-PT-5a-13
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-5a-05: INITIAL true preprocessing
DLCflexbar-PT-5a-06: INITIAL false preprocessing
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-12: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-04: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-08: LTL 0 0 1 0 0 0 0 0
DLCflexbar-PT-5a-09: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-5a-11: LTL/CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-13: AG 4 0 0 0 3 0 0 1
DLCflexbar-PT-5a-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 LTL SRCH 5/3592 1/5 DLCflexbar-PT-5a-08 94979 m, 18995 m/sec, 867931 t fired, .
Time elapsed: 13 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 71 (type EXCL) for 51 DLCflexbar-PT-5a-13
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 69 (type FNDP) for 51 DLCflexbar-PT-5a-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type EQUN) for 51 DLCflexbar-PT-5a-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 71 (type EXCL) for DLCflexbar-PT-5a-13
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 69 (type FNDP) for DLCflexbar-PT-5a-13 (obsolete)
lola: CANCELED task # 70 (type EQUN) for DLCflexbar-PT-5a-13 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 69 (type FNDP) for DLCflexbar-PT-5a-13
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/LTLCardinality-70.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 70 (type EQUN) for DLCflexbar-PT-5a-13
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:735
lola: rewrite Frontend/Parser/formula_rewrite.k:695
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 73 (type EXCL) for 0 DLCflexbar-PT-5a-00
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: FINISHED task # 73 (type EXCL) for DLCflexbar-PT-5a-00
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 DLCflexbar-PT-5a-11
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for DLCflexbar-PT-5a-11
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 DLCflexbar-PT-5a-07
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for DLCflexbar-PT-5a-07
lola: result : false
lola: markings : 45
lola: fired transitions : 1873
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 DLCflexbar-PT-5a-08
lola: time limit : 358 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-5a-05: INITIAL true preprocessing
DLCflexbar-PT-5a-06: INITIAL false preprocessing
DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
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DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: LTL 0 0 2 0 0 0 0 0
DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 1/358 1/32 DLCflexbar-PT-5a-08 691 m, 138 m/sec, 63563 t fired, .
60 LTL SRCH 10/3592 1/5 DLCflexbar-PT-5a-08 224247 m, 25853 m/sec, 2197071 t fired, .
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DLCflexbar-PT-5a-06: INITIAL false preprocessing
DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: LTL 0 0 2 0 0 0 0 0
DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 6/358 1/32 DLCflexbar-PT-5a-08 27153 m, 5292 m/sec, 3060675 t fired, .
60 LTL SRCH 15/3592 1/5 DLCflexbar-PT-5a-08 828299 m, 120810 m/sec, 8766710 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-08: LTL 0 0 2 0 0 0 0 0
DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 11/358 1/32 DLCflexbar-PT-5a-08 53543 m, 5278 m/sec, 6058237 t fired, .
60 LTL SRCH 20/3592 1/5 DLCflexbar-PT-5a-08 1444417 m, 123223 m/sec, 15098015 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
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DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-08: LTL 0 0 2 0 0 0 0 0
DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 16/358 1/32 DLCflexbar-PT-5a-08 79975 m, 5286 m/sec, 9020962 t fired, .
60 LTL SRCH 25/3592 1/5 DLCflexbar-PT-5a-08 2043407 m, 119798 m/sec, 21330204 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-08: LTL 0 0 2 0 0 0 0 0
DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 21/358 1/32 DLCflexbar-PT-5a-08 106633 m, 5331 m/sec, 11972217 t fired, .
60 LTL SRCH 30/3592 1/5 DLCflexbar-PT-5a-08 2618783 m, 115075 m/sec, 27489316 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-08: LTL 0 0 2 0 0 0 0 0
DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 26/358 1/32 DLCflexbar-PT-5a-08 133589 m, 5391 m/sec, 14913212 t fired, .
60 LTL SRCH 35/3592 1/5 DLCflexbar-PT-5a-08 3134233 m, 103090 m/sec, 33751440 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
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29 LTL EXCL 31/358 2/32 DLCflexbar-PT-5a-08 160207 m, 5323 m/sec, 17863381 t fired, .
60 LTL SRCH 40/3592 1/5 DLCflexbar-PT-5a-08 3638813 m, 100916 m/sec, 39889648 t fired, .
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DLCflexbar-PT-5a-06: INITIAL false preprocessing
DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 36/358 2/32 DLCflexbar-PT-5a-08 187043 m, 5367 m/sec, 20792255 t fired, .
60 LTL SRCH 45/3592 1/5 DLCflexbar-PT-5a-08 4152421 m, 102721 m/sec, 46306385 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-03: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 41/358 2/32 DLCflexbar-PT-5a-08 213637 m, 5318 m/sec, 23721438 t fired, .
60 LTL SRCH 50/3592 1/5 DLCflexbar-PT-5a-08 4710737 m, 111663 m/sec, 52436123 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 46/358 2/32 DLCflexbar-PT-5a-08 240347 m, 5342 m/sec, 26640902 t fired, .
60 LTL SRCH 55/3592 1/5 DLCflexbar-PT-5a-08 5313447 m, 120542 m/sec, 58705302 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 51/358 2/32 DLCflexbar-PT-5a-08 266915 m, 5313 m/sec, 29569086 t fired, .
60 LTL SRCH 60/3592 1/5 DLCflexbar-PT-5a-08 5832223 m, 103755 m/sec, 64887016 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-00: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-03: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 56/358 3/32 DLCflexbar-PT-5a-08 293383 m, 5293 m/sec, 32485034 t fired, .
60 LTL SRCH 65/3592 1/5 DLCflexbar-PT-5a-08 6356413 m, 104838 m/sec, 70899687 t fired, .
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DLCflexbar-PT-5a-07: LTL false LTL model checker
DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
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DLCflexbar-PT-5a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-02: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
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29 LTL EXCL 61/358 3/32 DLCflexbar-PT-5a-08 320001 m, 5323 m/sec, 35398853 t fired, .
60 LTL SRCH 70/3592 1/5 DLCflexbar-PT-5a-08 6851047 m, 98926 m/sec, 76893847 t fired, .
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DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
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DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 66/358 3/32 DLCflexbar-PT-5a-08 346671 m, 5334 m/sec, 38305108 t fired, .
60 LTL SRCH 75/3592 1/5 DLCflexbar-PT-5a-08 7372587 m, 104308 m/sec, 82962425 t fired, .
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DLCflexbar-PT-5a-10: CONJ false preprocessing
DLCflexbar-PT-5a-11: LTL/CTL true LTL model checker
DLCflexbar-PT-5a-12: INITIAL false preprocessing
DLCflexbar-PT-5a-13: AG false state space
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DLCflexbar-PT-5a-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-5a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-15: LTL 0 1 0 0 1 0 0 0
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29 LTL EXCL 71/358 3/32 DLCflexbar-PT-5a-08 373473 m, 5360 m/sec, 41209691 t fired, .
60 LTL SRCH 80/3592 2/5 DLCflexbar-PT-5a-08 7890938 m, 103670 m/sec, 88893683 t fired, .
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5a"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5a, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038392900212"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5a.tgz
mv DLCflexbar-PT-5a execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;