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Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r061-tall-162038392900197
Last Updated
Jun 28, 2021

About the Execution of LoLA for DLCflexbar-PT-4a

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16247.684 1211792.00 1246928.00 4718.70 F??FT??????TTFF? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r061-tall-162038392900197.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCflexbar-PT-4a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038392900197
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.1M
-rw-r--r-- 1 mcc users 13K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 122K May 5 16:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 97K May 5 16:58 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Mar 23 03:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 23 03:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Mar 22 13:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K Mar 22 13:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 1.7M May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4a-00
FORMULA_NAME DLCflexbar-PT-4a-01
FORMULA_NAME DLCflexbar-PT-4a-02
FORMULA_NAME DLCflexbar-PT-4a-03
FORMULA_NAME DLCflexbar-PT-4a-04
FORMULA_NAME DLCflexbar-PT-4a-05
FORMULA_NAME DLCflexbar-PT-4a-06
FORMULA_NAME DLCflexbar-PT-4a-07
FORMULA_NAME DLCflexbar-PT-4a-08
FORMULA_NAME DLCflexbar-PT-4a-09
FORMULA_NAME DLCflexbar-PT-4a-10
FORMULA_NAME DLCflexbar-PT-4a-11
FORMULA_NAME DLCflexbar-PT-4a-12
FORMULA_NAME DLCflexbar-PT-4a-13
FORMULA_NAME DLCflexbar-PT-4a-14
FORMULA_NAME DLCflexbar-PT-4a-15

=== Now, execution of the tool begins

BK_START 1620435767145

starting LoLA
BK_INPUT DLCflexbar-PT-4a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
LTLFireability

FORMULA DLCflexbar-PT-4a-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620436978937

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:490
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 56 (type SKEL/SRCH) for 28 DLCflexbar-PT-4a-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 60 (type EXCL) for 0 DLCflexbar-PT-4a-00
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 58 (type FNDP) for 0 DLCflexbar-PT-4a-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 0 DLCflexbar-PT-4a-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type EXCL) for DLCflexbar-PT-4a-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 58 (type FNDP) for DLCflexbar-PT-4a-00 (obsolete)
lola: CANCELED task # 59 (type EQUN) for DLCflexbar-PT-4a-00 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/LTLFireability-59.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 58 (type FNDP) for DLCflexbar-PT-4a-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 59 (type EQUN) for DLCflexbar-PT-4a-00
lola: result : true
lola: planning for (null) stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-00: CONJ false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-01: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-04: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 0 1 0 0 0 0 0
DLCflexbar-PT-4a-09: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 LTL SRCH 4/3599 1/5 DLCflexbar-PT-4a-08 84340 m, 16868 m/sec, 982081 t fired, .

Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 23 (type EXCL) for 22 DLCflexbar-PT-4a-06
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type SKEL/SRCH) for DLCflexbar-PT-4a-08
lola: result : false
lola: markings : 478201
lola: fired transitions : 6100227
lola: time used : 9.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-00: CONJ false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 4/224 1/32 DLCflexbar-PT-4a-06 32154 m, 6430 m/sec, 2943549 t fired, .

Time elapsed: 10 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-00: CONJ false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 9/224 1/32 DLCflexbar-PT-4a-06 74658 m, 8500 m/sec, 7029059 t fired, .

Time elapsed: 15 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-00: CONJ false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 14/224 1/32 DLCflexbar-PT-4a-06 117136 m, 8495 m/sec, 11058032 t fired, .

Time elapsed: 20 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-00: CONJ false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-01: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 104/224 6/32 DLCflexbar-PT-4a-06 849416 m, 7930 m/sec, 81952148 t fired, .

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DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
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23 LTL EXCL 174/224 10/32 DLCflexbar-PT-4a-06 1405320 m, 7936 m/sec, 136492284 t fired, .

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 179/224 10/32 DLCflexbar-PT-4a-06 1444842 m, 7904 m/sec, 140382935 t fired, .

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DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 184/224 11/32 DLCflexbar-PT-4a-06 1484124 m, 7856 m/sec, 144258351 t fired, .

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 189/224 11/32 DLCflexbar-PT-4a-06 1523440 m, 7863 m/sec, 148143808 t fired, .

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DLCflexbar-PT-4a-04: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 194/224 11/32 DLCflexbar-PT-4a-06 1563168 m, 7945 m/sec, 152025365 t fired, .

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DLCflexbar-PT-4a-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 199/224 12/32 DLCflexbar-PT-4a-06 1602508 m, 7868 m/sec, 155905790 t fired, .

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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 204/224 12/32 DLCflexbar-PT-4a-06 1643612 m, 8220 m/sec, 159803120 t fired, .

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DLCflexbar-PT-4a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 209/224 12/32 DLCflexbar-PT-4a-06 1684934 m, 8264 m/sec, 163693128 t fired, .

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DLCflexbar-PT-4a-03: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-04: LTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 214/224 12/32 DLCflexbar-PT-4a-06 1724902 m, 7993 m/sec, 167602289 t fired, .

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DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 219/224 13/32 DLCflexbar-PT-4a-06 1764132 m, 7846 m/sec, 171494307 t fired, .

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DLCflexbar-PT-4a-04: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-07: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-08: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 224/224 13/32 DLCflexbar-PT-4a-06 1803560 m, 7885 m/sec, 175371816 t fired, .

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: result : false
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DLCflexbar-PT-4a-14: LTL false LTL model checker

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 5/224 1/5 DLCflexbar-PT-4a-06 44100 m, -351892 m/sec, 4094551 t fired, .

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DLCflexbar-PT-4a-14: LTL false LTL model checker

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 10/224 1/5 DLCflexbar-PT-4a-06 86726 m, 8525 m/sec, 8171832 t fired, .

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DLCflexbar-PT-4a-14: LTL false LTL model checker

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DLCflexbar-PT-4a-06: LTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-4a-09: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-10: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 15/224 1/5 DLCflexbar-PT-4a-06 128943 m, 8443 m/sec, 12176468 t fired, .

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DLCflexbar-PT-4a-14: LTL false LTL model checker

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DLCflexbar-PT-4a-11: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 20/224 2/5 DLCflexbar-PT-4a-06 170512 m, 8313 m/sec, 16163441 t fired, .

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DLCflexbar-PT-4a-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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23 LTL EXCL 30/224 2/5 DLCflexbar-PT-4a-06 252560 m, 8221 m/sec, 24106821 t fired, .

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-15: LTL 0 1 0 0 1 0 0 0

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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
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DLCflexbar-PT-4a-13: CONJ 0 2 0 0 2 0 0 0
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/home/mcc/BenchKit/BenchKit_head.sh: line 62: 407 Killed lola --conf=$BIN_DIR/configfiles/ltlfireabilityconf --formula=$DIR/LTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-4a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038392900197"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4a.tgz
mv DLCflexbar-PT-4a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;