fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r061-tall-162038392900194
Last Updated
Jun 28, 2021

About the Execution of LoLA for DLCflexbar-PT-4a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16232.531 3250284.00 4720685.00 9060.00 F?T????????????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r061-tall-162038392900194.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is DLCflexbar-PT-4a, examination is CTLFireability
Time confinement is 3600 seconds

Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r061-tall-162038392900194
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.1M
-rw-r--r-- 1 mcc users 13K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 122K May 10 09:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 97K May 10 09:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Mar 28 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 28 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Mar 23 03:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 23 03:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Mar 22 13:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K Mar 22 13:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 09:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 09:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 3 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 1.7M May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1620810628346

starting LoLA
BK_INPUT DLCflexbar-PT-4a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCflexbar-PT-4a-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-4a-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620813878630

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 364 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
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lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 369 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
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DLCflexbar-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 374 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 0 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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10 CTL EXCL 2/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 7989 m, 1597 m/sec, 275374 t fired, .

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10 CTL EXCL 9/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 31786 m, 4759 m/sec, 1079252 t fired, .

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10 CTL EXCL 14/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 52059 m, 4054 m/sec, 1696582 t fired, .

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10 CTL EXCL 19/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 74458 m, 4479 m/sec, 2372730 t fired, .

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10 CTL EXCL 24/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 94179 m, 3944 m/sec, 3022789 t fired, .

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10 CTL EXCL 29/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 113937 m, 3951 m/sec, 3666959 t fired, .

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10 CTL EXCL 34/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 133473 m, 3907 m/sec, 4306603 t fired, .

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10 CTL EXCL 39/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 153581 m, 4021 m/sec, 4974195 t fired, .

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10 CTL EXCL 44/213 1/32 DLCflexbar-PT-4a-CTLFireability-03 176749 m, 4633 m/sec, 5607508 t fired, .

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10 CTL EXCL 49/213 2/32 DLCflexbar-PT-4a-CTLFireability-03 196882 m, 4026 m/sec, 6258470 t fired, .

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10 CTL EXCL 54/213 2/32 DLCflexbar-PT-4a-CTLFireability-03 217164 m, 4056 m/sec, 6879207 t fired, .

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10 CTL EXCL 59/213 2/32 DLCflexbar-PT-4a-CTLFireability-03 237925 m, 4152 m/sec, 7520737 t fired, .

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10 CTL EXCL 64/213 2/32 DLCflexbar-PT-4a-CTLFireability-03 262579 m, 4930 m/sec, 8165633 t fired, .

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10 CTL EXCL 69/213 2/32 DLCflexbar-PT-4a-CTLFireability-03 287195 m, 4923 m/sec, 8840054 t fired, .

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10 CTL EXCL 74/213 2/32 DLCflexbar-PT-4a-CTLFireability-03 307566 m, 4074 m/sec, 9481846 t fired, .

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10 CTL EXCL 79/213 2/32 DLCflexbar-PT-4a-CTLFireability-03 329639 m, 4414 m/sec, 10103796 t fired, .

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10 CTL EXCL 84/213 2/32 DLCflexbar-PT-4a-CTLFireability-03 351705 m, 4413 m/sec, 10728459 t fired, .

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10 CTL EXCL 89/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 373804 m, 4419 m/sec, 11399008 t fired, .

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10 CTL EXCL 94/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 396754 m, 4590 m/sec, 12071758 t fired, .

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10 CTL EXCL 99/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 416744 m, 3998 m/sec, 12713338 t fired, .

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10 CTL EXCL 104/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 435820 m, 3815 m/sec, 13344827 t fired, .

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10 CTL EXCL 109/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 456730 m, 4182 m/sec, 13985955 t fired, .

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10 CTL EXCL 114/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 477215 m, 4097 m/sec, 14580813 t fired, .

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10 CTL EXCL 119/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 497759 m, 4108 m/sec, 15206965 t fired, .

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10 CTL EXCL 124/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 518969 m, 4242 m/sec, 15850557 t fired, .

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10 CTL EXCL 129/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 539262 m, 4058 m/sec, 16493624 t fired, .

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10 CTL EXCL 134/213 3/32 DLCflexbar-PT-4a-CTLFireability-03 558873 m, 3922 m/sec, 17100825 t fired, .

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10 CTL EXCL 139/213 4/32 DLCflexbar-PT-4a-CTLFireability-03 577905 m, 3806 m/sec, 17710124 t fired, .

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10 CTL EXCL 144/213 4/32 DLCflexbar-PT-4a-CTLFireability-03 596930 m, 3805 m/sec, 18332293 t fired, .

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10 CTL EXCL 149/213 4/32 DLCflexbar-PT-4a-CTLFireability-03 615044 m, 3622 m/sec, 18966197 t fired, .

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10 CTL EXCL 154/213 4/32 DLCflexbar-PT-4a-CTLFireability-03 634283 m, 3847 m/sec, 19589286 t fired, .

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10 CTL EXCL 159/213 4/32 DLCflexbar-PT-4a-CTLFireability-03 655106 m, 4164 m/sec, 20222118 t fired, .

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10 CTL EXCL 164/213 4/32 DLCflexbar-PT-4a-CTLFireability-03 676164 m, 4211 m/sec, 20844516 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 174/213 4/32 DLCflexbar-PT-4a-CTLFireability-03 719018 m, 4226 m/sec, 22110587 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

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10 CTL EXCL 179/213 4/32 DLCflexbar-PT-4a-CTLFireability-03 738789 m, 3954 m/sec, 22730187 t fired, .

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10 CTL EXCL 184/213 5/32 DLCflexbar-PT-4a-CTLFireability-03 758557 m, 3953 m/sec, 23358399 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

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10 CTL EXCL 189/213 5/32 DLCflexbar-PT-4a-CTLFireability-03 779238 m, 4136 m/sec, 23985041 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 194/213 5/32 DLCflexbar-PT-4a-CTLFireability-03 799128 m, 3978 m/sec, 24604812 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 2 0 0 2 0 0 0

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10 CTL EXCL 199/213 5/32 DLCflexbar-PT-4a-CTLFireability-03 819844 m, 4143 m/sec, 25262490 t fired, .

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10 CTL EXCL 204/213 5/32 DLCflexbar-PT-4a-CTLFireability-03 839982 m, 4027 m/sec, 25877908 t fired, .

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10 CTL EXCL 209/213 5/32 DLCflexbar-PT-4a-CTLFireability-03 859424 m, 3888 m/sec, 26507447 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 4/213 1/5 DLCflexbar-PT-4a-CTLFireability-03 19206 m, -168043 m/sec, 650318 t fired, .

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10 CTL EXCL 9/213 1/5 DLCflexbar-PT-4a-CTLFireability-03 39011 m, 3961 m/sec, 1297653 t fired, .

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10 CTL EXCL 14/213 1/5 DLCflexbar-PT-4a-CTLFireability-03 60786 m, 4355 m/sec, 1949512 t fired, .

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10 CTL EXCL 19/213 1/5 DLCflexbar-PT-4a-CTLFireability-03 82167 m, 4276 m/sec, 2614190 t fired, .

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10 CTL EXCL 24/213 1/5 DLCflexbar-PT-4a-CTLFireability-03 101349 m, 3836 m/sec, 3274020 t fired, .

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10 CTL EXCL 29/213 1/5 DLCflexbar-PT-4a-CTLFireability-03 121133 m, 3956 m/sec, 3906906 t fired, .

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DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 94/213 3/5 DLCflexbar-PT-4a-CTLFireability-03 398627 m, 4295 m/sec, 12139315 t fired, .

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DLCflexbar-PT-4a-CTLFireability-00: CTL false CTL model checker
DLCflexbar-PT-4a-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 99/213 3/5 DLCflexbar-PT-4a-CTLFireability-03 419150 m, 4104 m/sec, 12784547 t fired, .

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DLCflexbar-PT-4a-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-4a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 104/213 3/5 DLCflexbar-PT-4a-CTLFireability-03 438032 m, 3776 m/sec, 13406920 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 109/213 3/5 DLCflexbar-PT-4a-CTLFireability-03 458221 m, 4037 m/sec, 14027788 t fired, .

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DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 114/213 3/5 DLCflexbar-PT-4a-CTLFireability-03 479508 m, 4257 m/sec, 14649711 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 119/213 3/5 DLCflexbar-PT-4a-CTLFireability-03 500580 m, 4214 m/sec, 15303061 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 124/213 3/5 DLCflexbar-PT-4a-CTLFireability-03 521493 m, 4182 m/sec, 15938176 t fired, .

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DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 129/213 3/5 DLCflexbar-PT-4a-CTLFireability-03 541724 m, 4046 m/sec, 16579181 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 134/213 4/5 DLCflexbar-PT-4a-CTLFireability-03 562810 m, 4217 m/sec, 17217531 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 139/213 4/5 DLCflexbar-PT-4a-CTLFireability-03 582469 m, 3931 m/sec, 17852632 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 144/213 4/5 DLCflexbar-PT-4a-CTLFireability-03 602593 m, 4024 m/sec, 18522248 t fired, .

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10 CTL EXCL 149/213 4/5 DLCflexbar-PT-4a-CTLFireability-03 621526 m, 3786 m/sec, 19171783 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 154/213 4/5 DLCflexbar-PT-4a-CTLFireability-03 642022 m, 4099 m/sec, 19803598 t fired, .

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10 CTL EXCL 174/213 4/5 DLCflexbar-PT-4a-CTLFireability-03 726470 m, 3935 m/sec, 22330952 t fired, .

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10 CTL EXCL 189/213 5/5 DLCflexbar-PT-4a-CTLFireability-03 786921 m, 4194 m/sec, 24223481 t fired, .

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10 CTL EXCL 209/213 5/5 DLCflexbar-PT-4a-CTLFireability-03 867797 m, 4201 m/sec, 26729401 t fired, .

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10 CTL EXCL 4/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 15203 m, -170518 m/sec, 507168 t fired, .
48 CTL EXCL 5/213 1/32 DLCflexbar-PT-4a-CTLFireability-15 2682 m, 536 m/sec, 160197 t fired, .

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10 CTL EXCL 9/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 28738 m, 2707 m/sec, 990330 t fired, .
48 CTL EXCL 10/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 5516 m, 566 m/sec, 343118 t fired, .

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DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 41033 m, 2459 m/sec, 1360034 t fired, .
48 CTL EXCL 16/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 7391 m, 375 m/sec, 462289 t fired, .

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DLCflexbar-PT-4a-CTLFireability-02: CTL true CTL model checker

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DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 54172 m, 2627 m/sec, 1760501 t fired, .
48 CTL EXCL 21/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 9593 m, 440 m/sec, 602341 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 66601 m, 2485 m/sec, 2117385 t fired, .
48 CTL EXCL 26/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 11450 m, 371 m/sec, 729241 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 77844 m, 2248 m/sec, 2473328 t fired, .
48 CTL EXCL 31/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 13216 m, 353 m/sec, 844689 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 35/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 88782 m, 2187 m/sec, 2843897 t fired, .
48 CTL EXCL 36/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 15141 m, 385 m/sec, 974416 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 40/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 102272 m, 2698 m/sec, 3307693 t fired, .
48 CTL EXCL 41/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 17633 m, 498 m/sec, 1149586 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 44/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 114742 m, 2494 m/sec, 3691103 t fired, .
48 CTL EXCL 45/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 19653 m, 404 m/sec, 1283306 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 50/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 125383 m, 2128 m/sec, 4048758 t fired, .
48 CTL EXCL 51/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 21425 m, 354 m/sec, 1406621 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 55/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 136315 m, 2186 m/sec, 4408674 t fired, .
48 CTL EXCL 56/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 23240 m, 363 m/sec, 1530973 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 60/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 152584 m, 3253 m/sec, 4939572 t fired, .
48 CTL EXCL 61/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 26243 m, 600 m/sec, 1739117 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 65/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 167801 m, 3043 m/sec, 5344269 t fired, .
48 CTL EXCL 66/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 28446 m, 440 m/sec, 1888057 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 70/2769 1/5 DLCflexbar-PT-4a-CTLFireability-03 179023 m, 2244 m/sec, 5691823 t fired, .
48 CTL EXCL 71/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 30192 m, 349 m/sec, 2010693 t fired, .

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10 CTL EXCL 75/2769 2/5 DLCflexbar-PT-4a-CTLFireability-03 196524 m, 3500 m/sec, 6246273 t fired, .
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10 CTL EXCL 140/2769 3/5 DLCflexbar-PT-4a-CTLFireability-03 393712 m, 2545 m/sec, 11968460 t fired, .
48 CTL EXCL 141/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 65465 m, 394 m/sec, 4407618 t fired, .

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48 CTL EXCL 146/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 67943 m, 495 m/sec, 4575463 t fired, .

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48 CTL EXCL 151/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 70302 m, 471 m/sec, 4737246 t fired, .

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48 CTL EXCL 156/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 72015 m, 342 m/sec, 4856432 t fired, .

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48 CTL EXCL 161/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 73940 m, 385 m/sec, 4990022 t fired, .

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10 CTL EXCL 170/2769 3/5 DLCflexbar-PT-4a-CTLFireability-03 469844 m, 3086 m/sec, 14371831 t fired, .
48 CTL EXCL 171/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 78214 m, 507 m/sec, 5289314 t fired, .

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10 CTL EXCL 175/2769 3/5 DLCflexbar-PT-4a-CTLFireability-03 482761 m, 2583 m/sec, 14752345 t fired, .
48 CTL EXCL 176/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 80145 m, 386 m/sec, 5418317 t fired, .

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48 CTL EXCL 196/197 1/32 DLCflexbar-PT-4a-CTLFireability-15 88545 m, 315 m/sec, 5993330 t fired, .

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DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 205/212 3/5 DLCflexbar-PT-4a-CTLFireability-03 553713 m, 1915 m/sec, 16958714 t fired, .
48 CTL EXCL 5/2568 1/5 DLCflexbar-PT-4a-CTLFireability-15 1148 m, -17479 m/sec, 64229 t fired, .

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DLCflexbar-PT-4a-CTLFireability-02: CTL true CTL model checker

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DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 210/212 4/5 DLCflexbar-PT-4a-CTLFireability-03 563213 m, 1900 m/sec, 17227863 t fired, .
48 CTL EXCL 10/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 2529 m, 276 m/sec, 150313 t fired, .

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DLCflexbar-PT-4a-CTLFireability-00: CTL false CTL model checker
DLCflexbar-PT-4a-CTLFireability-02: CTL true CTL model checker

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 15/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 4239 m, 342 m/sec, 261819 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 4/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 6580 m, -111326 m/sec, 238762 t fired, .
48 CTL EXCL 20/197 1/5 DLCflexbar-PT-4a-CTLFireability-15 5928 m, 337 m/sec, 369390 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 9/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 13535 m, 1391 m/sec, 454784 t fired, .
48 CTL EXCL 25/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 6947 m, 203 m/sec, 434806 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 14/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 23313 m, 1955 m/sec, 789387 t fired, .
48 CTL EXCL 30/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 8490 m, 308 m/sec, 530256 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 19/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 30707 m, 1478 m/sec, 1043943 t fired, .
48 CTL EXCL 35/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 9466 m, 195 m/sec, 594185 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 24/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 38061 m, 1470 m/sec, 1275804 t fired, .
48 CTL EXCL 40/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 10844 m, 275 m/sec, 687503 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 29/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 48350 m, 2057 m/sec, 1586984 t fired, .
48 CTL EXCL 45/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 12919 m, 415 m/sec, 827175 t fired, .

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DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 34/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 55275 m, 1385 m/sec, 1786246 t fired, .
48 CTL EXCL 50/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 13760 m, 168 m/sec, 881961 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 39/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 62568 m, 1458 m/sec, 2000751 t fired, .
48 CTL EXCL 55/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 14680 m, 184 m/sec, 944170 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 44/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 71279 m, 1742 m/sec, 2277894 t fired, .
48 CTL EXCL 60/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 16143 m, 292 m/sec, 1044969 t fired, .

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DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 49/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 81505 m, 2045 m/sec, 2587639 t fired, .
48 CTL EXCL 65/183 1/5 DLCflexbar-PT-4a-CTLFireability-15 18136 m, 398 m/sec, 1183222 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-00: CTL false CTL model checker
DLCflexbar-PT-4a-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: EFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CONJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 54/2553 1/5 DLCflexbar-PT-4a-CTLFireability-03 92429 m, 2184 m/sec, 2962616 t fired, .

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-4a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r061-tall-162038392900194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4a.tgz
mv DLCflexbar-PT-4a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;